From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cjWnM-000860-18 for qemu-devel@nongnu.org; Thu, 02 Mar 2017 14:53:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cjWnL-0002WW-5R for qemu-devel@nongnu.org; Thu, 02 Mar 2017 14:53:48 -0500 Received: from mail-wr0-x22b.google.com ([2a00:1450:400c:c0c::22b]:34533) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cjWnL-0002W6-05 for qemu-devel@nongnu.org; Thu, 02 Mar 2017 14:53:47 -0500 Received: by mail-wr0-x22b.google.com with SMTP id l37so60263651wrc.1 for ; Thu, 02 Mar 2017 11:53:46 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 2 Mar 2017 19:53:36 +0000 Message-Id: <20170302195337.31558-11-alex.bennee@linaro.org> In-Reply-To: <20170302195337.31558-1-alex.bennee@linaro.org> References: <20170302195337.31558-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2 10/11] target/arm/helper: make it clear the EC field is also in hex List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org, rth@twiddle.net, pbonzini@redhat.com Cc: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com, =?UTF-8?q?Alex=20Benn=C3=A9e?= , "open list:ARM" ..just like the rest of the displayed ESR register. Otherwise people might scratch their heads if a not obviously hex number is displayed for the EC field. Signed-off-by: Alex Bennée --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f4211b572..76b608f0ba 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6857,7 +6857,7 @@ void arm_cpu_do_interrupt(CPUState *cs) new_el); if (qemu_loglevel_mask(CPU_LOG_INT) && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n", + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", env->exception.syndrome >> ARM_EL_EC_SHIFT, env->exception.syndrome); } -- 2.11.0