* [Qemu-devel] [PATCH 1/5] target-mips: fix compiler warnings (clang 5)
2017-03-04 18:56 [Qemu-devel] [PATCH 0/5] target-mips: fixes, start using trace points Philippe Mathieu-Daudé
@ 2017-03-04 18:56 ` Philippe Mathieu-Daudé
2017-03-13 14:59 ` Yongbok Kim
2017-03-04 18:56 ` [Qemu-devel] [PATCH 2/5] target-mips: remove old & unuseful comments Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-03-04 18:56 UTC (permalink / raw)
To: Aurelien Jarno, Yongbok Kim; +Cc: Philippe Mathieu-Daudé, qemu-devel
static code analyzer complain:
target/mips/helper.c:453:5: warning: Function call argument is an uninitialized value
qemu_log_mask(CPU_LOG_MMU,
^~~~~~~~~~~~~~~~~~~~~~~~~~
'physical' and 'prot' are uninitialized if 'ret' is not TLBRET_MATCH.
Reported-by: Clang Static Analyzer
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/helper.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index d2e77958fd..e359ca3b44 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -450,10 +450,18 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
- qemu_log_mask(CPU_LOG_MMU,
- "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
- " prot %d\n",
- __func__, address, ret, physical, prot);
+ switch (ret) {
+ case TLBRET_MATCH:
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
+ " prot %d\n", __func__, address, physical, prot);
+ break;
+ default:
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
+ ret);
+ break;
+ }
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 1/5] target-mips: fix compiler warnings (clang 5)
2017-03-04 18:56 ` [Qemu-devel] [PATCH 1/5] target-mips: fix compiler warnings (clang 5) Philippe Mathieu-Daudé
@ 2017-03-13 14:59 ` Yongbok Kim
0 siblings, 0 replies; 11+ messages in thread
From: Yongbok Kim @ 2017-03-13 14:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aurelien Jarno; +Cc: qemu-devel
On 04/03/2017 18:56, Philippe Mathieu-Daudé wrote:
> static code analyzer complain:
>
> target/mips/helper.c:453:5: warning: Function call argument is an uninitialized value
> qemu_log_mask(CPU_LOG_MMU,
> ^~~~~~~~~~~~~~~~~~~~~~~~~~
>
> 'physical' and 'prot' are uninitialized if 'ret' is not TLBRET_MATCH.
>
> Reported-by: Clang Static Analyzer
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/helper.c | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index d2e77958fd..e359ca3b44 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -450,10 +450,18 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> access_type = ACCESS_INT;
> ret = get_physical_address(env, &physical, &prot,
> address, rw, access_type);
> - qemu_log_mask(CPU_LOG_MMU,
> - "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
> - " prot %d\n",
> - __func__, address, ret, physical, prot);
> + switch (ret) {
> + case TLBRET_MATCH:
> + qemu_log_mask(CPU_LOG_MMU,
> + "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx
> + " prot %d\n", __func__, address, physical, prot);
> + break;
> + default:
> + qemu_log_mask(CPU_LOG_MMU,
> + "%s address=%" VADDR_PRIx " ret %d\n", __func__, address,
> + ret);
> + break;
> + }
> if (ret == TLBRET_MATCH) {
> tlb_set_page(cs, address & TARGET_PAGE_MASK,
> physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 2/5] target-mips: remove old & unuseful comments
2017-03-04 18:56 [Qemu-devel] [PATCH 0/5] target-mips: fixes, start using trace points Philippe Mathieu-Daudé
2017-03-04 18:56 ` [Qemu-devel] [PATCH 1/5] target-mips: fix compiler warnings (clang 5) Philippe Mathieu-Daudé
@ 2017-03-04 18:56 ` Philippe Mathieu-Daudé
2017-03-13 15:00 ` Yongbok Kim
2017-03-04 18:56 ` [Qemu-devel] [PATCH 3/5] target-mips: log bad coprocessor0 register accesses with LOG_UNIMP Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-03-04 18:56 UTC (permalink / raw)
To: Aurelien Jarno, Yongbok Kim; +Cc: Philippe Mathieu-Daudé, qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8b4a072ecb..1fe0ff39f2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5137,7 +5137,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
rn = "ContextConfig";
goto cp0_unimplemented;
-// break;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_ld32s_tl(arg, cpu_env,
@@ -5791,7 +5790,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
rn = "ContextConfig";
goto cp0_unimplemented;
-// break;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
@@ -6454,7 +6452,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
rn = "ContextConfig";
goto cp0_unimplemented;
-// break;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
@@ -7092,7 +7089,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
rn = "ContextConfig";
goto cp0_unimplemented;
-// break;
case 2:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 2/5] target-mips: remove old & unuseful comments
2017-03-04 18:56 ` [Qemu-devel] [PATCH 2/5] target-mips: remove old & unuseful comments Philippe Mathieu-Daudé
@ 2017-03-13 15:00 ` Yongbok Kim
0 siblings, 0 replies; 11+ messages in thread
From: Yongbok Kim @ 2017-03-13 15:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aurelien Jarno; +Cc: qemu-devel
On 04/03/2017 18:56, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 8b4a072ecb..1fe0ff39f2 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -5137,7 +5137,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
> rn = "ContextConfig";
> goto cp0_unimplemented;
> -// break;
> case 2:
> CP0_CHECK(ctx->ulri);
> tcg_gen_ld32s_tl(arg, cpu_env,
> @@ -5791,7 +5790,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
> rn = "ContextConfig";
> goto cp0_unimplemented;
> -// break;
> case 2:
> CP0_CHECK(ctx->ulri);
> tcg_gen_st_tl(arg, cpu_env,
> @@ -6454,7 +6452,6 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
> rn = "ContextConfig";
> goto cp0_unimplemented;
> -// break;
> case 2:
> CP0_CHECK(ctx->ulri);
> tcg_gen_ld_tl(arg, cpu_env,
> @@ -7092,7 +7089,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> // gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
> rn = "ContextConfig";
> goto cp0_unimplemented;
> -// break;
> case 2:
> CP0_CHECK(ctx->ulri);
> tcg_gen_st_tl(arg, cpu_env,
>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 3/5] target-mips: log bad coprocessor0 register accesses with LOG_UNIMP
2017-03-04 18:56 [Qemu-devel] [PATCH 0/5] target-mips: fixes, start using trace points Philippe Mathieu-Daudé
2017-03-04 18:56 ` [Qemu-devel] [PATCH 1/5] target-mips: fix compiler warnings (clang 5) Philippe Mathieu-Daudé
2017-03-04 18:56 ` [Qemu-devel] [PATCH 2/5] target-mips: remove old & unuseful comments Philippe Mathieu-Daudé
@ 2017-03-04 18:56 ` Philippe Mathieu-Daudé
2017-03-13 15:00 ` Yongbok Kim
2017-03-04 18:56 ` [Qemu-devel] [PATCH 4/5] target-mips: replace break by goto cp0_unimplemented Philippe Mathieu-Daudé
2017-03-04 18:56 ` [Qemu-devel] [PATCH 5/5] target-mips: replace few LOG_DISAS() with trace points Philippe Mathieu-Daudé
4 siblings, 1 reply; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-03-04 18:56 UTC (permalink / raw)
To: Aurelien Jarno, Yongbok Kim; +Cc: Philippe Mathieu-Daudé, qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1fe0ff39f2..5c030a90cd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4872,7 +4872,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
tcg_gen_movi_tl(arg, 0);
}
@@ -4944,7 +4944,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
(void)rn; /* avoid a compiler warning */
cp0_unimplemented:
- LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
@@ -5627,7 +5627,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
gen_mfc0_unimplemented(ctx, arg);
}
@@ -6294,7 +6294,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
#if defined(TARGET_MIPS64)
@@ -6928,7 +6928,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
gen_mfc0_unimplemented(ctx, arg);
}
@@ -7593,7 +7593,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
return;
cp0_unimplemented:
- LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
#endif /* TARGET_MIPS64 */
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 3/5] target-mips: log bad coprocessor0 register accesses with LOG_UNIMP
2017-03-04 18:56 ` [Qemu-devel] [PATCH 3/5] target-mips: log bad coprocessor0 register accesses with LOG_UNIMP Philippe Mathieu-Daudé
@ 2017-03-13 15:00 ` Yongbok Kim
0 siblings, 0 replies; 11+ messages in thread
From: Yongbok Kim @ 2017-03-13 15:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aurelien Jarno; +Cc: qemu-devel
On 04/03/2017 18:56, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 1fe0ff39f2..5c030a90cd 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -4872,7 +4872,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> return;
>
> cp0_unimplemented:
> - LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + qemu_log_mask(LOG_UNIMP, "mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
> tcg_gen_movi_tl(arg, 0);
> }
>
> @@ -4944,7 +4944,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
>
> (void)rn; /* avoid a compiler warning */
> cp0_unimplemented:
> - LOG_DISAS("mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
> }
>
> static inline void gen_mfc0_unimplemented(DisasContext *ctx, TCGv arg)
> @@ -5627,7 +5627,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> return;
>
> cp0_unimplemented:
> - LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + qemu_log_mask(LOG_UNIMP, "mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
> gen_mfc0_unimplemented(ctx, arg);
> }
>
> @@ -6294,7 +6294,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> return;
>
> cp0_unimplemented:
> - LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + qemu_log_mask(LOG_UNIMP, "mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
> }
>
> #if defined(TARGET_MIPS64)
> @@ -6928,7 +6928,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> return;
>
> cp0_unimplemented:
> - LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + qemu_log_mask(LOG_UNIMP, "dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
> gen_mfc0_unimplemented(ctx, arg);
> }
>
> @@ -7593,7 +7593,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> return;
>
> cp0_unimplemented:
> - LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + qemu_log_mask(LOG_UNIMP, "dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
> }
> #endif /* TARGET_MIPS64 */
>
>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 4/5] target-mips: replace break by goto cp0_unimplemented
2017-03-04 18:56 [Qemu-devel] [PATCH 0/5] target-mips: fixes, start using trace points Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2017-03-04 18:56 ` [Qemu-devel] [PATCH 3/5] target-mips: log bad coprocessor0 register accesses with LOG_UNIMP Philippe Mathieu-Daudé
@ 2017-03-04 18:56 ` Philippe Mathieu-Daudé
2017-03-13 15:00 ` Yongbok Kim
2017-03-04 18:56 ` [Qemu-devel] [PATCH 5/5] target-mips: replace few LOG_DISAS() with trace points Philippe Mathieu-Daudé
4 siblings, 1 reply; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-03-04 18:56 UTC (permalink / raw)
To: Aurelien Jarno, Yongbok Kim; +Cc: Philippe Mathieu-Daudé, qemu-devel
this fixes many warnings like:
target/mips/translate.c:6253:13: warning: Value stored to 'rn' is never read
rn = "invalid sel";
^ ~~~~~~~~~~~~~
Reported-by: Clang Static Analyzer
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 88 ++++++++++++++++++++++++-------------------------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5c030a90cd..fc11e15a17 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5458,19 +5458,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 1:
// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
rn = "TraceControl";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
rn = "TraceControl2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
rn = "UserTraceData";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
rn = "TraceBPC";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -5496,31 +5496,31 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 1:
// gen_helper_mfc0_performance1(arg);
rn = "Performance1";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_mfc0_performance2(arg);
rn = "Performance2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_mfc0_performance3(arg);
rn = "Performance3";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_mfc0_performance4(arg);
rn = "Performance4";
-// break;
+ goto cp0_unimplemented;
case 5:
// gen_helper_mfc0_performance5(arg);
rn = "Performance5";
-// break;
+ goto cp0_unimplemented;
case 6:
// gen_helper_mfc0_performance6(arg);
rn = "Performance6";
-// break;
+ goto cp0_unimplemented;
case 7:
// gen_helper_mfc0_performance7(arg);
rn = "Performance7";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -6116,13 +6116,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
rn = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
-// break;
+ goto cp0_unimplemented;
case 3:
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
@@ -6130,13 +6130,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
rn = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -6161,31 +6161,31 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 1:
// gen_helper_mtc0_performance1(arg);
rn = "Performance1";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_performance2(arg);
rn = "Performance2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_performance3(arg);
rn = "Performance3";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_performance4(arg);
rn = "Performance4";
-// break;
+ goto cp0_unimplemented;
case 5:
// gen_helper_mtc0_performance5(arg);
rn = "Performance5";
-// break;
+ goto cp0_unimplemented;
case 6:
// gen_helper_mtc0_performance6(arg);
rn = "Performance6";
-// break;
+ goto cp0_unimplemented;
case 7:
// gen_helper_mtc0_performance7(arg);
rn = "Performance7";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -6766,19 +6766,19 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 1:
// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
rn = "TraceControl";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
rn = "TraceControl2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
rn = "UserTraceData";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
rn = "TraceBPC";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -6803,31 +6803,31 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 1:
// gen_helper_dmfc0_performance1(arg);
rn = "Performance1";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_dmfc0_performance2(arg);
rn = "Performance2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_dmfc0_performance3(arg);
rn = "Performance3";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_dmfc0_performance4(arg);
rn = "Performance4";
-// break;
+ goto cp0_unimplemented;
case 5:
// gen_helper_dmfc0_performance5(arg);
rn = "Performance5";
-// break;
+ goto cp0_unimplemented;
case 6:
// gen_helper_dmfc0_performance6(arg);
rn = "Performance6";
-// break;
+ goto cp0_unimplemented;
case 7:
// gen_helper_dmfc0_performance7(arg);
rn = "Performance7";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -7417,25 +7417,25 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceControl2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "UserTraceData";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
/* Stop translation as we may have switched the execution mode */
ctx->bstate = BS_STOP;
rn = "TraceBPC";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
@@ -7460,31 +7460,31 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 1:
// gen_helper_mtc0_performance1(cpu_env, arg);
rn = "Performance1";
-// break;
+ goto cp0_unimplemented;
case 2:
// gen_helper_mtc0_performance2(cpu_env, arg);
rn = "Performance2";
-// break;
+ goto cp0_unimplemented;
case 3:
// gen_helper_mtc0_performance3(cpu_env, arg);
rn = "Performance3";
-// break;
+ goto cp0_unimplemented;
case 4:
// gen_helper_mtc0_performance4(cpu_env, arg);
rn = "Performance4";
-// break;
+ goto cp0_unimplemented;
case 5:
// gen_helper_mtc0_performance5(cpu_env, arg);
rn = "Performance5";
-// break;
+ goto cp0_unimplemented;
case 6:
// gen_helper_mtc0_performance6(cpu_env, arg);
rn = "Performance6";
-// break;
+ goto cp0_unimplemented;
case 7:
// gen_helper_mtc0_performance7(cpu_env, arg);
rn = "Performance7";
-// break;
+ goto cp0_unimplemented;
default:
goto cp0_unimplemented;
}
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 4/5] target-mips: replace break by goto cp0_unimplemented
2017-03-04 18:56 ` [Qemu-devel] [PATCH 4/5] target-mips: replace break by goto cp0_unimplemented Philippe Mathieu-Daudé
@ 2017-03-13 15:00 ` Yongbok Kim
0 siblings, 0 replies; 11+ messages in thread
From: Yongbok Kim @ 2017-03-13 15:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aurelien Jarno; +Cc: qemu-devel
On 04/03/2017 18:56, Philippe Mathieu-Daudé wrote:
> this fixes many warnings like:
>
> target/mips/translate.c:6253:13: warning: Value stored to 'rn' is never read
> rn = "invalid sel";
> ^ ~~~~~~~~~~~~~
>
> Reported-by: Clang Static Analyzer
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/translate.c | 88 ++++++++++++++++++++++++-------------------------
> 1 file changed, 44 insertions(+), 44 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index 5c030a90cd..fc11e15a17 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -5458,19 +5458,19 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 1:
> // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
> rn = "TraceControl";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
> rn = "TraceControl2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
> rn = "UserTraceData";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
> rn = "TraceBPC";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -5496,31 +5496,31 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 1:
> // gen_helper_mfc0_performance1(arg);
> rn = "Performance1";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_mfc0_performance2(arg);
> rn = "Performance2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_mfc0_performance3(arg);
> rn = "Performance3";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_mfc0_performance4(arg);
> rn = "Performance4";
> -// break;
> + goto cp0_unimplemented;
> case 5:
> // gen_helper_mfc0_performance5(arg);
> rn = "Performance5";
> -// break;
> + goto cp0_unimplemented;
> case 6:
> // gen_helper_mfc0_performance6(arg);
> rn = "Performance6";
> -// break;
> + goto cp0_unimplemented;
> case 7:
> // gen_helper_mfc0_performance7(arg);
> rn = "Performance7";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -6116,13 +6116,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> rn = "TraceControl";
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
> rn = "TraceControl2";
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> -// break;
> + goto cp0_unimplemented;
> case 3:
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> @@ -6130,13 +6130,13 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> rn = "UserTraceData";
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> rn = "TraceBPC";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -6161,31 +6161,31 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 1:
> // gen_helper_mtc0_performance1(arg);
> rn = "Performance1";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_performance2(arg);
> rn = "Performance2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_mtc0_performance3(arg);
> rn = "Performance3";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_performance4(arg);
> rn = "Performance4";
> -// break;
> + goto cp0_unimplemented;
> case 5:
> // gen_helper_mtc0_performance5(arg);
> rn = "Performance5";
> -// break;
> + goto cp0_unimplemented;
> case 6:
> // gen_helper_mtc0_performance6(arg);
> rn = "Performance6";
> -// break;
> + goto cp0_unimplemented;
> case 7:
> // gen_helper_mtc0_performance7(arg);
> rn = "Performance7";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -6766,19 +6766,19 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 1:
> // gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
> rn = "TraceControl";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
> rn = "TraceControl2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
> rn = "UserTraceData";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
> rn = "TraceBPC";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -6803,31 +6803,31 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 1:
> // gen_helper_dmfc0_performance1(arg);
> rn = "Performance1";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_dmfc0_performance2(arg);
> rn = "Performance2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_dmfc0_performance3(arg);
> rn = "Performance3";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_dmfc0_performance4(arg);
> rn = "Performance4";
> -// break;
> + goto cp0_unimplemented;
> case 5:
> // gen_helper_dmfc0_performance5(arg);
> rn = "Performance5";
> -// break;
> + goto cp0_unimplemented;
> case 6:
> // gen_helper_dmfc0_performance6(arg);
> rn = "Performance6";
> -// break;
> + goto cp0_unimplemented;
> case 7:
> // gen_helper_dmfc0_performance7(arg);
> rn = "Performance7";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -7417,25 +7417,25 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> rn = "TraceControl";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> rn = "TraceControl2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> rn = "UserTraceData";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
> /* Stop translation as we may have switched the execution mode */
> ctx->bstate = BS_STOP;
> rn = "TraceBPC";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
> @@ -7460,31 +7460,31 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case 1:
> // gen_helper_mtc0_performance1(cpu_env, arg);
> rn = "Performance1";
> -// break;
> + goto cp0_unimplemented;
> case 2:
> // gen_helper_mtc0_performance2(cpu_env, arg);
> rn = "Performance2";
> -// break;
> + goto cp0_unimplemented;
> case 3:
> // gen_helper_mtc0_performance3(cpu_env, arg);
> rn = "Performance3";
> -// break;
> + goto cp0_unimplemented;
> case 4:
> // gen_helper_mtc0_performance4(cpu_env, arg);
> rn = "Performance4";
> -// break;
> + goto cp0_unimplemented;
> case 5:
> // gen_helper_mtc0_performance5(cpu_env, arg);
> rn = "Performance5";
> -// break;
> + goto cp0_unimplemented;
> case 6:
> // gen_helper_mtc0_performance6(cpu_env, arg);
> rn = "Performance6";
> -// break;
> + goto cp0_unimplemented;
> case 7:
> // gen_helper_mtc0_performance7(cpu_env, arg);
> rn = "Performance7";
> -// break;
> + goto cp0_unimplemented;
> default:
> goto cp0_unimplemented;
> }
>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH 5/5] target-mips: replace few LOG_DISAS() with trace points
2017-03-04 18:56 [Qemu-devel] [PATCH 0/5] target-mips: fixes, start using trace points Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2017-03-04 18:56 ` [Qemu-devel] [PATCH 4/5] target-mips: replace break by goto cp0_unimplemented Philippe Mathieu-Daudé
@ 2017-03-04 18:56 ` Philippe Mathieu-Daudé
2017-03-13 15:00 ` Yongbok Kim
4 siblings, 1 reply; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-03-04 18:56 UTC (permalink / raw)
To: Aurelien Jarno, Yongbok Kim; +Cc: Philippe Mathieu-Daudé, qemu-devel
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
Makefile.objs | 1 +
target/mips/trace-events | 5 +++++
target/mips/translate.c | 25 +++++++++++--------------
3 files changed, 17 insertions(+), 14 deletions(-)
create mode 100644 target/mips/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index e740500e2d..6167e7b17d 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -157,6 +157,7 @@ trace-events-subdirs += audio
trace-events-subdirs += net
trace-events-subdirs += target/arm
trace-events-subdirs += target/i386
+trace-events-subdirs += target/mips
trace-events-subdirs += target/sparc
trace-events-subdirs += target/s390x
trace-events-subdirs += target/ppc
diff --git a/target/mips/trace-events b/target/mips/trace-events
new file mode 100644
index 0000000000..43824089b3
--- /dev/null
+++ b/target/mips/trace-events
@@ -0,0 +1,5 @@
+# See docs/tracing.txt for syntax documentation.
+
+# target/mips/translate.c
+mips_translate_c0(const char *instr, const char *rn, int reg, int sel) "%s %s (reg %d sel %d)"
+mips_translate_tr(const char *instr, int rt, int u, int sel, int h) "%s (reg %d u %d sel %d h %d)"
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fc11e15a17..78b7264add 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -33,6 +33,7 @@
#include "sysemu/kvm.h"
#include "exec/semihost.h"
+#include "target/mips/trace.h"
#include "trace-tcg.h"
#include "exec/log.h"
@@ -4866,9 +4867,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
-
- (void)rn; /* avoid a compiler warning */
- LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ trace_mips_translate_c0("mfhc0", rn, reg, sel);
return;
cp0_unimplemented:
@@ -4941,8 +4940,8 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
+ trace_mips_translate_c0("mthc0", rn, reg, sel);
- (void)rn; /* avoid a compiler warning */
cp0_unimplemented:
qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
}
@@ -5622,8 +5621,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- (void)rn; /* avoid a compiler warning */
- LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ trace_mips_translate_c0("mfc0", rn, reg, sel);
return;
cp0_unimplemented:
@@ -6284,8 +6282,8 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- (void)rn; /* avoid a compiler warning */
- LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ trace_mips_translate_c0("mtc0", rn, reg, sel);
+
/* For simplicity assume that all writes can cause interrupts. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
@@ -6923,8 +6921,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- (void)rn; /* avoid a compiler warning */
- LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ trace_mips_translate_c0("dmfc0", rn, reg, sel);
return;
cp0_unimplemented:
@@ -7583,8 +7580,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
default:
goto cp0_unimplemented;
}
- (void)rn; /* avoid a compiler warning */
- LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
+ trace_mips_translate_c0("dmtc0", rn, reg, sel);
+
/* For simplicity assume that all writes can cause interrupts. */
if (ctx->tb->cflags & CF_USE_ICOUNT) {
gen_io_end();
@@ -7803,7 +7800,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
default:
goto die;
}
- LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
+ trace_mips_translate_tr("mftr", rt, u, sel, h);
gen_store_gpr(t0, rd);
tcg_temp_free(t0);
return;
@@ -8008,7 +8005,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
default:
goto die;
}
- LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
+ trace_mips_translate_tr("mttr", rd, u, sel, h);
tcg_temp_free(t0);
return;
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH 5/5] target-mips: replace few LOG_DISAS() with trace points
2017-03-04 18:56 ` [Qemu-devel] [PATCH 5/5] target-mips: replace few LOG_DISAS() with trace points Philippe Mathieu-Daudé
@ 2017-03-13 15:00 ` Yongbok Kim
0 siblings, 0 replies; 11+ messages in thread
From: Yongbok Kim @ 2017-03-13 15:00 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Aurelien Jarno; +Cc: qemu-devel
On 04/03/2017 18:56, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> Makefile.objs | 1 +
> target/mips/trace-events | 5 +++++
> target/mips/translate.c | 25 +++++++++++--------------
> 3 files changed, 17 insertions(+), 14 deletions(-)
> create mode 100644 target/mips/trace-events
>
> diff --git a/Makefile.objs b/Makefile.objs
> index e740500e2d..6167e7b17d 100644
> --- a/Makefile.objs
> +++ b/Makefile.objs
> @@ -157,6 +157,7 @@ trace-events-subdirs += audio
> trace-events-subdirs += net
> trace-events-subdirs += target/arm
> trace-events-subdirs += target/i386
> +trace-events-subdirs += target/mips
> trace-events-subdirs += target/sparc
> trace-events-subdirs += target/s390x
> trace-events-subdirs += target/ppc
> diff --git a/target/mips/trace-events b/target/mips/trace-events
> new file mode 100644
> index 0000000000..43824089b3
> --- /dev/null
> +++ b/target/mips/trace-events
> @@ -0,0 +1,5 @@
> +# See docs/tracing.txt for syntax documentation.
> +
> +# target/mips/translate.c
> +mips_translate_c0(const char *instr, const char *rn, int reg, int sel) "%s %s (reg %d sel %d)"
> +mips_translate_tr(const char *instr, int rt, int u, int sel, int h) "%s (reg %d u %d sel %d h %d)"
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index fc11e15a17..78b7264add 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -33,6 +33,7 @@
> #include "sysemu/kvm.h"
> #include "exec/semihost.h"
>
> +#include "target/mips/trace.h"
> #include "trace-tcg.h"
> #include "exec/log.h"
>
> @@ -4866,9 +4867,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> default:
> goto cp0_unimplemented;
> }
> -
> - (void)rn; /* avoid a compiler warning */
> - LOG_DISAS("mfhc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + trace_mips_translate_c0("mfhc0", rn, reg, sel);
> return;
>
> cp0_unimplemented:
> @@ -4941,8 +4940,8 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> default:
> goto cp0_unimplemented;
> }
> + trace_mips_translate_c0("mthc0", rn, reg, sel);
>
> - (void)rn; /* avoid a compiler warning */
> cp0_unimplemented:
> qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", rn, reg, sel);
> }
> @@ -5622,8 +5621,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> default:
> goto cp0_unimplemented;
> }
> - (void)rn; /* avoid a compiler warning */
> - LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + trace_mips_translate_c0("mfc0", rn, reg, sel);
> return;
>
> cp0_unimplemented:
> @@ -6284,8 +6282,8 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> default:
> goto cp0_unimplemented;
> }
> - (void)rn; /* avoid a compiler warning */
> - LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + trace_mips_translate_c0("mtc0", rn, reg, sel);
> +
> /* For simplicity assume that all writes can cause interrupts. */
> if (ctx->tb->cflags & CF_USE_ICOUNT) {
> gen_io_end();
> @@ -6923,8 +6921,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> default:
> goto cp0_unimplemented;
> }
> - (void)rn; /* avoid a compiler warning */
> - LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + trace_mips_translate_c0("dmfc0", rn, reg, sel);
> return;
>
> cp0_unimplemented:
> @@ -7583,8 +7580,8 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> default:
> goto cp0_unimplemented;
> }
> - (void)rn; /* avoid a compiler warning */
> - LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
> + trace_mips_translate_c0("dmtc0", rn, reg, sel);
> +
> /* For simplicity assume that all writes can cause interrupts. */
> if (ctx->tb->cflags & CF_USE_ICOUNT) {
> gen_io_end();
> @@ -7803,7 +7800,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
> default:
> goto die;
> }
> - LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
> + trace_mips_translate_tr("mftr", rt, u, sel, h);
> gen_store_gpr(t0, rd);
> tcg_temp_free(t0);
> return;
> @@ -8008,7 +8005,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
> default:
> goto die;
> }
> - LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
> + trace_mips_translate_tr("mttr", rd, u, sel, h);
> tcg_temp_free(t0);
> return;
>
>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
^ permalink raw reply [flat|nested] 11+ messages in thread