From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: agraf@suse.de, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 3/5] target/ppc: fmadd check for excp independently
Date: Mon, 6 Mar 2017 15:08:21 +1100 [thread overview]
Message-ID: <20170306040823.28482-4-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20170306040823.28482-1-david@gibson.dropbear.id.au>
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Current order of checking does not confirm with the spec
(ISA 3.0: MultiplyAddDP page-469). Change the order and make them
independent of each other.
For example: a = infinity, b = zero, c = SNaN, this should set both
VXIMZ and VXNAN
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0535ad0..a547f58 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -747,17 +747,21 @@ static void float64_maddsub_update_excp(CPUPPCState *env, float64 arg1,
float64 arg2, float64 arg3,
unsigned int madd_flags)
{
+ if (unlikely(float64_is_signaling_nan(arg1, &env->fp_status) ||
+ float64_is_signaling_nan(arg2, &env->fp_status) ||
+ float64_is_signaling_nan(arg3, &env->fp_status))) {
+ /* sNaN operation */
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ }
+
if (unlikely((float64_is_infinity(arg1) && float64_is_zero(arg2)) ||
(float64_is_zero(arg1) && float64_is_infinity(arg2)))) {
/* Multiplication of zero by infinity */
- arg1 = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
- } else if (unlikely(float64_is_signaling_nan(arg1, &env->fp_status) ||
- float64_is_signaling_nan(arg2, &env->fp_status) ||
- float64_is_signaling_nan(arg3, &env->fp_status))) {
- /* sNaN operation */
- float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
- } else if ((float64_is_infinity(arg1) || float64_is_infinity(arg2)) &&
- float64_is_infinity(arg3)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
+ }
+
+ if ((float64_is_infinity(arg1) || float64_is_infinity(arg2)) &&
+ float64_is_infinity(arg3)) {
uint8_t aSign, bSign, cSign;
aSign = float64_is_neg(arg1);
--
2.9.3
next prev parent reply other threads:[~2017-03-06 4:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-06 4:08 [Qemu-devel] [PULL 0/5] ppc-for-2.9 queue 20170306 David Gibson
2017-03-06 4:08 ` [Qemu-devel] [PULL 1/5] ppc/xics: register reset handlers for the ICP and ICS objects David Gibson
2017-03-06 4:08 ` [Qemu-devel] [PULL 2/5] spapr: ensure that all threads within core are on the same NUMA node David Gibson
2017-03-06 4:08 ` David Gibson [this message]
2017-03-06 4:08 ` [Qemu-devel] [PULL 4/5] target/ppc: fmadd: add macro for updating flags David Gibson
2017-03-06 4:08 ` [Qemu-devel] [PULL 5/5] target/ppc: use helper for excp handling David Gibson
2017-03-06 15:12 ` [Qemu-devel] [PULL 0/5] ppc-for-2.9 queue 20170306 Peter Maydell
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