From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH for-2.10 1/8] ppc/xics: add a xics_get_cpu_index_by_pir() helper
Date: Tue, 14 Mar 2017 16:38:56 +1100 [thread overview]
Message-ID: <20170314053856.GH12564@umbus.fritz.box> (raw)
In-Reply-To: <1488970371-8865-2-git-send-email-clg@kaod.org>
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On Wed, Mar 08, 2017 at 11:52:44AM +0100, Cédric Le Goater wrote:
> This helper will be used to translate the server number of the XIVE
> (which is a PIR) into an ICPState index number (which is a cpu index).
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This seems a slightly roundabout way of doing things. Why not just
have the vcpu_by_pir() interface, then have the XICSFabric implementor
go directly from PIR to xics server state.
> ---
> hw/intc/xics.c | 11 +++++++++++
> hw/ppc/ppc.c | 16 ++++++++++++++++
> include/hw/ppc/xics.h | 1 +
> target/ppc/cpu.h | 10 ++++++++++
> 4 files changed, 38 insertions(+)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index e740989a1162..209e1a75ecb9 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -49,6 +49,17 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
> return -1;
> }
>
> +int xics_get_cpu_index_by_pir(int pir)
> +{
> + PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
> +
> + if (cpu) {
> + return cpu->parent_obj.cpu_index;
> + }
> +
> + return -1;
> +}
> +
> void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
> {
> CPUState *cs = CPU(cpu);
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index 5f93083d4a16..94bbe382a73a 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -1379,6 +1379,22 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
> return NULL;
> }
>
> +PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
> +{
> + CPUState *cs;
> +
> + CPU_FOREACH(cs) {
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *env = &cpu->env;
> +
> + if (env->spr_cb[SPR_PIR].default_value == pir) {
> + return cpu;
> + }
> + }
> +
> + return NULL;
> +}
> +
> void ppc_cpu_parse_features(const char *cpu_model)
> {
> CPUClass *cc;
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 9a5e715fe553..42bd24e975cb 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -173,6 +173,7 @@ void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu);
>
> /* Internal XICS interfaces */
> int xics_get_cpu_index_by_dt_id(int cpu_dt_id);
> +int xics_get_cpu_index_by_pir(int pir);
>
> void icp_set_cppr(ICPState *icp, uint8_t cppr);
> void icp_set_mfrr(ICPState *icp, uint8_t mfrr);
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 7c4a1f50b38b..24a5af95cb45 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2518,5 +2518,15 @@ int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
> */
> PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
>
> +/**
> + * ppc_get_vcpu_by_pir_id:
> + * @pir: Processor Identifier Register (SPR_PIR)
> + *
> + * Searches for a CPU by @pir.
> + *
> + * Returns: a PowerPCCPU struct
> + */
> +PowerPCCPU *ppc_get_vcpu_by_pir(int pir);
> +
> void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
> #endif /* PPC_CPU_H */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2017-03-14 5:55 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-08 10:52 [Qemu-devel] [PATCH for-2.10 0/8] ppc/pnv: interrupt controller (POWER8) Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 1/8] ppc/xics: add a xics_get_cpu_index_by_pir() helper Cédric Le Goater
2017-03-14 5:38 ` David Gibson [this message]
2017-03-14 8:11 ` Cédric Le Goater
2017-03-14 17:00 ` Cédric Le Goater
2017-03-15 4:53 ` David Gibson
2017-03-15 10:04 ` Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 2/8] ppc/xics: add an ics_eoi() handler to XICSFabric Cédric Le Goater
2017-03-14 5:40 ` David Gibson
2017-03-14 8:12 ` Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 3/8] ppc/pnv: create the ICP and ICS objects under the machine Cédric Le Goater
2017-03-14 5:45 ` David Gibson
2017-03-14 9:47 ` Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 4/8] ppc/pnv: add memory regions for the ICP registers Cédric Le Goater
2017-03-08 11:24 ` Philippe Mathieu-Daudé
2017-03-08 13:33 ` Cédric Le Goater
2017-03-14 5:49 ` David Gibson
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 5/8] ppc/pnv: map the ICP memory regions Cédric Le Goater
2017-03-14 5:52 ` David Gibson
2017-03-14 10:02 ` Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 6/8] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt Cédric Le Goater
2017-03-15 6:16 ` David Gibson
2017-03-15 9:38 ` Benjamin Herrenschmidt
2017-03-16 13:52 ` Cédric Le Goater
2017-03-17 2:00 ` David Gibson
2017-03-17 8:27 ` Cédric Le Goater
2017-03-21 13:36 ` Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 7/8] ppc/pnv: Add OCC model stub with interrupt support Cédric Le Goater
2017-03-08 10:52 ` [Qemu-devel] [PATCH for-2.10 8/8] ppc/pnv: Add support for POWER8+ LPC Controller Cédric Le Goater
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