From: Tim 'mithro' Ansell <mithro@mithis.com>
To: qemu-devel@nongnu.org
Cc: Tim 'mithro' Ansell <mithro@mithis.com>, shorne@gmail.com
Subject: [Qemu-devel] [PATCH 0/2] targets/openrisc: Improve exception vectoring.
Date: Tue, 18 Apr 2017 16:15:49 +1000 [thread overview]
Message-ID: <20170418061551.196582-1-mithro@mithis.com> (raw)
Hi,
This patch series improves the exception vectoring on the OpenRISC platform by
adding support for both the EVBAR register and EPH bit.
This is my first patch to upstream QEMU, so please do point of if I have done
anything silly.
Tim 'mithro' Ansell (2):
target/openrisc: Implement EVBAR register
target/openrisc: Implement EPH bit
target/openrisc/cpu.c | 2 ++
target/openrisc/cpu.h | 7 +++++++
target/openrisc/interrupt.c | 9 ++++++++-
target/openrisc/sys_helper.c | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)
--
2.12.1
next reply other threads:[~2017-04-18 6:17 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-18 6:15 Tim 'mithro' Ansell [this message]
2017-04-18 6:15 ` [Qemu-devel] [PATCH 1/2] target/openrisc: Implement EVBAR register Tim 'mithro' Ansell
2017-04-18 12:47 ` Stafford Horne
2017-04-20 7:00 ` Richard Henderson
2017-04-27 0:55 ` Tim Ansell
2017-04-27 21:18 ` Stafford Horne
2017-04-18 6:15 ` [Qemu-devel] [PATCH 2/2] target/openrisc: Implement EPH bit Tim 'mithro' Ansell
2017-04-18 12:40 ` Stafford Horne
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