From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1d3W62-00061P-LU for qemu-devel@nongnu.org; Wed, 26 Apr 2017 19:11:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1d3W61-0003U6-BN for qemu-devel@nongnu.org; Wed, 26 Apr 2017 19:11:42 -0400 Date: Wed, 26 Apr 2017 19:11:32 -0400 From: "Emilio G. Cota" Message-ID: <20170426231132.GC16014@flamenco> References: <1493187803-4510-1-git-send-email-cota@braap.org> <1493187803-4510-2-git-send-email-cota@braap.org> <20170426215604.GA16014@flamenco> <22fb44cc-b8de-c3fb-0980-bfc908229a2e@twiddle.net> <20170426224531.GB16014@flamenco> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170426224531.GB16014@flamenco> Subject: Re: [Qemu-devel] [PATCH v3 01/10] tcg-runtime: add lookup_tb_ptr helper List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, Paolo Bonzini , Peter Crosthwaite , Peter Maydell , Eduardo Habkost , Andrzej Zaborowski , Aurelien Jarno , Alexander Graf , Stefan Weil , qemu-arm@nongnu.org, alex.bennee@linaro.org, Pranith Kumar On Wed, Apr 26, 2017 at 18:45:31 -0400, Emilio G. Cota wrote: > On Thu, Apr 27, 2017 at 00:29:49 +0200, Richard Henderson wrote: > > On 04/26/2017 11:56 PM, Emilio G. Cota wrote: > > >On Wed, Apr 26, 2017 at 10:40:45 +0200, Richard Henderson wrote: > > >>On 04/26/2017 08:23 AM, Emilio G. Cota wrote: > > >(snip) > > >>>+ cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); > > >>>+ tb = atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(addr)]); > > >>>+ if (likely(tb && tb->pc == addr && tb->cs_base == cs_base && > > >>>+ tb->flags == flags)) { > > >> > > >>This comparison is wrong. It will incorrectly reject a TB for i386 guest > > >>when CS_BASE != 0. You really want > > >> > > >> tb = atomic_rcu_read(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(addr)]); > > >> if (tb) { > > >> cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); > > >> if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags) { > > >> return tb->tc_ptr; > > >> } > > >> } > > >> return tcg_ctx.code_gen_epilogue; > > > > > >wrt the comparison, the only change I notice in your suggested change is > > > tb->pc == pc > > > > > >instead of > > > tb->pc == addr > > > > > >, which seems innocuous to me (since tb->pc == addr). > > > > > >I fail to see how this relates to your "CS_BASE != 0" comment. > > >What am I missing? > > > > Recall how you computed vaddr for target/i386: > > > > addr = pc + cs_base > > I see, thanks! Hmm TB's are added to tb_jmp_cache by pc, not by pc + cs_base: atomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); Shouldn't we then pass just the pc (without adding cs_base) to lookup_ptr, then? i.e. --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -2533,11 +2533,7 @@ gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, TCGv jr) } else if (s->tf) { gen_helper_single_step(cpu_env); } else if (!TCGV_IS_UNUSED(jr)) { - TCGv vaddr = tcg_temp_new(); - - tcg_gen_add_tl(vaddr, jr, cpu_seg_base[R_CS]); - tcg_gen_lookup_and_goto_ptr(vaddr); - tcg_temp_free(vaddr); + tcg_gen_lookup_and_goto_ptr(jr); } else { tcg_gen_exit_tb(0); } And while at it, rename the "addr" argument in lookup_ptr to "pc". Hmm? E.