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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: cota@braap.org
Subject: [Qemu-devel] [PATCH v6 03/25] qemu/atomic: Loosen restrictions for 64-bit ILP32 hosts
Date: Tue,  2 May 2017 12:22:38 -0700	[thread overview]
Message-ID: <20170502192300.2124-4-rth@twiddle.net> (raw)
In-Reply-To: <20170502192300.2124-1-rth@twiddle.net>

We need to coordinate with the TCG_OVERSIZED_GUEST test in cputlb.c,
and allow 64-bit atomics even though sizeof(void *) == 4.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 include/qemu/atomic.h | 34 ++++++++++++++++++++++++++--------
 1 file changed, 26 insertions(+), 8 deletions(-)

diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
index 878fa07..e07c797 100644
--- a/include/qemu/atomic.h
+++ b/include/qemu/atomic.h
@@ -88,6 +88,24 @@
 #define smp_read_barrier_depends()   barrier()
 #endif
 
+/* Sanity check that the size of an atomic operation isn't "overly large".
+ * Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
+ * want to use them because we ought not need them, and this lets us do a
+ * bit of sanity checking that other 32-bit hosts might build.
+ *
+ * That said, we have a problem on 64-bit ILP32 hosts in that in order to
+ * sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
+ * We'd prefer not want to pull in everything else TCG related, so handle
+ * those few cases by hand.
+ *
+ * Note that x32 is fully detected with __x64_64__ + _ILP32, and that for
+ * Sparc we always force the use of sparcv9 in configure.
+ */
+#if defined(__x86_64__) || defined(__sparc__)
+# define ATOMIC_REG_SIZE  8
+#else
+# define ATOMIC_REG_SIZE  sizeof(void *)
+#endif
 
 /* Weak atomic operations prevent the compiler moving other
  * loads/stores past the atomic operation load/store. However there is
@@ -104,7 +122,7 @@
 
 #define atomic_read(ptr)                              \
     ({                                                \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
     atomic_read__nocheck(ptr);                        \
     })
 
@@ -112,7 +130,7 @@
     __atomic_store_n(ptr, i, __ATOMIC_RELAXED)
 
 #define atomic_set(ptr, i)  do {                      \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
     atomic_set__nocheck(ptr, i);                      \
 } while(0)
 
@@ -130,27 +148,27 @@
 
 #define atomic_rcu_read(ptr)                          \
     ({                                                \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
     typeof_strip_qual(*ptr) _val;                     \
     atomic_rcu_read__nocheck(ptr, &_val);             \
     _val;                                             \
     })
 
 #define atomic_rcu_set(ptr, i) do {                   \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *)); \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
     __atomic_store_n(ptr, i, __ATOMIC_RELEASE);       \
 } while(0)
 
 #define atomic_load_acquire(ptr)                        \
     ({                                                  \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);  \
     typeof_strip_qual(*ptr) _val;                       \
     __atomic_load(ptr, &_val, __ATOMIC_ACQUIRE);        \
     _val;                                               \
     })
 
 #define atomic_store_release(ptr, i)  do {              \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));   \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);  \
     __atomic_store_n(ptr, i, __ATOMIC_RELEASE);         \
 } while(0)
 
@@ -162,7 +180,7 @@
 })
 
 #define atomic_xchg(ptr, i)    ({                           \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));       \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);      \
     atomic_xchg__nocheck(ptr, i);                           \
 })
 
@@ -175,7 +193,7 @@
 })
 
 #define atomic_cmpxchg(ptr, old, new)    ({                             \
-    QEMU_BUILD_BUG_ON(sizeof(*ptr) > sizeof(void *));                   \
+    QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE);                  \
     atomic_cmpxchg__nocheck(ptr, old, new);                             \
 })
 
-- 
2.9.3

  parent reply	other threads:[~2017-05-02 19:23 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-02 19:22 [Qemu-devel] [PATCH v6 00/25] tcg cross-tb optimizations Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 01/25] target/nios2: Fix 64-bit ilp32 compilation Richard Henderson
2017-05-05 11:51   ` Philippe Mathieu-Daudé
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 02/25] tcg/sparc: Use the proper compilation flags for 32-bit Richard Henderson
2017-05-02 19:22 ` Richard Henderson [this message]
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 04/25] tcg: Introduce goto_ptr opcode and tcg_gen_lookup_and_goto_ptr Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 05/25] tcg/i386: implement goto_ptr Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 06/25] target/arm: optimize cross-page direct jumps in softmmu Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 07/25] target/arm: optimize indirect branches Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 08/25] target/i386: introduce gen_jr helper to generate lookup_and_goto_ptr Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 09/25] target/i386: optimize cross-page direct jumps in softmmu Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 10/25] target/i386: optimize indirect branches Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 11/25] tb-hash: improve tb_jmp_cache hash function in user mode Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 12/25] tcg/ppc: Implement goto_ptr Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 13/25] tcg/aarch64: " Richard Henderson
2017-05-06 11:52   ` Aurelien Jarno
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 14/25] tcg/sparc: " Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 15/25] tcg/s390: " Richard Henderson
2017-05-06 12:15   ` Aurelien Jarno
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 16/25] tcg/arm: Clarify tcg_out_bx for arm4 host Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 17/25] tcg/arm: Implement goto_ptr Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 18/25] target/s390: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2017-05-06 12:14   ` Aurelien Jarno
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 19/25] target/hppa: " Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 20/25] target/alpha: " Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 21/25] target/aarch64: optimize cross-page direct jumps in softmmu Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 22/25] target/aarch64: optimize indirect branches Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 23/25] tcg/mips: implement goto_ptr Richard Henderson
2017-05-02 19:22 ` [Qemu-devel] [PATCH v6 24/25] target/mips: optimize cross-page direct jumps in softmmu Richard Henderson
2017-05-02 19:23 ` [Qemu-devel] [PATCH v6 25/25] target/mips: optimize indirect branches Richard Henderson
2017-05-02 20:22 ` [Qemu-devel] [PATCH v6 00/25] tcg cross-tb optimizations no-reply
2017-05-03  3:36 ` Richard Henderson
2017-05-03 15:51   ` Emilio G. Cota
2017-05-03 16:27     ` Richard Henderson
2017-05-03 18:24       ` Emilio G. Cota

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