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From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>
Subject: [Qemu-devel] [PATCH v2 06/14] target/sh4: fix BS_EXCP exit
Date: Sat,  6 May 2017 13:14:23 +0200	[thread overview]
Message-ID: <20170506111431.12548-7-aurelien@aurel32.net> (raw)
In-Reply-To: <20170506111431.12548-1-aurelien@aurel32.net>

In case of exception, there is no need to call tcg_gen_exit_tb as the
exception helper won't return.

Also fix a few cases where BS_BRANCH is called instead of BS_EXCP.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target/sh4/translate.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 04bc18bf7c..f608e314b6 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -339,7 +339,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
     if (ctx->envflags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {     \
         tcg_gen_movi_i32(cpu_pc, ctx->pc);                           \
         gen_helper_raise_slot_illegal_instruction(cpu_env);          \
-        ctx->bstate = BS_BRANCH;                                     \
+        ctx->bstate = BS_EXCP;                                       \
         return;                                                      \
     }
 
@@ -351,7 +351,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
         } else {                                                     \
             gen_helper_raise_illegal_instruction(cpu_env);           \
         }                                                            \
-        ctx->bstate = BS_BRANCH;                                     \
+        ctx->bstate = BS_EXCP;                                       \
         return;                                                      \
     }
 
@@ -363,7 +363,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
         } else {                                                     \
             gen_helper_raise_fpu_disable(cpu_env);                   \
         }                                                            \
-        ctx->bstate = BS_BRANCH;                                     \
+        ctx->bstate = BS_EXCP;                                       \
         return;                                                      \
     }
 
@@ -1289,7 +1289,7 @@ static void _decode_opc(DisasContext * ctx)
 	    imm = tcg_const_i32(B7_0);
             gen_helper_trapa(cpu_env, imm);
 	    tcg_temp_free(imm);
-	    ctx->bstate = BS_BRANCH;
+            ctx->bstate = BS_EXCP;
 	}
 	return;
     case 0xc800:		/* tst #imm,R0 */
@@ -1798,7 +1798,7 @@ static void _decode_opc(DisasContext * ctx)
     } else {
         gen_helper_raise_illegal_instruction(cpu_env);
     }
-    ctx->bstate = BS_BRANCH;
+    ctx->bstate = BS_EXCP;
 }
 
 static void decode_opc(DisasContext * ctx)
@@ -1867,7 +1867,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
             /* We have hit a breakpoint - make sure PC is up-to-date */
             tcg_gen_movi_i32(cpu_pc, ctx.pc);
             gen_helper_debug(cpu_env);
-            ctx.bstate = BS_BRANCH;
+            ctx.bstate = BS_EXCP;
             /* The address covered by the breakpoint must be included in
                [tb->pc, tb->pc + tb->size) in order to for it to be
                properly cleared -- thus we increment the PC here so that
@@ -1911,9 +1911,7 @@ void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
             gen_goto_tb(&ctx, 0, ctx.pc);
             break;
         case BS_EXCP:
-            /* gen_op_interrupt_restart(); */
-            tcg_gen_exit_tb(0);
-            break;
+            /* fall through */
         case BS_BRANCH:
         default:
             break;
-- 
2.11.0

  parent reply	other threads:[~2017-05-06 11:14 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-06 11:14 [Qemu-devel] [PATCH v2 00/14] target/sh4: misc fixes, cleanup and optimizations Aurelien Jarno
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 01/14] target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags Aurelien Jarno
2017-05-06 16:15   ` Philippe Mathieu-Daudé
2017-05-09 20:55   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 02/14] target/sh4: get rid of DELAY_SLOT_CLEARME Aurelien Jarno
2017-05-09 20:56   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 03/14] target/sh4: do not include DELAY_SLOT_TRUE in the TB state Aurelien Jarno
2017-05-06 16:16   ` Philippe Mathieu-Daudé
2017-05-09 20:56   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 04/14] target/sh4: move DELAY_SLOT_TRUE flag into a separate global Aurelien Jarno
2017-05-09 20:59   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 05/14] target/sh4: fix BS_STOP exit Aurelien Jarno
2017-05-09 21:02   ` Richard Henderson
2017-05-06 11:14 ` Aurelien Jarno [this message]
2017-05-06 16:17   ` [Qemu-devel] [PATCH v2 06/14] target/sh4: fix BS_EXCP exit Philippe Mathieu-Daudé
2017-05-09 21:03   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 07/14] target/sh4: only save flags state at the end of the TB Aurelien Jarno
2017-05-09 21:06   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 08/14] target/sh4: fold ctx->bstate = BS_BRANCH into gen_conditional_jump Aurelien Jarno
2017-05-09 21:07   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 09/14] target/sh4: optimize gen_store_fpr64 Aurelien Jarno
2017-05-09 21:09   ` Richard Henderson
2017-05-10  6:54     ` Aurelien Jarno
2017-05-10 11:01     ` Philippe Mathieu-Daudé
2017-05-13  0:29     ` [Qemu-devel] [PATCH] tcg: optimize gen_extr_i64_i32() Philippe Mathieu-Daudé
2017-05-13  2:13       ` Richard Henderson
2017-05-30 15:01         ` Philippe Mathieu-Daudé
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 10/14] target/sh4: optimize gen_write_sr using extract op Aurelien Jarno
2017-05-06 16:19   ` Philippe Mathieu-Daudé
2017-05-09 21:09   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 11/14] target/sh4: generate fences for SH4 Aurelien Jarno
2017-05-09 21:10   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 12/14] target/sh4: implement tas.b using atomic helper Aurelien Jarno
2017-05-09 21:10   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 13/14] target/sh4: movua.l is an SH4-A only instruction Aurelien Jarno
2017-05-09 21:11   ` Richard Henderson
2017-05-06 11:14 ` [Qemu-devel] [PATCH v2 14/14] target/sh4: trap unaligned accesses Aurelien Jarno
2017-05-09 21:13   ` Richard Henderson
2017-05-10  7:00     ` Aurelien Jarno

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