From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
mdroth@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com,
agraf@suse.de, aik@ozlabs.ru, sjitindarsingh@gmail.com,
mark.cave-ayland@ilande.co.uk, sam.bobroff@au1.ibm.com,
nikunj@linux.vnet.ibm.com, clg@kaod.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 16/22] target/ppc: Change tlbie invalid fields for POWER9 support
Date: Wed, 10 May 2017 17:01:09 +1000 [thread overview]
Message-ID: <20170510070115.13063-17-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20170510070115.13063-1-david@gibson.dropbear.id.au>
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The tlbie[l] instructions are used to invalidate TLB entries used to cache
address translations.
In ISAv3.00 (POWER9) more fields were added to the tblie[l] instructions
which were previously invalid. We don't care about any of these new fields
since we just invalidate the whole world anyway but we need to not
cause an illegal instruction exception when the instructions are called.
We also don't want to allow an older processor to have these fields set
since that would be invalid.
Add a new GEN_HANDLER for the ISAv3 instructions with the correct invalid
mask. These will only be generated to a POWER9 processor for now based on
the instruction flag. Also remove the PPC_MEM_TLBIE instruction flag from
the POWER9 processor definition to ensure the old tlbie isn't generated.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 2 ++
target/ppc/translate_init.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1ce6ab1..c0cd64d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6578,6 +6578,8 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
* different ISA versions */
GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
+GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
#if defined(TARGET_PPC64)
GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 9b048cd..fda30b0 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8960,7 +8960,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBSYNC |
PPC_64B | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
--
2.9.3
next prev parent reply other threads:[~2017-05-10 7:01 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-10 7:00 [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510 David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 01/22] ppc/pnv: restrict BMC object to the BMC simulator David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 02/22] target/ppc: Emulate LL/SC using cmpxchg helpers David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 03/22] cputlb: handle first atomic write to the page David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 04/22] target/ppc: Generate fence operations David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 05/22] cpus: Fix CPU unplug for MTTCG David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 06/22] tcg: enable MTTCG by default for PPC64 on x86 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 07/22] target/ppc: do not reset reserve_addr in exec_enter David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 08/22] ppc/xics: Fix stale irq->status bits after get David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 09/22] ppc/xics: preserve P and Q bits for KVM IRQs David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 10/22] Add QemuMacDrivers as submodule David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 11/22] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built " David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 12/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 13/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 15/22] target/ppc: Update tlbie to check privilege level based on GTSE David Gibson
2017-05-10 7:01 ` David Gibson [this message]
2017-05-10 7:01 ` [Qemu-devel] [PULL 17/22] target/ppc: Implement ISA V3.00 radix page fault handler David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 18/22] target/ppc: Enable RADIX mmu mode for pseries TCG guest David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 19/22] ppc: xics: fix compilation with CentOS 6 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 20/22] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 22/22] pnv: Fix build failures on some host platforms David Gibson
2017-05-10 7:50 ` [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510 no-reply
2017-05-10 9:45 ` David Gibson
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