From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
mdroth@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com,
agraf@suse.de, aik@ozlabs.ru, sjitindarsingh@gmail.com,
mark.cave-ayland@ilande.co.uk, sam.bobroff@au1.ibm.com,
nikunj@linux.vnet.ibm.com, clg@kaod.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 04/22] target/ppc: Generate fence operations
Date: Wed, 10 May 2017 17:00:57 +1000 [thread overview]
Message-ID: <20170510070115.13063-5-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20170510070115.13063-1-david@gibson.dropbear.id.au>
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 50b6d4d..4a1f24a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2971,6 +2971,7 @@ static void gen_stswx(DisasContext *ctx)
/* eieio */
static void gen_eieio(DisasContext *ctx)
{
+ tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
}
#if !defined(CONFIG_USER_ONLY)
@@ -3008,6 +3009,7 @@ static void gen_isync(DisasContext *ctx)
if (!ctx->pr) {
gen_check_tlb_flush(ctx, false);
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
gen_stop_exception(ctx);
}
@@ -3028,6 +3030,7 @@ static void gen_##name(DisasContext *ctx) \
tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop); \
tcg_gen_mov_tl(cpu_reserve, t0); \
tcg_gen_mov_tl(cpu_reserve_val, gpr); \
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); \
tcg_temp_free(t0); \
}
@@ -3177,6 +3180,10 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
tcg_gen_br(l2);
gen_set_label(l1);
+
+ /* Address mismatch implies failure. But we still need to provide the
+ memory barrier semantics of the instruction. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
gen_set_label(l2);
@@ -3308,6 +3315,7 @@ static void gen_sync(DisasContext *ctx)
if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
gen_check_tlb_flush(ctx, true);
}
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
}
/* wait */
--
2.9.3
next prev parent reply other threads:[~2017-05-10 7:01 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-10 7:00 [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510 David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 01/22] ppc/pnv: restrict BMC object to the BMC simulator David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 02/22] target/ppc: Emulate LL/SC using cmpxchg helpers David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 03/22] cputlb: handle first atomic write to the page David Gibson
2017-05-10 7:00 ` David Gibson [this message]
2017-05-10 7:00 ` [Qemu-devel] [PULL 05/22] cpus: Fix CPU unplug for MTTCG David Gibson
2017-05-10 7:00 ` [Qemu-devel] [PULL 06/22] tcg: enable MTTCG by default for PPC64 on x86 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 07/22] target/ppc: do not reset reserve_addr in exec_enter David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 08/22] ppc/xics: Fix stale irq->status bits after get David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 09/22] ppc/xics: preserve P and Q bits for KVM IRQs David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 10/22] Add QemuMacDrivers as submodule David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 11/22] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built " David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 12/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 13/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 15/22] target/ppc: Update tlbie to check privilege level based on GTSE David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 16/22] target/ppc: Change tlbie invalid fields for POWER9 support David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 17/22] target/ppc: Implement ISA V3.00 radix page fault handler David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 18/22] target/ppc: Enable RADIX mmu mode for pseries TCG guest David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 19/22] ppc: xics: fix compilation with CentOS 6 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 20/22] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1 David Gibson
2017-05-10 7:01 ` [Qemu-devel] [PULL 22/22] pnv: Fix build failures on some host platforms David Gibson
2017-05-10 7:50 ` [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510 no-reply
2017-05-10 9:45 ` David Gibson
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