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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	mdroth@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com,
	agraf@suse.de, aik@ozlabs.ru, sjitindarsingh@gmail.com,
	mark.cave-ayland@ilande.co.uk, sam.bobroff@au1.ibm.com,
	nikunj@linux.vnet.ibm.com, clg@kaod.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 07/22] target/ppc: do not reset reserve_addr in exec_enter
Date: Wed, 10 May 2017 17:01:00 +1000	[thread overview]
Message-ID: <20170510070115.13063-8-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20170510070115.13063-1-david@gibson.dropbear.id.au>

From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>

In case when atomic operation is not supported, exit_atomic is called
and we stop the world and execute the atomic operation. This results
in a following call chain:

tcg_gen_atomic_cmpxchg_tl()
  -> gen_helper_exit_atomic()
     -> HELPER(exit_atomic)
        -> cpu_loop_exit_atomic() -> EXCP_ATOMIC
           -> qemu_tcg_cpu_thread_fn() => case EXCP_ATOMIC
              -> cpu_exec_step_atomic()
                 -> cpu_step_atomic()
                    -> cc->cpu_exec_enter() = ppc_cpu_exec_enter()
                       Sets env->reserve_addr = -1;

But by the time it return back, the reservation is erased and the code
fails, this continues forever and the lock is never taken.

Instead set this in powerpc_excp()

Now that ppc_cpu_exec_enter() doesn't have anything meaningful to do,
let us get rid of the function.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/excp_helper.c    | 3 +++
 target/ppc/translate_init.c | 9 ---------
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index f4ee7aa..a6bcb47 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -728,6 +728,9 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
     cs->exception_index = POWERPC_EXCP_NONE;
     env->error_code = 0;
 
+    /* Reset the reservation */
+    env->reserve_addr = -1;
+
     /* Any interrupt is context synchronizing, check if TCG TLB
      * needs a delayed flush on ppc64
      */
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index e82e3e6..9b048cd 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -10436,14 +10436,6 @@ static bool ppc_cpu_has_work(CPUState *cs)
     return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
 }
 
-static void ppc_cpu_exec_enter(CPUState *cs)
-{
-    PowerPCCPU *cpu = POWERPC_CPU(cs);
-    CPUPPCState *env = &cpu->env;
-
-    env->reserve_addr = -1;
-}
-
 /* CPUClass::reset() */
 static void ppc_cpu_reset(CPUState *s)
 {
@@ -10660,7 +10652,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_ppc_cpu;
 #endif
-    cc->cpu_exec_enter = ppc_cpu_exec_enter;
 #if defined(CONFIG_SOFTMMU)
     cc->write_elf64_note = ppc64_cpu_write_elf64_note;
     cc->write_elf32_note = ppc32_cpu_write_elf32_note;
-- 
2.9.3

  parent reply	other threads:[~2017-05-10  7:01 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-05-10  7:00 [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510 David Gibson
2017-05-10  7:00 ` [Qemu-devel] [PULL 01/22] ppc/pnv: restrict BMC object to the BMC simulator David Gibson
2017-05-10  7:00 ` [Qemu-devel] [PULL 02/22] target/ppc: Emulate LL/SC using cmpxchg helpers David Gibson
2017-05-10  7:00 ` [Qemu-devel] [PULL 03/22] cputlb: handle first atomic write to the page David Gibson
2017-05-10  7:00 ` [Qemu-devel] [PULL 04/22] target/ppc: Generate fence operations David Gibson
2017-05-10  7:00 ` [Qemu-devel] [PULL 05/22] cpus: Fix CPU unplug for MTTCG David Gibson
2017-05-10  7:00 ` [Qemu-devel] [PULL 06/22] tcg: enable MTTCG by default for PPC64 on x86 David Gibson
2017-05-10  7:01 ` David Gibson [this message]
2017-05-10  7:01 ` [Qemu-devel] [PULL 08/22] ppc/xics: Fix stale irq->status bits after get David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 09/22] ppc/xics: preserve P and Q bits for KVM IRQs David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 10/22] Add QemuMacDrivers as submodule David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 11/22] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built " David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 12/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 13/22] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 14/22] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 15/22] target/ppc: Update tlbie to check privilege level based on GTSE David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 16/22] target/ppc: Change tlbie invalid fields for POWER9 support David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 17/22] target/ppc: Implement ISA V3.00 radix page fault handler David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 18/22] target/ppc: Enable RADIX mmu mode for pseries TCG guest David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 19/22] ppc: xics: fix compilation with CentOS 6 David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 20/22] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 21/22] target/ppc: Allow workarounds for POWER9 DD1 David Gibson
2017-05-10  7:01 ` [Qemu-devel] [PULL 22/22] pnv: Fix build failures on some host platforms David Gibson
2017-05-10  7:50 ` [Qemu-devel] [PULL 00/22] ppc-for-2.10 queue 20170510 no-reply
2017-05-10  9:45   ` David Gibson

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