From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
mdroth@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com,
agraf@suse.de, aik@ozlabs.ru, sjitindarsingh@gmail.com,
mark.cave-ayland@ilande.co.uk, sam.bobroff@au1.ibm.com,
nikunj@linux.vnet.ibm.com, clg@kaod.org,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 15/23] target/ppc: Update tlbie to check privilege level based on GTSE
Date: Thu, 11 May 2017 14:14:18 +1000 [thread overview]
Message-ID: <20170511041426.6488-16-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20170511041426.6488-1-david@gibson.dropbear.id.au>
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
The Guest Translation Shootdown Enable (GTSE) bit in the Logical Partition
Control Register (LPCR) can be set to enable a guest to use the tlbie
instruction directly to invalidate translations.
When the GTSE bit is set then the tlbie instruction is supervisor
privileged, otherwise it is hypervisor privileged.
Add a guest translation shootdown enable (gtse) field to the diassembly
context and use this to check the correct privilege level at code
generation time.
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4a1f24a..1ce6ab1 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -218,6 +218,7 @@ struct DisasContext {
bool vsx_enabled;
bool spe_enabled;
bool tm_enabled;
+ bool gtse;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -4538,7 +4539,12 @@ static void gen_tlbie(DisasContext *ctx)
GEN_PRIV;
#else
TCGv_i32 t1;
- CHK_HV;
+
+ if (ctx->gtse) {
+ CHK_SV; /* If gtse is set then tblie is supervisor privileged */
+ } else {
+ CHK_HV; /* Else hypervisor privileged */
+ }
if (NARROW_MODE(ctx)) {
TCGv t0 = tcg_temp_new();
@@ -7252,6 +7258,7 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
ctx.tm_enabled = false;
}
#endif
+ ctx.gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
ctx.singlestep_enabled = CPU_SINGLE_STEP;
else
--
2.9.3
next prev parent reply other threads:[~2017-05-11 4:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-11 4:14 [Qemu-devel] [PULL 00/23] ppc-for-2.10 queue 20170511 David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 01/23] ppc/pnv: restrict BMC object to the BMC simulator David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 02/23] target/ppc: Emulate LL/SC using cmpxchg helpers David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 03/23] cputlb: handle first atomic write to the page David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 04/23] target/ppc: Generate fence operations David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 05/23] cpus: Fix CPU unplug for MTTCG David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 06/23] tcg: enable MTTCG by default for PPC64 on x86 David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 07/23] target/ppc: do not reset reserve_addr in exec_enter David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 08/23] ppc/xics: Fix stale irq->status bits after get David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 09/23] ppc/xics: preserve P and Q bits for KVM IRQs David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 10/23] Add QemuMacDrivers as submodule David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 11/23] Add QemuMacDrivers qemu_vga.ndrv revision d4e7d7a built " David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 12/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for OldWorld Macs David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 13/23] ppc: add qemu_vga.ndrv ROM to fw_cfg interface for NewWorld Macs David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 14/23] target/ppc: Set UPRT and GTSE on all cpus in H_REGISTER_PROCESS_TABLE David Gibson
2017-05-11 4:14 ` David Gibson [this message]
2017-05-11 4:14 ` [Qemu-devel] [PULL 16/23] target/ppc: Change tlbie invalid fields for POWER9 support David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 17/23] target/ppc: Implement ISA V3.00 radix page fault handler David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 18/23] target/ppc: Enable RADIX mmu mode for pseries TCG guest David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 19/23] ppc: xics: fix compilation with CentOS 6 David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 20/23] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 21/23] target/ppc: Allow workarounds for POWER9 DD1 David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 22/23] pnv: Fix build failures on some host platforms David Gibson
2017-05-11 4:14 ` [Qemu-devel] [PULL 23/23] target/ppc: Avoid printing wrong aliases in CPU help text David Gibson
2017-05-15 13:04 ` [Qemu-devel] [PULL 00/23] ppc-for-2.10 queue 20170511 Stefan Hajnoczi
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