* [Qemu-devel] [PATCH] spapr: Don't accidentally advertise HTM support on POWER9
@ 2017-05-09 5:04 David Gibson
2017-05-09 5:41 ` Thomas Huth
2017-05-22 5:33 ` Sam Bobroff
0 siblings, 2 replies; 3+ messages in thread
From: David Gibson @ 2017-05-09 5:04 UTC (permalink / raw)
To: sam.bobroff, thuth
Cc: lvivier, mdroth, bharata, aik, qemu-ppc, qemu-devel, David Gibson
Logic in spapr_populate_pa_features() enables the bit advertising
Hardware Transactional Memory (HTM) in the guest's device tree only when
KVM advertises its availability with the KVM_CAP_PPC_HTM feature.
However, this assumes that the HTM bit is off in the base template used for
the device tree value. That is true for POWER8, but not for POWER9.
It looks like that was accidentally changed in 9fb4541 "spapr: Enable ISA
3.0 MMU mode selection via CAS".
Fixes: 9fb4541f5803f8d2ba116b12113386e26482ba30
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e2dc77c..1b7cada 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -219,7 +219,7 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
/* 16: Vector */
0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
/* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
+ 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
/* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
/* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
--
2.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] spapr: Don't accidentally advertise HTM support on POWER9
2017-05-09 5:04 [Qemu-devel] [PATCH] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
@ 2017-05-09 5:41 ` Thomas Huth
2017-05-22 5:33 ` Sam Bobroff
1 sibling, 0 replies; 3+ messages in thread
From: Thomas Huth @ 2017-05-09 5:41 UTC (permalink / raw)
To: David Gibson, sam.bobroff
Cc: lvivier, mdroth, bharata, aik, qemu-ppc, qemu-devel
On 09.05.2017 07:04, David Gibson wrote:
> Logic in spapr_populate_pa_features() enables the bit advertising
> Hardware Transactional Memory (HTM) in the guest's device tree only when
> KVM advertises its availability with the KVM_CAP_PPC_HTM feature.
>
> However, this assumes that the HTM bit is off in the base template used for
> the device tree value. That is true for POWER8, but not for POWER9.
>
> It looks like that was accidentally changed in 9fb4541 "spapr: Enable ISA
> 3.0 MMU mode selection via CAS".
>
> Fixes: 9fb4541f5803f8d2ba116b12113386e26482ba30
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/spapr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index e2dc77c..1b7cada 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -219,7 +219,7 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
> /* 16: Vector */
> 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
> - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
>
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH] spapr: Don't accidentally advertise HTM support on POWER9
2017-05-09 5:04 [Qemu-devel] [PATCH] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
2017-05-09 5:41 ` Thomas Huth
@ 2017-05-22 5:33 ` Sam Bobroff
1 sibling, 0 replies; 3+ messages in thread
From: Sam Bobroff @ 2017-05-22 5:33 UTC (permalink / raw)
To: David Gibson; +Cc: thuth, lvivier, mdroth, bharata, aik, qemu-ppc, qemu-devel
On Tue, May 09, 2017 at 03:04:58PM +1000, David Gibson wrote:
> Logic in spapr_populate_pa_features() enables the bit advertising
> Hardware Transactional Memory (HTM) in the guest's device tree only when
> KVM advertises its availability with the KVM_CAP_PPC_HTM feature.
>
> However, this assumes that the HTM bit is off in the base template used for
> the device tree value. That is true for POWER8, but not for POWER9.
>
> It looks like that was accidentally changed in 9fb4541 "spapr: Enable ISA
> 3.0 MMU mode selection via CAS".
>
> Fixes: 9fb4541f5803f8d2ba116b12113386e26482ba30
>
> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/ppc/spapr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index e2dc77c..1b7cada 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -219,7 +219,7 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset,
> /* 16: Vector */
> 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
> - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */
> + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
> --
> 2.9.3
Looks good to me.
Reviewed-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2017-05-22 5:34 UTC | newest]
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2017-05-09 5:04 [Qemu-devel] [PATCH] spapr: Don't accidentally advertise HTM support on POWER9 David Gibson
2017-05-09 5:41 ` Thomas Huth
2017-05-22 5:33 ` Sam Bobroff
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