From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40217) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dIaJs-0000om-8N for qemu-devel@nongnu.org; Wed, 07 Jun 2017 08:44:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dIaJn-0000II-N7 for qemu-devel@nongnu.org; Wed, 07 Jun 2017 08:44:16 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39418) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dIaJn-0000Hs-Ev for qemu-devel@nongnu.org; Wed, 07 Jun 2017 08:44:11 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 76B1461BAA for ; Wed, 7 Jun 2017 12:44:10 +0000 (UTC) From: Marcel Apfelbaum Date: Wed, 7 Jun 2017 15:43:59 +0300 Message-Id: <20170607124359.79478-1-marcel@redhat.com> Subject: [Qemu-devel] [PATCH V2] hw/pcie: fix the generic pcie root port to support migration List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: marcel@redhat.com, mst@redhat.com, dgilbert@redhat.com Add msix state to pcie-root-ports's vmstate in order to support migration. Signed-off-by: Marcel Apfelbaum --- v1 -> v2: - Added x-migrate-msix compat property to avoid breaking migration (Dave) hw/pci-bridge/gen_pcie_root_port.c | 25 +++++++++++++++++++++++++ include/hw/compat.h | 4 ++++ 2 files changed, 29 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index 8ebffa8..cb694d6 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -20,6 +20,14 @@ #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 +typedef struct GenPCIERootPort { + /*< private >*/ + PCIESlot parent_obj; + /*< public >*/ + + bool migrate_msix; +} GenPCIERootPort; + static uint8_t gen_rp_aer_vector(const PCIDevice *d) { return 0; @@ -45,6 +53,13 @@ static void gen_rp_interrupts_uninit(PCIDevice *d) msix_uninit_exclusive_bar(d); } +static bool gen_rp_test_migrate_msix(void *opaque, int version_id) +{ + GenPCIERootPort *rp = opaque; + + return rp->migrate_msix; +} + static const VMStateDescription vmstate_rp_dev = { .name = "pcie-root-port", .version_id = 1, @@ -54,10 +69,18 @@ static const VMStateDescription vmstate_rp_dev = { VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), + VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj, + GenPCIERootPort, + gen_rp_test_migrate_msix), VMSTATE_END_OF_LIST() } }; +static Property gen_rp_props[] = { + DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true), + DEFINE_PROP_END_OF_LIST() +}; + static void gen_rp_dev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -68,6 +91,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data) k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP; dc->desc = "PCI Express Root Port"; dc->vmsd = &vmstate_rp_dev; + dc->props = gen_rp_props; rpc->aer_vector = gen_rp_aer_vector; rpc->interrupts_init = gen_rp_interrupts_init; rpc->interrupts_uninit = gen_rp_interrupts_uninit; @@ -77,6 +101,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, void *data) static const TypeInfo gen_rp_dev_info = { .name = TYPE_GEN_PCIE_ROOT_PORT, .parent = TYPE_PCIE_ROOT_PORT, + .instance_size = sizeof(GenPCIERootPort), .class_init = gen_rp_dev_class_init, }; diff --git a/include/hw/compat.h b/include/hw/compat.h index 55b1765..4fb6a19 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -6,6 +6,10 @@ .driver = "pci-bridge",\ .property = "shpc",\ .value = "off",\ + },{\ + .driver = "pcie-root-port",\ + .property = "x-migrate-msix",\ + .value = "false",\ }, #define HW_COMPAT_2_8 \ -- 2.9.4