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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: cota@braap.org
Subject: [Qemu-devel] [PATCH v4 7/7] target/arm: Use ldr (literal) for goto_tb
Date: Wed,  7 Jun 2017 08:55:36 -0700	[thread overview]
Message-ID: <20170607155536.1193-8-rth@twiddle.net> (raw)
In-Reply-To: <20170607155536.1193-1-rth@twiddle.net>

The new placement of the TB means that we can use one insn
to load the goto_tb destination directly from the TB.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.inc.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 18708b1..b640fb9 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1669,14 +1669,27 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
     case INDEX_op_goto_tb:
-        tcg_debug_assert(s->tb_jmp_insn_offset == 0);
         {
             /* Indirect jump method */
-            intptr_t ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]);
-            tcg_out_movi32(s, COND_AL, TCG_REG_R0, ptr & ~0xfff);
-            tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_R0, ptr & 0xfff);
+            intptr_t ptr, dif, dil;
+            TCGReg base = TCG_REG_PC;
+
+            tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+            ptr = (intptr_t)(s->tb_jmp_target_addr + args[0]);
+            dif = ptr - ((intptr_t)s->code_ptr + 8);
+            dil = sextract32(dif, 0, 12);
+            if (dif != dil) {
+                /* The TB is close, but outside the 12 bits addressable by
+                   the load.  We can extend this to 20 bits with a sub of a
+                   shifted immediate from pc.  In the vastly unlikely event
+                   the code requires more than 1MB, we'll use 2 insns and
+                   be no worse off.  */
+                base = TCG_REG_R0;
+                tcg_out_movi32(s, COND_AL, base, ptr - dil);
+            }
+            tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, base, dil);
+            s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
         }
-        s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);
         break;
     case INDEX_op_goto_ptr:
         tcg_out_bx(s, COND_AL, args[0]);
-- 
2.9.4

  parent reply	other threads:[~2017-06-07 15:56 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-07 15:55 [Qemu-devel] [PATCH v4 0/7] tcg: allocate TB structs preceding translate Richard Henderson
2017-06-07 15:55 ` [Qemu-devel] [PATCH v4 1/7] util: add cacheinfo Richard Henderson
2017-06-07 22:11   ` Emilio G. Cota
2017-06-08 16:42     ` Richard Henderson
2017-06-07 15:55 ` [Qemu-devel] [PATCH v4 2/7] tcg: allocate TB structs before the corresponding translated code Richard Henderson
2017-06-07 15:55 ` [Qemu-devel] [PATCH v4 3/7] tcg/aarch64: Use ADR in tcg_out_movi Richard Henderson
2017-06-07 15:55 ` [Qemu-devel] [PATCH v4 4/7] target/arm: Use indirect branch for goto_tb Richard Henderson
2017-06-07 15:55 ` [Qemu-devel] [PATCH v4 5/7] target/arm: Remove limit on code buffer size Richard Henderson
2017-06-07 15:55 ` [Qemu-devel] [PATCH v4 6/7] target/arm: Try pc-relative addresses for movi Richard Henderson
2017-06-07 15:55 ` Richard Henderson [this message]
2017-06-07 19:46 ` [Qemu-devel] [PATCH v4 0/7] tcg: allocate TB structs preceding translate no-reply
2017-06-07 23:30 ` Emilio G. Cota
2017-06-08 16:44   ` Richard Henderson
2017-06-08 17:44     ` Emilio G. Cota
2017-06-08 20:17       ` Richard Henderson
2017-06-08  0:02 ` no-reply

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