* [Qemu-devel] [PATCH 1/2] tests/q35-test: push down qtest_start / qtest_end to test case(s)
2017-06-16 11:21 [Qemu-devel] [PATCH 0/2] tests/q35-test: add TSEG size checks Laszlo Ersek
@ 2017-06-16 11:22 ` Laszlo Ersek
2017-06-16 11:22 ` [Qemu-devel] [PATCH 2/2] tests/q35-test: add TSEG size checks Laszlo Ersek
1 sibling, 0 replies; 3+ messages in thread
From: Laszlo Ersek @ 2017-06-16 11:22 UTC (permalink / raw)
To: qemu devel list; +Cc: Michael S. Tsirkin, Gerd Hoffmann, Paolo Bonzini
A test program can start up QEMU several times, with different command
lines. For such cases, qtest_start() and qtest_end() are called from
within the individual test functions. Examples: "virtio-console-test.c",
"numa-test.c", and many others.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
tests/q35-test.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/tests/q35-test.c b/tests/q35-test.c
index cc58f3ecf491..6c21b402a76c 100644
--- a/tests/q35-test.c
+++ b/tests/q35-test.c
@@ -42,6 +42,8 @@ static void test_smram_lock(void)
QPCIDevice *pcidev;
QDict *response;
+ qtest_start("-M q35");
+
pcibus = qpci_init_pc(NULL);
g_assert(pcibus != NULL);
@@ -74,19 +76,15 @@ static void test_smram_lock(void)
g_free(pcidev);
qpci_free_pc(pcibus);
+
+ qtest_end();
}
int main(int argc, char **argv)
{
- int ret;
-
g_test_init(&argc, &argv, NULL);
qtest_add_func("/q35/smram/lock", test_smram_lock);
- qtest_start("-M q35");
- ret = g_test_run();
- qtest_end();
-
- return ret;
+ return g_test_run();
}
--
2.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread* [Qemu-devel] [PATCH 2/2] tests/q35-test: add TSEG size checks
2017-06-16 11:21 [Qemu-devel] [PATCH 0/2] tests/q35-test: add TSEG size checks Laszlo Ersek
2017-06-16 11:22 ` [Qemu-devel] [PATCH 1/2] tests/q35-test: push down qtest_start / qtest_end to test case(s) Laszlo Ersek
@ 2017-06-16 11:22 ` Laszlo Ersek
1 sibling, 0 replies; 3+ messages in thread
From: Laszlo Ersek @ 2017-06-16 11:22 UTC (permalink / raw)
To: qemu devel list; +Cc: Michael S. Tsirkin, Gerd Hoffmann, Paolo Bonzini
These checks verify that the guest RAM turns from read-write to
"blackhole" when crossing the low boundary of the TSEG. Both the standard
1MB/2MB/8MB TSEG sizes and an extended (16MB) TSEG size are tested.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
Notes:
The "/q35/tseg-size/ext/16mb" test depends on the following patch:
[PATCH] q35/mch: implement extended TSEG sizes
http://mid.mail-archive.com/20170608161013.17920-1-lersek@redhat.com
tests/q35-test.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 113 insertions(+)
diff --git a/tests/q35-test.c b/tests/q35-test.c
index 6c21b402a76c..f98bed7a2d13 100644
--- a/tests/q35-test.c
+++ b/tests/q35-test.c
@@ -15,6 +15,48 @@
#include "libqos/pci-pc.h"
#include "hw/pci-host/q35.h"
+#define TSEG_SIZE_TEST_GUEST_RAM_MBYTES 128
+
+/* @esmramc_tseg_sz: ESMRAMC.TSEG_SZ bitmask for selecting the requested TSEG
+ * size. Must be a subset of
+ * MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK.
+ *
+ * @extended_tseg_mbytes: Size of the extended TSEG. Only consulted if
+ * @esmramc_tseg_sz equals
+ * MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK precisely.
+ *
+ * @expected_tseg_mbytes: Expected guest-visible TSEG size in megabytes,
+ * matching @esmramc_tseg_sz and @extended_tseg_mbytes
+ * above.
+ */
+struct TsegSizeArgs {
+ uint8_t esmramc_tseg_sz;
+ uint16_t extended_tseg_mbytes;
+ uint16_t expected_tseg_mbytes;
+};
+typedef struct TsegSizeArgs TsegSizeArgs;
+
+static const TsegSizeArgs tseg_1mb = {
+ .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB,
+ .extended_tseg_mbytes = 0,
+ .expected_tseg_mbytes = 1,
+};
+static const TsegSizeArgs tseg_2mb = {
+ .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB,
+ .extended_tseg_mbytes = 0,
+ .expected_tseg_mbytes = 2,
+};
+static const TsegSizeArgs tseg_8mb = {
+ .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB,
+ .extended_tseg_mbytes = 0,
+ .expected_tseg_mbytes = 8,
+};
+static const TsegSizeArgs tseg_ext_16mb = {
+ .esmramc_tseg_sz = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK,
+ .extended_tseg_mbytes = 16,
+ .expected_tseg_mbytes = 16,
+};
+
static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled)
{
uint8_t smram;
@@ -80,11 +122,82 @@ static void test_smram_lock(void)
qtest_end();
}
+static void test_tseg_size(const void *data)
+{
+ const TsegSizeArgs *args = data;
+ char *cmdline;
+ QPCIBus *pcibus;
+ QPCIDevice *pcidev;
+ uint8_t smram_val;
+ uint8_t esmramc_val;
+ uint32_t ram_offs;
+
+ if (args->esmramc_tseg_sz == MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
+ cmdline = g_strdup_printf("-M q35 -m %uM "
+ "-global mch.extended-tseg-mbytes=%u",
+ TSEG_SIZE_TEST_GUEST_RAM_MBYTES,
+ args->extended_tseg_mbytes);
+ } else {
+ cmdline = g_strdup_printf("-M q35 -m %uM",
+ TSEG_SIZE_TEST_GUEST_RAM_MBYTES);
+ }
+ qtest_start(cmdline);
+ g_free(cmdline);
+
+ /* locate the DRAM controller */
+ pcibus = qpci_init_pc(NULL);
+ g_assert(pcibus != NULL);
+ pcidev = qpci_device_find(pcibus, 0);
+ g_assert(pcidev != NULL);
+
+ /* Set TSEG size. Restrict TSEG visibility to SMM by setting T_EN. */
+ esmramc_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_ESMRAMC);
+ esmramc_val &= ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK;
+ esmramc_val |= args->esmramc_tseg_sz;
+ esmramc_val |= MCH_HOST_BRIDGE_ESMRAMC_T_EN;
+ qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_ESMRAMC, esmramc_val);
+
+ /* Enable TSEG by setting G_SMRAME. Close TSEG by setting D_CLS. */
+ smram_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
+ smram_val &= ~(MCH_HOST_BRIDGE_SMRAM_D_OPEN |
+ MCH_HOST_BRIDGE_SMRAM_D_LCK);
+ smram_val |= (MCH_HOST_BRIDGE_SMRAM_D_CLS |
+ MCH_HOST_BRIDGE_SMRAM_G_SMRAME);
+ qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
+
+ /* lock TSEG */
+ smram_val |= MCH_HOST_BRIDGE_SMRAM_D_LCK;
+ qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
+
+ /* Now check that the byte right before the TSEG is r/w, and that the first
+ * byte in the TSEG always reads as 0xff.
+ */
+ ram_offs = (TSEG_SIZE_TEST_GUEST_RAM_MBYTES - args->expected_tseg_mbytes) *
+ 1024 * 1024 - 1;
+ g_assert_cmpint(readb(ram_offs), ==, 0);
+ writeb(ram_offs, 1);
+ g_assert_cmpint(readb(ram_offs), ==, 1);
+
+ ram_offs++;
+ g_assert_cmpint(readb(ram_offs), ==, 0xff);
+ writeb(ram_offs, 1);
+ g_assert_cmpint(readb(ram_offs), ==, 0xff);
+
+ g_free(pcidev);
+ qpci_free_pc(pcibus);
+ qtest_end();
+}
+
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
qtest_add_func("/q35/smram/lock", test_smram_lock);
+ qtest_add_data_func("/q35/tseg-size/1mb", &tseg_1mb, test_tseg_size);
+ qtest_add_data_func("/q35/tseg-size/2mb", &tseg_2mb, test_tseg_size);
+ qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size);
+ qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb,
+ test_tseg_size);
return g_test_run();
}
--
2.9.3
^ permalink raw reply related [flat|nested] 3+ messages in thread