From: David Gibson <david@gibson.dropbear.id.au>
To: Aaron Larson <alarson@ddci.com>
Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3] target-ppc: Enable open-pic timers to count and generate interrupts
Date: Sun, 18 Jun 2017 20:24:35 +0800 [thread overview]
Message-ID: <20170618122435.GH22449@umbus> (raw)
In-Reply-To: <201706051722.v55HMrD0024174@linux03a.ddci.com>
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On Mon, Jun 05, 2017 at 10:22:53AM -0700, Aaron Larson wrote:
> Previously QEMU open-pic implemented the 4 open-pic timers including
> all timer registers, but the timers did not "count" or generate any
> interrupts. The patch makes the timers both count and generate
> interrupts. The timer clock frequency is fixed at 25MHZ.
Applied to ppc-for-2.10.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2017-06-18 12:25 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-05 17:22 [Qemu-devel] [PATCH v3] target-ppc: Enable open-pic timers to count and generate interrupts Aaron Larson
2017-06-16 16:31 ` alarson
2017-06-18 9:04 ` David Gibson
2017-06-19 13:57 ` alarson
2017-06-18 12:24 ` David Gibson [this message]
[not found] <mailman.79275.1497783014.22739.qemu-devel@nongnu.org>
2017-06-18 14:45 ` G 3
2017-06-18 20:36 ` alarson
2017-06-18 20:38 ` G 3
2017-06-18 22:15 ` alarson
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