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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: ricardo.ribalda@gmail.com, ehabkost@redhat.com, pbonzini@redhat.com
Subject: [Qemu-devel] [PATCH] target/i386: Fix BLSR and BLSI
Date: Wed, 12 Jul 2017 08:45:40 -1000	[thread overview]
Message-ID: <20170712184540.12352-1-rth@twiddle.net> (raw)
In-Reply-To: <CAPybu_0+enKVGf-bZHrkvWQ8reFtJnkKC=sucr2aaZ_DidaHNA@mail.gmail.com>

The implementation of these two instructions was swapped.
At the same time, unify the setup of eflags for the insn group.

Reported-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target/i386/translate.c | 25 ++++++++-----------------
 1 file changed, 8 insertions(+), 17 deletions(-)

diff --git a/target/i386/translate.c b/target/i386/translate.c
index 8365a6d..087a2e6 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -4029,36 +4029,27 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
                     goto illegal_op;
                 }
                 ot = mo_64_32(s->dflag);
-                gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, ot, OR_TMP1, 0);
 
                 switch (reg & 7) {
                 case 1: /* blsr By,Ey */
-                    tcg_gen_neg_tl(cpu_T1, cpu_T0);
+                    tcg_gen_subi_tl(cpu_T0, cpu_T1, 1);
                     tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
                     gen_op_mov_reg_v(ot, s->vex_v, cpu_T0);
-                    gen_op_update2_cc();
-                    set_cc_op(s, CC_OP_BMILGB + ot);
                     break;
-
                 case 2: /* blsmsk By,Ey */
-                    tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
-                    tcg_gen_subi_tl(cpu_T0, cpu_T0, 1);
-                    tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_cc_src);
-                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
-                    set_cc_op(s, CC_OP_BMILGB + ot);
+                    tcg_gen_subi_tl(cpu_T0, cpu_T1, 1);
+                    tcg_gen_xor_tl(cpu_T0, cpu_T0, cpu_T1);
                     break;
-
                 case 3: /* blsi By, Ey */
-                    tcg_gen_mov_tl(cpu_cc_src, cpu_T0);
-                    tcg_gen_subi_tl(cpu_T0, cpu_T0, 1);
-                    tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_cc_src);
-                    tcg_gen_mov_tl(cpu_cc_dst, cpu_T0);
-                    set_cc_op(s, CC_OP_BMILGB + ot);
+                    tcg_gen_neg_tl(cpu_T0, cpu_T1);
+                    tcg_gen_and_tl(cpu_T0, cpu_T0, cpu_T1);
                     break;
-
                 default:
                     goto unknown_op;
                 }
+                gen_op_update2_cc();
+                set_cc_op(s, CC_OP_BMILGB + ot);
                 break;
 
             default:
-- 
2.9.4

  parent reply	other threads:[~2017-07-12 18:45 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-11 21:21 [Qemu-devel] [PATCH 0/2] target/i386: Implement all TBM instructions Richard Henderson
2017-07-11 21:21 ` [Qemu-devel] [PATCH 1/2] target/i386: Decode AMD XOP prefix Richard Henderson
2017-07-11 21:21 ` [Qemu-devel] [PATCH 2/2] target/i386: Implement all TBM instructions Richard Henderson
2017-07-12  4:04 ` [Qemu-devel] [PATCH 0/2] " Richard Henderson
2017-07-12 13:28   ` Ricardo Ribalda Delgado
2017-07-12 18:43     ` Richard Henderson
2017-07-12 18:45     ` Richard Henderson [this message]
2017-07-12 18:58       ` [Qemu-devel] [PATCH] target/i386: Fix BLSR and BLSI Ricardo Ribalda Delgado
2017-07-12 19:12         ` Richard Henderson
2017-07-12 19:25           ` Ricardo Ribalda Delgado
2018-06-06  9:13       ` Ricardo Ribalda Delgado
2018-06-06 12:32         ` Paolo Bonzini
2017-07-12 19:29     ` [Qemu-devel] [PATCH v2] " Richard Henderson
2017-07-13 20:42       ` Ricardo Ribalda Delgado
2017-07-13 21:55         ` Ricardo Ribalda Delgado
2017-07-13 22:49           ` Ricardo Ribalda Delgado

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