From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38280) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWJbr-00047l-Cd for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWJbq-0003Ra-F5 for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:35 -0400 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:34972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dWJbq-0003R7-AB for qemu-devel@nongnu.org; Sat, 15 Jul 2017 05:43:34 -0400 Received: by mail-pg0-x244.google.com with SMTP id d193so13340758pgc.2 for ; Sat, 15 Jul 2017 02:43:34 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 14 Jul 2017 23:42:30 -1000 Message-Id: <20170715094243.28371-22-rth@twiddle.net> In-Reply-To: <20170715094243.28371-1-rth@twiddle.net> References: <20170715094243.28371-1-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v14 21/34] target/arm: [tcg] Port to insn_start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: vilanova@ac.upc.edu, cota@braap.org, alex.bennee@linaro.org, crosthwaite.peter@gmail.com, pbonzini@redhat.com From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index f5d69db..5e09682 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11898,6 +11898,16 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11941,10 +11951,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + arm_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; -- 2.9.4