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Date: Mon, 17 Jul 2017 19:59:52 +0300
From: "Michael S. Tsirkin" <mst@redhat.com>
Message-ID: <20170717195300-mutt-send-email-mst@kernel.org>
References: <20170716082917.720-1-dmitry@daynix.com>
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Subject: Re: [Qemu-devel] [PATCH] pci: honor PCI_COMMAND_MEMORY
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To: Dmitry Fleytman <dmitry@daynix.com>
Cc: Marcel Apfelbaum <marcel@redhat.com>, Qemu Developers <qemu-devel@nongnu.org>, Sameeh Jubran <sameeh@daynix.com>

On Mon, Jul 17, 2017 at 03:48:03PM +0300, Dmitry Fleytman wrote:
> Am I understand correctly that there are no special cases for
> IDE controllers, i.e. bus master bit must be set by SW same
> way as for other PCI devices?

Bus mastering is typically enabled by the driver.
E.g. under linux:

static int virtio_pci_restore(struct device *dev)
{
        struct pci_dev *pci_dev = to_pci_dev(dev);
        struct virtio_pci_device *vp_dev = pci_get_drvdata(pci_dev);
        int ret;

        ret = pci_enable_device(pci_dev);
        if (ret)
                return ret;

        pci_set_master(pci_dev);
        return virtio_device_restore(&vp_dev->vdev);
}


As an exception, in case of BIOS booting using device ROM, it is set by
the ROM. E.g. src/hw/virtio-pci.c:

    vp_reset(vp);
    pci_enable_busmaster(pci);
    vp_set_status(vp, VIRTIO_CONFIG_S_ACKNOWLEDGE |
                  VIRTIO_CONFIG_S_DRIVER );


-- 
MST