* [Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_base.
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 02/14] util/cacheinfo: Add missing include for ppc linux Richard Henderson
` (13 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Jiang Biao
From: Jiang Biao <jiang.biao2@zte.com.cn>
Reserve a register for the guest_base using ppc code for reference.
By doing so, we do not have to recompute it for every memory load.
Signed-off-by: Jiang Biao <jiang.biao2@zte.com.cn>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1499677934-2249-1-git-send-email-jiang.biao2@zte.com.cn>
---
tcg/mips/tcg-target.inc.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 85756b81d5..1a8169f5fc 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -85,6 +85,10 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP2 TCG_REG_T8
#define TCG_TMP3 TCG_REG_T7
+#ifndef CONFIG_SOFTMMU
+#define TCG_GUEST_BASE_REG TCG_REG_S1
+#endif
+
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
/* Call saved registers. */
@@ -1547,8 +1551,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
#endif
@@ -1652,8 +1655,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
} else if (guest_base == (int16_t)guest_base) {
tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base);
} else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, guest_base);
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP0, addr_regl);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl);
}
tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
#endif
@@ -2452,6 +2454,13 @@ static void tcg_target_qemu_prologue(TCGContext *s)
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
}
+#ifndef CONFIG_SOFTMMU
+ if (guest_base) {
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+ tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+ }
+#endif
+
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
/* delay slot */
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 02/14] util/cacheinfo: Add missing include for ppc linux
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_base Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 03/14] tcg: Expand glue macros before stringifying helper names Richard Henderson
` (12 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This include was forgotten when splitting cacheinfo.c out of
tcg/ppc/tcg-target.inc.c (see commit b255b2c8).
For a Centos7 host, the include path
<signal.h>
<bits/sigcontext.h>
<asm/sigcontext.h>
<asm/elf.h>
<asm/auxvec.h>
implicitly pulls in the desired AT_* defines.
Not so for Debian Jessie.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170711015524.22936-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
util/cacheinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
index 6253049533..593940f27b 100644
--- a/util/cacheinfo.c
+++ b/util/cacheinfo.c
@@ -129,6 +129,7 @@ static void arch_cache_info(int *isize, int *dsize)
}
#elif defined(_ARCH_PPC) && defined(__linux__)
+# include "elf.h"
static void arch_cache_info(int *isize, int *dsize)
{
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 03/14] tcg: Expand glue macros before stringifying helper names
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_base Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 02/14] util/cacheinfo: Add missing include for ppc linux Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 04/14] coccinelle: ignore ASTs pre-parsed cached C files Richard Henderson
` (11 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
include/exec/helper-tcg.h | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h
index bb9287727c..b0c5bafa99 100644
--- a/include/exec/helper-tcg.h
+++ b/include/exec/helper-tcg.h
@@ -6,31 +6,35 @@
#include "exec/helper-head.h"
+/* Need one more level of indirection before stringification
+ to get all the macros expanded first. */
+#define str(s) #s
+
#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \
- { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) },
#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \
- { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) },
#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \
- { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) },
#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \
- { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) },
#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \
- { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) },
#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \
- { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \
+ { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \
.sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \
| dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \
| dh_sizemask(t5, 5) },
@@ -39,6 +43,7 @@
#include "trace/generated-helpers.h"
#include "tcg-runtime.h"
+#undef str
#undef DEF_HELPER_FLAGS_0
#undef DEF_HELPER_FLAGS_1
#undef DEF_HELPER_FLAGS_2
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 04/14] coccinelle: ignore ASTs pre-parsed cached C files
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (2 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 03/14] tcg: Expand glue macros before stringifying helper names Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract() Richard Henderson
` (10 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
files generated using coccinelle tool: 'spatch --use-cache'
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-2-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
.gitignore | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitignore b/.gitignore
index 09c2363acf..cf65316863 100644
--- a/.gitignore
+++ b/.gitignore
@@ -116,6 +116,8 @@ tags
TAGS
docker-src.*
*~
+*.ast_raw
+*.depend_raw
trace.h
trace.c
trace-ust.h
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract()
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (3 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 04/14] coccinelle: ignore ASTs pre-parsed cached C files Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 06/14] target/arm: Optimize aarch64 rev16 Richard Henderson
` (9 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The following thread was helpful while writing this script:
https://github.com/coccinelle/coccinelle/issues/86
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-3-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
| 107 +++++++++++++++++++++++++++++++
1 file changed, 107 insertions(+)
create mode 100644 scripts/coccinelle/tcg_gen_extract.cocci
--git a/scripts/coccinelle/tcg_gen_extract.cocci b/scripts/coccinelle/tcg_gen_extract.cocci
new file mode 100644
index 0000000000..81e66a35ae
--- /dev/null
+++ b/scripts/coccinelle/tcg_gen_extract.cocci
@@ -0,0 +1,107 @@
+// optimize TCG using extract op
+//
+// Copyright: (C) 2017 Philippe Mathieu-Daudé. GPLv2+.
+// Confidence: High
+// Options: --macro-file scripts/cocci-macro-file.h
+//
+// Nikunj A Dadhania optimization:
+// http://lists.nongnu.org/archive/html/qemu-devel/2017-02/msg05211.html
+// Aurelien Jarno optimization:
+// http://lists.nongnu.org/archive/html/qemu-devel/2017-05/msg01466.html
+//
+// This script can be run either using spatch locally or via a docker image:
+//
+// $ spatch \
+// --macro-file scripts/cocci-macro-file.h \
+// --sp-file scripts/coccinelle/tcg_gen_extract.cocci \
+// --keep-comments --in-place \
+// --use-gitgrep --dir target
+//
+// $ docker run --rm -v `pwd`:`pwd` -w `pwd` philmd/coccinelle \
+// --macro-file scripts/cocci-macro-file.h \
+// --sp-file scripts/coccinelle/tcg_gen_extract.cocci \
+// --keep-comments --in-place \
+// --use-gitgrep --dir target
+
+@initialize:python@
+@@
+import sys
+fd = sys.stderr
+def debug(msg="", trailer="\n"):
+ fd.write("[DBG] " + msg + trailer)
+def low_bits_count(value):
+ bits_count = 0
+ while (value & (1 << bits_count)):
+ bits_count += 1
+ return bits_count
+def Mn(order): # Mersenne number
+ return (1 << order) - 1
+
+@match@
+identifier ret;
+metavariable arg;
+constant ofs, msk;
+position shr_p, and_p;
+@@
+(
+ tcg_gen_shri_i32@shr_p
+|
+ tcg_gen_shri_i64@shr_p
+|
+ tcg_gen_shri_tl@shr_p
+)(ret, arg, ofs);
+... WHEN != ret
+(
+ tcg_gen_andi_i32@and_p
+|
+ tcg_gen_andi_i64@and_p
+|
+ tcg_gen_andi_tl@and_p
+)(ret, ret, msk);
+
+@script:python verify_len depends on match@
+ret_s << match.ret;
+msk_s << match.msk;
+shr_p << match.shr_p;
+extract_len;
+@@
+is_optimizable = False
+debug("candidate at %s:%s" % (shr_p[0].file, shr_p[0].line))
+try: # only eval integer, no #define like 'SR_M' (cpp did this, else some headers are missing).
+ msk_v = long(msk_s.strip("UL"), 0)
+ msk_b = low_bits_count(msk_v)
+ if msk_b == 0:
+ debug(" value: 0x%x low_bits: %d" % (msk_v, msk_b))
+ else:
+ debug(" value: 0x%x low_bits: %d [Mersenne number: 0x%x]" % (msk_v, msk_b, Mn(msk_b)))
+ is_optimizable = Mn(msk_b) == msk_v # check low_bits
+ coccinelle.extract_len = "%d" % msk_b
+ debug(" candidate %s optimizable" % ("IS" if is_optimizable else "is NOT"))
+except:
+ debug(" ERROR (check included headers?)")
+cocci.include_match(is_optimizable)
+debug()
+
+@replacement depends on verify_len@
+identifier match.ret;
+metavariable match.arg;
+constant match.ofs, match.msk;
+position match.shr_p, match.and_p;
+identifier verify_len.extract_len;
+@@
+(
+-tcg_gen_shri_i32@shr_p(ret, arg, ofs);
++tcg_gen_extract_i32(ret, arg, ofs, extract_len);
+... WHEN != ret
+-tcg_gen_andi_i32@and_p(ret, ret, msk);
+|
+-tcg_gen_shri_i64@shr_p(ret, arg, ofs);
++tcg_gen_extract_i64(ret, arg, ofs, extract_len);
+... WHEN != ret
+-tcg_gen_andi_i64@and_p(ret, ret, msk);
+|
+-tcg_gen_shri_tl@shr_p(ret, arg, ofs);
++tcg_gen_extract_tl(ret, arg, ofs, extract_len);
+... WHEN != ret
+-tcg_gen_andi_tl@and_p(ret, ret, msk);
+)
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 06/14] target/arm: Optimize aarch64 rev16
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (4 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract() Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-21 5:42 ` [Qemu-devel] [PATCH] target/arm: fix TCG temp leak in " Emilio G. Cota
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 07/14] target/arm: optimize aarch32 rev16 Richard Henderson
` (8 subsequent siblings)
14 siblings, 1 reply; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
It is much shorter to reverse all 4 half-words in parallel
than extract, reverse, and deposit each in turn.
Suggested-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/arm/translate-a64.c | 24 ++++++------------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 3fa39023ca..5bb0f8ef22 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4043,25 +4043,13 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
TCGv_i64 tcg_rd = cpu_reg(s, rd);
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
+ TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
- tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
- tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
-
- tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
- tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
- tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
-
- if (sf) {
- tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
- tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
- tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
-
- tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
- tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
- tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
- }
+ tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
+ tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
+ tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
+ tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
+ tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
tcg_temp_free_i64(tcg_tmp);
}
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PATCH] target/arm: fix TCG temp leak in aarch64 rev16
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 06/14] target/arm: Optimize aarch64 rev16 Richard Henderson
@ 2017-07-21 5:42 ` Emilio G. Cota
2017-07-21 13:16 ` Peter Maydell
0 siblings, 1 reply; 19+ messages in thread
From: Emilio G. Cota @ 2017-07-21 5:42 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, peter.maydell
On Wed, Jul 19, 2017 at 13:34:47 -1000, Richard Henderson wrote:
> It is much shorter to reverse all 4 half-words in parallel
> than extract, reverse, and deposit each in turn.
>
> Suggested-by: Aurelien Jarno <aurelien@aurel32.net>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target/arm/translate-a64.c | 24 ++++++------------------
> 1 file changed, 6 insertions(+), 18 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 3fa39023ca..5bb0f8ef22 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -4043,25 +4043,13 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
> TCGv_i64 tcg_rd = cpu_reg(s, rd);
> TCGv_i64 tcg_tmp = tcg_temp_new_i64();
> TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
> + TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
>
> - tcg_gen_andi_i64(tcg_tmp, tcg_rn, 0xffff);
> - tcg_gen_bswap16_i64(tcg_rd, tcg_tmp);
> -
> - tcg_gen_shri_i64(tcg_tmp, tcg_rn, 16);
> - tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
> - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
> - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 16, 16);
> -
> - if (sf) {
> - tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
> - tcg_gen_andi_i64(tcg_tmp, tcg_tmp, 0xffff);
> - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
> - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 32, 16);
> -
> - tcg_gen_shri_i64(tcg_tmp, tcg_rn, 48);
> - tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
> - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, 48, 16);
> - }
> + tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
> + tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
> + tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
> + tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
> + tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
>
> tcg_temp_free_i64(tcg_tmp);
const leak! patch below -- cut with `git am --scissors'.
Emilio
---8<---
Signed-off-by: Emilio G. Cota <cota@braap.org>
---
target/arm/translate-a64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 883e9df..58ed4c6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4044,20 +4044,21 @@ static void handle_rev16(DisasContext *s, unsigned int sf,
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
+ tcg_temp_free_i64(mask);
tcg_temp_free_i64(tcg_tmp);
}
/* C3.5.7 Data-processing (1 source)
* 31 30 29 28 21 20 16 15 10 9 5 4 0
* +----+---+---+-----------------+---------+--------+------+------+
* | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
* +----+---+---+-----------------+---------+--------+------+------+
*/
static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH] target/arm: fix TCG temp leak in aarch64 rev16
2017-07-21 5:42 ` [Qemu-devel] [PATCH] target/arm: fix TCG temp leak in " Emilio G. Cota
@ 2017-07-21 13:16 ` Peter Maydell
2017-07-21 19:16 ` Emilio G. Cota
0 siblings, 1 reply; 19+ messages in thread
From: Peter Maydell @ 2017-07-21 13:16 UTC (permalink / raw)
To: Emilio G. Cota; +Cc: Richard Henderson, QEMU Developers
On 21 July 2017 at 06:42, Emilio G. Cota <cota@braap.org> wrote:
> const leak! patch below -- cut with `git am --scissors'.
>
> Emilio
>
> ---8<---
>
> Signed-off-by: Emilio G. Cota <cota@braap.org>
> ---
Applied to target-arm.next, thanks -- but in future could you
send patches as proper patch emails, please (output of
git format-patch, sent as its own top level email, not a
reply to an existing thread) ? Otherwise the automated tools
don't recognise them as patches and it requires some tedious
manual application at this end.
thanks
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH] target/arm: fix TCG temp leak in aarch64 rev16
2017-07-21 13:16 ` Peter Maydell
@ 2017-07-21 19:16 ` Emilio G. Cota
0 siblings, 0 replies; 19+ messages in thread
From: Emilio G. Cota @ 2017-07-21 19:16 UTC (permalink / raw)
To: Peter Maydell; +Cc: Richard Henderson, QEMU Developers
On Fri, Jul 21, 2017 at 14:16:46 +0100, Peter Maydell wrote:
> On 21 July 2017 at 06:42, Emilio G. Cota <cota@braap.org> wrote:
> > const leak! patch below -- cut with `git am --scissors'.
> >
> > Emilio
> >
> > ---8<---
> >
> > Signed-off-by: Emilio G. Cota <cota@braap.org>
> > ---
>
> Applied to target-arm.next, thanks -- but in future could you
> send patches as proper patch emails, please (output of
> git format-patch, sent as its own top level email, not a
> reply to an existing thread) ? Otherwise the automated tools
> don't recognise them as patches and it requires some tedious
> manual application at this end.
Will do, sorry about that.
E.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PULL v2 07/14] target/arm: optimize aarch32 rev16
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (5 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 06/14] target/arm: Optimize aarch64 rev16 Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 08/14] target/m68k: optimize bcd_flags() using extract op Richard Henderson
` (7 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Aurelien Jarno
From: Aurelien Jarno <aurelien@aurel32.net>
Use the same mask to avoid having to load two different constants, as
suggested by Richard Henderson.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170516230159.4195-2-aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/arm/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e27736ce5b..d3003ae0d8 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -343,11 +343,13 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b)
static void gen_rev16(TCGv_i32 var)
{
TCGv_i32 tmp = tcg_temp_new_i32();
+ TCGv_i32 mask = tcg_const_i32(0x00ff00ff);
tcg_gen_shri_i32(tmp, var, 8);
- tcg_gen_andi_i32(tmp, tmp, 0x00ff00ff);
+ tcg_gen_and_i32(tmp, tmp, mask);
+ tcg_gen_and_i32(var, var, mask);
tcg_gen_shli_i32(var, var, 8);
- tcg_gen_andi_i32(var, var, 0xff00ff00);
tcg_gen_or_i32(var, var, tmp);
+ tcg_temp_free_i32(mask);
tcg_temp_free_i32(tmp);
}
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 08/14] target/m68k: optimize bcd_flags() using extract op
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (6 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 07/14] target/arm: optimize aarch32 rev16 Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 09/14] target/ppc: optimize various functions " Richard Henderson
` (6 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718045540.16322-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/m68k/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 3a519b790d..e709e6cde2 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1749,8 +1749,7 @@ static void bcd_flags(TCGv val)
tcg_gen_andi_i32(QREG_CC_C, val, 0x0ff);
tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_C);
- tcg_gen_shri_i32(QREG_CC_C, val, 8);
- tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
+ tcg_gen_extract_i32(QREG_CC_C, val, 8, 1);
tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
}
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 09/14] target/ppc: optimize various functions using extract op
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (7 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 08/14] target/m68k: optimize bcd_flags() using extract op Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 10/14] target/sparc: " Richard Henderson
` (5 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20170718045540.16322-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/ppc/translate.c | 21 +++++++--------------
target/ppc/translate/vsx-impl.inc.c | 24 ++++++++----------------
2 files changed, 15 insertions(+), 30 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c0cd64d927..de271af52b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -873,8 +873,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
}
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
tcg_temp_free(t1);
- tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
- tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@@ -1404,8 +1403,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_temp_free(inv1);
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
tcg_temp_free(t1);
- tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
- tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@@ -4336,8 +4334,7 @@ static void gen_mfsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -4368,8 +4365,7 @@ static void gen_mtsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -4403,8 +4399,7 @@ static void gen_mfsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -4435,8 +4430,7 @@ static void gen_mtsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -5414,8 +5408,7 @@ static void gen_mfsri(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- tcg_gen_shri_tl(t0, t0, 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, t0, 28, 4);
gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
tcg_temp_free(t0);
if (ra != 0 && ra != rd)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 7f12908029..85ed135d44 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1248,8 +1248,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
- tcg_gen_andi_i64(rt, rt, 0x7FF);
+ tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11);
}
static void gen_xsxexpqp(DisasContext *ctx)
@@ -1262,8 +1261,7 @@ static void gen_xsxexpqp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- tcg_gen_shri_i64(xth, xbh, 48);
- tcg_gen_andi_i64(xth, xth, 0x7FFF);
+ tcg_gen_extract_i64(xth, xbh, 48, 15);
tcg_gen_movi_i64(xtl, 0);
}
@@ -1323,8 +1321,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
- tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
- tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@@ -1352,8 +1349,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(32767);
- tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
- tcg_gen_andi_i64(exp, exp, 0x7FFF);
+ tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@@ -1448,10 +1444,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- tcg_gen_shri_i64(xth, xbh, 52);
- tcg_gen_andi_i64(xth, xth, 0x7FF);
- tcg_gen_shri_i64(xtl, xbl, 52);
- tcg_gen_andi_i64(xtl, xtl, 0x7FF);
+ tcg_gen_extract_i64(xth, xbh, 52, 11);
+ tcg_gen_extract_i64(xtl, xbl, 52, 11);
}
GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
@@ -1474,16 +1468,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
- tcg_gen_shri_i64(exp, xbh, 52);
- tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
tcg_gen_or_i64(xth, xth, t0);
- tcg_gen_shri_i64(exp, xbl, 52);
- tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 10/14] target/sparc: optimize various functions using extract op
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (8 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 09/14] target/ppc: optimize various functions " Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 11/14] target/sparc: optimize gen_op_mulscc() using deposit op Richard Henderson
` (4 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/sparc/translate.c | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index aa6734d54e..67a83b77cc 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -380,29 +380,25 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num,
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_NEG_SHIFT, 1);
}
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_ZERO_SHIFT, 1);
}
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_OVF_SHIFT, 1);
}
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
{
tcg_gen_extu_i32_tl(reg, src);
- tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
- tcg_gen_andi_tl(reg, reg, 0x1);
+ tcg_gen_extract_tl(reg, reg, PSR_CARRY_SHIFT, 1);
}
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -638,8 +634,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
// env->y = (b2 << 31) | (env->y >> 1);
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
tcg_gen_shli_tl(r_temp, r_temp, 31);
- tcg_gen_shri_tl(t0, cpu_y, 1);
- tcg_gen_andi_tl(t0, t0, 0x7fffffff);
+ tcg_gen_extract_tl(t0, cpu_y, 1, 31);
tcg_gen_or_tl(t0, t0, r_temp);
tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 11/14] target/sparc: optimize gen_op_mulscc() using deposit op
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (9 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 10/14] target/sparc: " Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 12/14] target/alpha: optimize gen_cvtlq() " Richard Henderson
` (3 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-9-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/sparc/translate.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 67a83b77cc..d13173275f 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -632,11 +632,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
// b2 = T0 & 1;
// env->y = (b2 << 31) | (env->y >> 1);
- tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
- tcg_gen_shli_tl(r_temp, r_temp, 31);
tcg_gen_extract_tl(t0, cpu_y, 1, 31);
- tcg_gen_or_tl(t0, t0, r_temp);
- tcg_gen_andi_tl(cpu_y, t0, 0xffffffff);
+ tcg_gen_deposit_tl(cpu_y, t0, cpu_cc_src, 31, 1);
// b1 = N ^ V;
gen_mov_reg_N(t0, cpu_psr);
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 12/14] target/alpha: optimize gen_cvtlq() using deposit op
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (10 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 11/14] target/sparc: optimize gen_op_mulscc() using deposit op Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 13/14] tcg/tci: enable bswap16_i64 Richard Henderson
` (2 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20170718045540.16322-10-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/alpha/translate.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 90e6d5285f..744d8bbf12 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -783,11 +783,9 @@ static void gen_cvtlq(TCGv vc, TCGv vb)
/* The arithmetic right shift here, plus the sign-extended mask below
yields a sign-extended result without an explicit ext32s_i64. */
- tcg_gen_sari_i64(tmp, vb, 32);
- tcg_gen_shri_i64(vc, vb, 29);
- tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
- tcg_gen_andi_i64(vc, vc, 0x3fffffff);
- tcg_gen_or_i64(vc, vc, tmp);
+ tcg_gen_shri_i64(tmp, vb, 29);
+ tcg_gen_sari_i64(vc, vb, 32);
+ tcg_gen_deposit_i64(vc, vc, tmp, 0, 30);
tcg_temp_free(tmp);
}
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 13/14] tcg/tci: enable bswap16_i64
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (11 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 12/14] target/alpha: optimize gen_cvtlq() " Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 14/14] tcg: Pass generic CPUState to gen_intermediate_code() Richard Henderson
2017-07-20 11:03 ` [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé, Jaroslaw Pelczar
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Altough correctly implemented, bswap16_i64() never got tested/executed so the
safety TODO() statement was never removed.
Since it got now tested the TODO() can be removed.
while running Alex Bennée's image aarch64-linux-3.15rc2-buildroot.img:
Trace 0x7fa1904b0890 [0: ffffffc00036cd04]
----------------
IN:
0xffffffc00036cd24: 5ac00694 rev16 w20, w20
OP:
---- ffffffc00036cd24 0000000000000000 0000000000000000
ext32u_i64 tmp3,x20
ext16u_i64 tmp2,tmp3
bswap16_i64 x20,tmp2
movi_i64 tmp4,$0x10
shr_i64 tmp2,tmp3,tmp4
ext16u_i64 tmp2,tmp2
bswap16_i64 tmp2,tmp2
deposit_i64 x20,x20,tmp2,$0x10,$0x10
Linking TBs 0x7fa1904b0890 [ffffffc00036cd04] index 0 -> 0x7fa1904b0aa0 [ffffffc00036cd24]
Trace 0x7fa1904b0aa0 [0: ffffffc00036cd24]
TODO qemu/tci.c:1049: tcg_qemu_tb_exec()
qemu/tci.c:1049: tcg fatal error
Aborted
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Message-Id: <20170718045540.16322-11-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tci.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index 4bdc645f2a..f39bfb95c0 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -1046,7 +1046,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
break;
#if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64:
- TODO();
t0 = *tb_ptr++;
t1 = tci_read_r16(&tb_ptr);
tci_write_reg64(t0, bswap16(t1));
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PULL v2 14/14] tcg: Pass generic CPUState to gen_intermediate_code()
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (12 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 13/14] tcg/tci: enable bswap16_i64 Richard Henderson
@ 2017-07-19 23:34 ` Richard Henderson
2017-07-20 11:03 ` [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: Richard Henderson @ 2017-07-19 23:34 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Lluís Vilanova
From: Lluís Vilanova <vilanova@ac.upc.edu>
Needed to implement a target-agnostic gen_intermediate_code()
in the future.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
include/exec/exec-all.h | 2 +-
target/arm/translate.h | 4 ++--
accel/tcg/translate-all.c | 2 +-
target/alpha/translate.c | 5 ++---
target/arm/translate-a64.c | 6 +++---
target/arm/translate.c | 6 +++---
target/cris/translate.c | 7 +++----
target/hppa/translate.c | 5 ++---
target/i386/translate.c | 5 ++---
target/lm32/translate.c | 4 ++--
target/m68k/translate.c | 5 ++---
target/microblaze/translate.c | 4 ++--
target/mips/translate.c | 5 ++---
target/moxie/translate.c | 4 ++--
target/nios2/translate.c | 5 ++---
target/openrisc/translate.c | 4 ++--
target/ppc/translate.c | 5 ++---
target/s390x/translate.c | 5 ++---
target/sh4/translate.c | 5 ++---
target/sparc/translate.c | 5 ++---
target/tilegx/translate.c | 5 ++---
target/tricore/translate.c | 5 ++---
target/unicore32/translate.c | 5 ++---
target/xtensa/translate.c | 5 ++---
24 files changed, 49 insertions(+), 64 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 87b1b74e3b..440fc31b37 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -66,7 +66,7 @@ typedef ram_addr_t tb_page_addr_t;
#include "qemu/log.h"
-void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
target_ulong *data);
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 12fd79ba8e..2fe144baa9 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -149,7 +149,7 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
#ifdef TARGET_AARCH64
void a64_translate_init(void);
-void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
+void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb);
void gen_a64_set_pc_im(uint64_t val);
void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags);
@@ -158,7 +158,7 @@ static inline void a64_translate_init(void)
{
}
-static inline void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
+static inline void gen_intermediate_code_a64(CPUState *cpu, TranslationBlock *tb)
{
}
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 090ebad0a7..37ecafa931 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1280,7 +1280,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_func_start(&tcg_ctx);
tcg_ctx.cpu = ENV_GET_CPU(env);
- gen_intermediate_code(env, tb);
+ gen_intermediate_code(cpu, tb);
tcg_ctx.cpu = NULL;
trace_translate_block(tb, tb->pc, tb->tc_ptr);
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 744d8bbf12..f465752208 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2952,10 +2952,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return ret;
}
-void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUAlphaState *env = cs->env_ptr;
DisasContext ctx, *ctxp = &ctx;
target_ulong pc_start;
target_ulong pc_mask;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 5bb0f8ef22..883e9df0c2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11179,10 +11179,10 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s);
}
-void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
+void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
{
- CPUState *cs = CPU(cpu);
- CPUARMState *env = &cpu->env;
+ CPUARMState *env = cs->env_ptr;
+ ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d3003ae0d8..d1a5f56998 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11795,10 +11795,10 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
+ CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
target_ulong next_page_start;
@@ -11812,7 +11812,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
* the A32/T32 complexity to do with conditional execution/IT blocks/etc.
*/
if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
- gen_intermediate_code_a64(cpu, tb);
+ gen_intermediate_code_a64(cs, tb);
return;
}
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 0ee05ca02d..12b96eb68f 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3080,10 +3080,9 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
*/
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUCRISState *env = cs->env_ptr;
uint32_t pc_start;
unsigned int insn_len;
struct DisasContext ctx;
@@ -3105,7 +3104,7 @@ void gen_intermediate_code(CPUCRISState *env, struct TranslationBlock *tb)
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
- dc->cpu = cpu;
+ dc->cpu = cris_env_get_cpu(env);
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index e10abc5e04..900870cd5a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3740,10 +3740,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
return gen_illegal(ctx);
}
-void gen_intermediate_code(CPUHPPAState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- HPPACPU *cpu = hppa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUHPPAState *env = cs->env_ptr;
DisasContext ctx;
ExitStatus ret;
int num_insns, max_insns, i;
diff --git a/target/i386/translate.c b/target/i386/translate.c
index ed3b896db4..cab9e32f91 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -8378,10 +8378,9 @@ void tcg_x86_init(void)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUX86State *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_ptr;
uint32_t flags;
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index 692882f447..f68f372f15 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1044,10 +1044,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPULM32State *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
+ CPULM32State *env = cs->env_ptr;
LM32CPU *cpu = lm32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index e709e6cde2..ada2a91b64 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -5518,10 +5518,9 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUM68KState *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
int pc_offset;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index cb65d1e129..a24373c0be 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1625,10 +1625,10 @@ static inline void decode(DisasContext *dc, uint32_t ir)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUMBState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
+ CPUMBState *env = cs->env_ptr;
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
uint32_t pc_start;
struct DisasContext ctx;
struct DisasContext *dc = &ctx;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fe44f2f807..1fd18e9d2a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -19888,10 +19888,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-void gen_intermediate_code(CPUMIPSState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUMIPSState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
target_ulong next_page_start;
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
index 0660b44c08..3cfd232558 100644
--- a/target/moxie/translate.c
+++ b/target/moxie/translate.c
@@ -822,10 +822,10 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
+ CPUMoxieState *env = cs->env_ptr;
MoxieCPU *cpu = moxie_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 2f3c2e5dfb..8b97d6585f 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -799,10 +799,9 @@ static void gen_exception(DisasContext *dc, uint32_t excp)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUNios2State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
- Nios2CPU *cpu = nios2_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUNios2State *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
int num_insns;
int max_insns;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index e49518e893..a01413113b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1518,10 +1518,10 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
}
}
-void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
+ CPUOpenRISCState *env = cs->env_ptr;
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
struct DisasContext ctx, *dc = &ctx;
uint32_t pc_start;
uint32_t next_page_start;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index de271af52b..01233e8b6d 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7196,10 +7196,9 @@ void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
}
/*****************************************************************************/
-void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- PowerPCCPU *cpu = ppc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUPPCState *env = cs->env_ptr;
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;
target_ulong pc_start;
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 1dffcee884..48b71f9604 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5853,10 +5853,9 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
return ret;
}
-void gen_intermediate_code(CPUS390XState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- S390CPU *cpu = s390_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUS390XState *env = cs->env_ptr;
DisasContext dc;
target_ulong pc_start;
uint64_t next_page_start;
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 498bb99dc1..10191073b2 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2230,10 +2230,9 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
}
#endif
-void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUSH4State *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns;
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index d13173275f..3bde47be83 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5739,10 +5739,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
}
}
-void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
{
- SPARCCPU *cpu = sparc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUSPARCState *env = cs->env_ptr;
target_ulong pc_start, last_pc;
DisasContext dc1, *dc = &dc1;
int num_insns;
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index ff2ef7b63d..ace2830a84 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -2370,12 +2370,11 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
}
}
-void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- TileGXCPU *cpu = tilegx_env_get_cpu(env);
+ CPUTLGState *env = cs->env_ptr;
DisasContext ctx;
DisasContext *dc = &ctx;
- CPUState *cs = CPU(cpu);
uint64_t pc_start = tb->pc;
uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
int num_insns = 0;
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ddd2dd07dd..4e4198e887 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8782,10 +8782,9 @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
}
}
-void gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
{
- TriCoreCPU *cpu = tricore_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUTriCoreState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
int num_insns, max_insns;
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 666a2016a8..8f30cff932 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1869,10 +1869,9 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
}
/* generate intermediate code for basic block 'tb'. */
-void gen_intermediate_code(CPUUniCore32State *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUUniCore32State *env = cs->env_ptr;
DisasContext dc1, *dc = &dc1;
target_ulong pc_start;
uint32_t next_page_start;
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 263002486c..f3f0ff589c 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -3117,10 +3117,9 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
}
}
-void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUXtensaState *env = cs->env_ptr;
DisasContext dc;
int insn_count = 0;
int max_insns = tb->cflags & CF_COUNT_MASK;
--
2.13.3
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PULL v2 00/14] tcg-next patch queue
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
` (13 preceding siblings ...)
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 14/14] tcg: Pass generic CPUState to gen_intermediate_code() Richard Henderson
@ 2017-07-20 11:03 ` Peter Maydell
14 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2017-07-20 11:03 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers
On 20 July 2017 at 00:34, Richard Henderson <rth@twiddle.net> wrote:
> This edition is a real mix:
> * Code gen improvement for mips64 host (Jiang)
> * Build fix for ppc-linux (Philippe)
> * Runtime fix for tci (Philippe)
> * Fix atomic helper names in debugging dumps (rth)
>
> * Cross-target tcg code gen improvements (Philippe)
> This one had no obvious tree through which it should go,
> so I went ahead and took them all.
>
> * Cherry-picked the first patch from Lluis' generic translate loop,
> wherein the interface to gen_intermediate_code changes trivially.
> It's the only patch from that series that touches all targets,
> and I see little point carrying it around further.
>
> V2: Fixed typo in the sparc mulscc deposit patch.
>
>
> r~
>
>
> The following changes since commit d4e59218ab80e86015753782fb5378767a51ccd0:
>
> Merge remote-tracking branch 'remotes/berrange/tags/pull-qcrypto-2017-07-18-2' into staging (2017-07-19 20:45:37 +0100)
>
> are available in the git repository at:
>
> git://github.com/rth7680/qemu.git tags/pull-tcg-20170719
>
> for you to fetch changes up to 9c489ea6bed134fecfd556b439c68bba48fbe102:
>
> tcg: Pass generic CPUState to gen_intermediate_code() (2017-07-19 14:45:16 -0700)
>
> ----------------------------------------------------------------
> Queued tcg and tcg code gen related cleanups
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread