From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PULL v2 09/14] target/ppc: optimize various functions using extract op
Date: Wed, 19 Jul 2017 13:34:50 -1000 [thread overview]
Message-ID: <20170719233455.8740-10-rth@twiddle.net> (raw)
In-Reply-To: <20170719233455.8740-1-rth@twiddle.net>
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20170718045540.16322-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target/ppc/translate.c | 21 +++++++--------------
target/ppc/translate/vsx-impl.inc.c | 24 ++++++++----------------
2 files changed, 15 insertions(+), 30 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index c0cd64d927..de271af52b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -873,8 +873,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
}
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
tcg_temp_free(t1);
- tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
- tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@@ -1404,8 +1403,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_temp_free(inv1);
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
tcg_temp_free(t1);
- tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
- tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
+ tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@@ -4336,8 +4334,7 @@ static void gen_mfsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -4368,8 +4365,7 @@ static void gen_mtsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -4403,8 +4399,7 @@ static void gen_mfsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -4435,8 +4430,7 @@ static void gen_mtsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
- tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@@ -5414,8 +5408,7 @@ static void gen_mfsri(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
- tcg_gen_shri_tl(t0, t0, 28);
- tcg_gen_andi_tl(t0, t0, 0xF);
+ tcg_gen_extract_tl(t0, t0, 28, 4);
gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
tcg_temp_free(t0);
if (ra != 0 && ra != rd)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 7f12908029..85ed135d44 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1248,8 +1248,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
- tcg_gen_andi_i64(rt, rt, 0x7FF);
+ tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11);
}
static void gen_xsxexpqp(DisasContext *ctx)
@@ -1262,8 +1261,7 @@ static void gen_xsxexpqp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- tcg_gen_shri_i64(xth, xbh, 48);
- tcg_gen_andi_i64(xth, xth, 0x7FFF);
+ tcg_gen_extract_i64(xth, xbh, 48, 15);
tcg_gen_movi_i64(xtl, 0);
}
@@ -1323,8 +1321,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
- tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
- tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@@ -1352,8 +1349,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(32767);
- tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
- tcg_gen_andi_i64(exp, exp, 0x7FFF);
+ tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@@ -1448,10 +1444,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
- tcg_gen_shri_i64(xth, xbh, 52);
- tcg_gen_andi_i64(xth, xth, 0x7FF);
- tcg_gen_shri_i64(xtl, xbl, 52);
- tcg_gen_andi_i64(xtl, xtl, 0x7FF);
+ tcg_gen_extract_i64(xth, xbh, 52, 11);
+ tcg_gen_extract_i64(xtl, xbl, 52, 11);
}
GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
@@ -1474,16 +1468,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
- tcg_gen_shri_i64(exp, xbh, 52);
- tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
tcg_gen_or_i64(xth, xth, t0);
- tcg_gen_shri_i64(exp, xbl, 52);
- tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
--
2.13.3
next prev parent reply other threads:[~2017-07-19 23:36 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-19 23:34 [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 01/14] tcg/mips: reserve a register for the guest_base Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 02/14] util/cacheinfo: Add missing include for ppc linux Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 03/14] tcg: Expand glue macros before stringifying helper names Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 04/14] coccinelle: ignore ASTs pre-parsed cached C files Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 05/14] coccinelle: add a script to optimize tcg op using tcg_gen_extract() Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 06/14] target/arm: Optimize aarch64 rev16 Richard Henderson
2017-07-21 5:42 ` [Qemu-devel] [PATCH] target/arm: fix TCG temp leak in " Emilio G. Cota
2017-07-21 13:16 ` Peter Maydell
2017-07-21 19:16 ` Emilio G. Cota
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 07/14] target/arm: optimize aarch32 rev16 Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 08/14] target/m68k: optimize bcd_flags() using extract op Richard Henderson
2017-07-19 23:34 ` Richard Henderson [this message]
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 10/14] target/sparc: optimize various functions " Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 11/14] target/sparc: optimize gen_op_mulscc() using deposit op Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 12/14] target/alpha: optimize gen_cvtlq() " Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 13/14] tcg/tci: enable bswap16_i64 Richard Henderson
2017-07-19 23:34 ` [Qemu-devel] [PULL v2 14/14] tcg: Pass generic CPUState to gen_intermediate_code() Richard Henderson
2017-07-20 11:03 ` [Qemu-devel] [PULL v2 00/14] tcg-next patch queue Peter Maydell
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