* [Qemu-devel] [RFC PATCH] booke206: fix MAS update on tlb miss
@ 2017-08-01 8:44 KONRAD Frederic
2017-08-02 0:43 ` David Gibson
2017-08-03 11:37 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
0 siblings, 2 replies; 6+ messages in thread
From: KONRAD Frederic @ 2017-08-01 8:44 UTC (permalink / raw)
To: david, agraf; +Cc: qemu-devel, qemu-ppc, frederic.konrad
When a tlb instruction miss happen, rw is set to 0 at the bottom
of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
target/ppc/mmu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index b7b9088..f06b938 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
env->spr[SPR_40x_ESR] = 0x00000000;
break;
case POWERPC_MMU_BOOKE206:
- booke206_update_mas_tlb_miss(env, address, rw);
+ booke206_update_mas_tlb_miss(env, address, 2);
/* fall through */
case POWERPC_MMU_BOOKE:
cs->exception_index = POWERPC_EXCP_ITLB;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [Qemu-devel] [RFC PATCH] booke206: fix MAS update on tlb miss
2017-08-01 8:44 [Qemu-devel] [RFC PATCH] booke206: fix MAS update on tlb miss KONRAD Frederic
@ 2017-08-02 0:43 ` David Gibson
2017-08-03 11:37 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
1 sibling, 0 replies; 6+ messages in thread
From: David Gibson @ 2017-08-02 0:43 UTC (permalink / raw)
To: KONRAD Frederic; +Cc: agraf, qemu-devel, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 1445 bytes --]
On Tue, Aug 01, 2017 at 10:44:57AM +0200, KONRAD Frederic wrote:
> When a tlb instruction miss happen, rw is set to 0 at the bottom
> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
> the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
>
> Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Applied to ppc-for-2.10.
> ---
> target/ppc/mmu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index b7b9088..f06b938 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> env->spr[SPR_40x_ESR] = 0x00000000;
> break;
> case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, address, rw);
> + booke206_update_mas_tlb_miss(env, address, 2);
> /* fall through */
> case POWERPC_MMU_BOOKE:
> cs->exception_index = POWERPC_EXCP_ITLB;
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH] booke206: fix MAS update on tlb miss
2017-08-01 8:44 [Qemu-devel] [RFC PATCH] booke206: fix MAS update on tlb miss KONRAD Frederic
2017-08-02 0:43 ` David Gibson
@ 2017-08-03 11:37 ` Thomas Huth
2017-08-03 12:08 ` KONRAD Frederic
1 sibling, 1 reply; 6+ messages in thread
From: Thomas Huth @ 2017-08-03 11:37 UTC (permalink / raw)
To: KONRAD Frederic, david, agraf; +Cc: qemu-ppc, qemu-devel
On 01.08.2017 10:44, KONRAD Frederic wrote:
> When a tlb instruction miss happen, rw is set to 0 at the bottom
> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
> the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
>
> Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> target/ppc/mmu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index b7b9088..f06b938 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> env->spr[SPR_40x_ESR] = 0x00000000;
> break;
> case POWERPC_MMU_BOOKE206:
> - booke206_update_mas_tlb_miss(env, address, rw);
> + booke206_update_mas_tlb_miss(env, address, 2);
Couldn't that code path be called for normal data read miss (instead of
instruction miss), too?
Anyway, could we please use MMU_INST_FETCH instead of magic values like
2 here?
Thomas
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH] booke206: fix MAS update on tlb miss
2017-08-03 11:37 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
@ 2017-08-03 12:08 ` KONRAD Frederic
2017-08-03 13:13 ` Thomas Huth
0 siblings, 1 reply; 6+ messages in thread
From: KONRAD Frederic @ 2017-08-03 12:08 UTC (permalink / raw)
To: Thomas Huth; +Cc: david, agraf, qemu-ppc, qemu-devel
On 08/03/2017 01:37 PM, Thomas Huth wrote:
> On 01.08.2017 10:44, KONRAD Frederic wrote:
>> When a tlb instruction miss happen, rw is set to 0 at the bottom
>> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
>> the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
>>
>> Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
>>
>> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
>> ---
>> target/ppc/mmu_helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>> index b7b9088..f06b938 100644
>> --- a/target/ppc/mmu_helper.c
>> +++ b/target/ppc/mmu_helper.c
>> @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
>> env->spr[SPR_40x_ESR] = 0x00000000;
>> break;
>> case POWERPC_MMU_BOOKE206:
>> - booke206_update_mas_tlb_miss(env, address, rw);
>> + booke206_update_mas_tlb_miss(env, address, 2);
>
Hi Thomas,
> Couldn't that code path be called for normal data read miss (instead of
> instruction miss), too?
>
I don't think so because we have access_type == ACCESS_CODE and
the code in cpu_ppc_handle_mmu_fault explicitely split the CODE
and DATA cases.
> Anyway, could we please use MMU_INST_FETCH instead of magic values like
> 2 here?
I agree it's not nice to have a magic value like this.. But it's
used all over the code there and david took the patch.
So I suggest I send a second patch to fix all the instances of
that magic value.
Fred
>
> Thomas
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH] booke206: fix MAS update on tlb miss
2017-08-03 12:08 ` KONRAD Frederic
@ 2017-08-03 13:13 ` Thomas Huth
2017-08-07 12:49 ` KONRAD Frederic
0 siblings, 1 reply; 6+ messages in thread
From: Thomas Huth @ 2017-08-03 13:13 UTC (permalink / raw)
To: KONRAD Frederic; +Cc: david, agraf, qemu-ppc, qemu-devel
On 03.08.2017 14:08, KONRAD Frederic wrote:
>
>
> On 08/03/2017 01:37 PM, Thomas Huth wrote:
>> On 01.08.2017 10:44, KONRAD Frederic wrote:
>>> When a tlb instruction miss happen, rw is set to 0 at the bottom
>>> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
>>> the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
>>>
>>> Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
>>>
>>> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
>>> ---
>>> target/ppc/mmu_helper.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>>> index b7b9088..f06b938 100644
>>> --- a/target/ppc/mmu_helper.c
>>> +++ b/target/ppc/mmu_helper.c
>>> @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState
>>> *env, target_ulong address,
>>> env->spr[SPR_40x_ESR] = 0x00000000;
>>> break;
>>> case POWERPC_MMU_BOOKE206:
>>> - booke206_update_mas_tlb_miss(env, address, rw);
>>> + booke206_update_mas_tlb_miss(env, address, 2);
>>
> Hi Thomas,
>
>> Couldn't that code path be called for normal data read miss (instead of
>> instruction miss), too?
>>
>
> I don't think so because we have access_type == ACCESS_CODE and
> the code in cpu_ppc_handle_mmu_fault explicitely split the CODE
> and DATA cases.
Ah, right, I missed that if-statement. So never mind about my comment!
>> Anyway, could we please use MMU_INST_FETCH instead of magic values like
>> 2 here?
>
> I agree it's not nice to have a magic value like this.. But it's
> used all over the code there and david took the patch.
>
> So I suggest I send a second patch to fix all the instances of
> that magic value.
Sounds like a good idea!
Thanks,
Thomas
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [Qemu-ppc] [RFC PATCH] booke206: fix MAS update on tlb miss
2017-08-03 13:13 ` Thomas Huth
@ 2017-08-07 12:49 ` KONRAD Frederic
0 siblings, 0 replies; 6+ messages in thread
From: KONRAD Frederic @ 2017-08-07 12:49 UTC (permalink / raw)
To: Thomas Huth; +Cc: david, agraf, qemu-ppc, qemu-devel
On 08/03/2017 03:13 PM, Thomas Huth wrote:
> On 03.08.2017 14:08, KONRAD Frederic wrote:
>>
>>
>> On 08/03/2017 01:37 PM, Thomas Huth wrote:
>>> On 01.08.2017 10:44, KONRAD Frederic wrote:
>>>> When a tlb instruction miss happen, rw is set to 0 at the bottom
>>>> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
>>>> the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
>>>>
>>>> Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue.
>>>>
>>>> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
>>>> ---
>>>> target/ppc/mmu_helper.c | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
>>>> index b7b9088..f06b938 100644
>>>> --- a/target/ppc/mmu_helper.c
>>>> +++ b/target/ppc/mmu_helper.c
>>>> @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState
>>>> *env, target_ulong address,
>>>> env->spr[SPR_40x_ESR] = 0x00000000;
>>>> break;
>>>> case POWERPC_MMU_BOOKE206:
>>>> - booke206_update_mas_tlb_miss(env, address, rw);
>>>> + booke206_update_mas_tlb_miss(env, address, 2);
>>>
>> Hi Thomas,
>>
>>> Couldn't that code path be called for normal data read miss (instead of
>>> instruction miss), too?
>>>
>>
>> I don't think so because we have access_type == ACCESS_CODE and
>> the code in cpu_ppc_handle_mmu_fault explicitely split the CODE
>> and DATA cases.
>
> Ah, right, I missed that if-statement. So never mind about my comment!
>
>>> Anyway, could we please use MMU_INST_FETCH instead of magic values like
>>> 2 here?
>>
>> I agree it's not nice to have a magic value like this.. But it's
>> used all over the code there and david took the patch.
>>
>> So I suggest I send a second patch to fix all the instances of
>> that magic value.
>
> Sounds like a good idea!
Hi Thomas,
Looking more in details at this magic value, it seems rw is
not considered as an access type but more as an is_write boolean.
The whole mmu code use "int access_type" which is kind of
redundant / confusing if we change rw to be MMUAccessType.
Fred
>
> Thanks,
> Thomas
>
^ permalink raw reply [flat|nested] 6+ messages in thread
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2017-08-01 8:44 [Qemu-devel] [RFC PATCH] booke206: fix MAS update on tlb miss KONRAD Frederic
2017-08-02 0:43 ` David Gibson
2017-08-03 11:37 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
2017-08-03 12:08 ` KONRAD Frederic
2017-08-03 13:13 ` Thomas Huth
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