[Qemu-devel] [PULL for-2.10 0/3] TCG misc patches

[Qemu-devel] [PULL for-2.10 0/3] TCG misc patches

[Richard Henderson]

Two of these have been posted before.  The third I discovered in
testing on a Sparc host yesterday.


r~


The following changes since commit aaaec6acad7cf97372d48c1b09126a09697519c8:

  Update version for v2.10.0-rc1 release (2017-08-02 16:36:32 +0100)

are available in the git repository at:

  git://github.com/rth7680/qemu.git tags/pull-tcg-20170803

for you to fetch changes up to 13aaef678ed377b12b76dc7fb9e615b2f2f9047b:

  tcg: Increase minimum alignment from tcg_malloc to 8 (2017-08-03 11:00:30 -0700)

----------------------------------------------------------------
Queued misc tcg patches

----------------------------------------------------------------
Richard Henderson (3):
      tcg/arm: Fix runtime overalignment test
      target/s390x: Fix CSST for 16-byte store
      tcg: Increase minimum alignment from tcg_malloc to 8

 tcg/tcg.h                 | 5 ++++-
 target/s390x/mem_helper.c | 1 +
 tcg/arm/tcg-target.inc.c  | 2 +-
 3 files changed, 6 insertions(+), 2 deletions(-)

[Qemu-devel] [PULL for-2.10 1/3] tcg/arm: Fix runtime overalignment test

[Richard Henderson]

Patch 85aa80813dd changed the IF emitting the TST instruction,
but failed to change the ?: converting CMP to CMPEQ, so the
result of the TST is ignored.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/arm/tcg-target.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index d1793ec77d..37efcf06af 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -1223,7 +1223,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
     /* Load the tlb addend.  */
     tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R2, add_off);
 
-    tcg_out_dat_reg(s, (s_bits ? COND_EQ : COND_AL), ARITH_CMP, 0,
+    tcg_out_dat_reg(s, (a_bits ? COND_EQ : COND_AL), ARITH_CMP, 0,
                     TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
 
     if (TARGET_LONG_BITS == 64) {
-- 
2.13.3

[Qemu-devel] [PULL for-2.10 2/3] target/s390x: Fix CSST for 16-byte store

[Richard Henderson]

Found by Coverity (CID 1378273).

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target/s390x/mem_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index cdc78aa3d4..c71dce4b1e 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -1580,6 +1580,7 @@ uint32_t HELPER(csst)(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2)
                 cpu_stq_data_ra(env, a2 + 0, svh, ra);
                 cpu_stq_data_ra(env, a2 + 8, svl, ra);
             }
+            break;
         default:
             g_assert_not_reached();
         }
-- 
2.13.3

[Qemu-devel] [PULL for-2.10 3/3] tcg: Increase minimum alignment from tcg_malloc to 8

[Richard Henderson]

For a 64-bit ILP32 host, aligning to sizeof(long) is not enough.
Guess the minimum for any host is 8, as that covers uint64_t.
Qemu doesn't use a host long double or host vectors, except in
extremely limited circumstances.

Fixes a bus error for a sparc v8plus host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tcg/tcg.h b/tcg/tcg.h
index da78721a0d..17b7750ee6 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -762,7 +762,10 @@ static inline void *tcg_malloc(int size)
 {
     TCGContext *s = &tcg_ctx;
     uint8_t *ptr, *ptr_end;
-    size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
+
+    /* ??? This is a weak placeholder for minimum malloc alignment.  */
+    size = QEMU_ALIGN_UP(size, 8);
+
     ptr = s->pool_cur;
     ptr_end = ptr + size;
     if (unlikely(ptr_end > s->pool_end)) {
-- 
2.13.3

[Qemu-devel] [PULL for-2.10 3/3] tcg: Increase minimum alignment from tcg_malloc to 8

[Richard Henderson]

For a 64-bit ILP32 host, aligning to sizeof(long) is not enough.
Guess the minimum for any host is 8, as that covers uint64_t.
Qemu doesn't use a host long double or host vectors, except in
extremely limited circumstances.

Fixes a bus error for a sparc v8plus host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tcg/tcg.h b/tcg/tcg.h
index da78721a0d..17b7750ee6 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -762,7 +762,10 @@ static inline void *tcg_malloc(int size)
 {
     TCGContext *s = &tcg_ctx;
     uint8_t *ptr, *ptr_end;
-    size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
+
+    /* ??? This is a weak placeholder for minimum malloc alignment.  */
+    size = QEMU_ALIGN_UP(size, 8);
+
     ptr = s->pool_cur;
     ptr_end = ptr + size;
     if (unlikely(ptr_end > s->pool_end)) {
-- 
2.13.3

Re: [Qemu-devel] [PULL for-2.10 0/3] TCG misc patches

[Peter Maydell]

On 3 August 2017 at 19:12, Richard Henderson <rth@twiddle.net> wrote:
> Two of these have been posted before.  The third I discovered in
> testing on a Sparc host yesterday.
>
>
> r~
>
>
> The following changes since commit aaaec6acad7cf97372d48c1b09126a09697519c8:
>
>   Update version for v2.10.0-rc1 release (2017-08-02 16:36:32 +0100)
>
> are available in the git repository at:
>
>   git://github.com/rth7680/qemu.git tags/pull-tcg-20170803
>
> for you to fetch changes up to 13aaef678ed377b12b76dc7fb9e615b2f2f9047b:
>
>   tcg: Increase minimum alignment from tcg_malloc to 8 (2017-08-03 11:00:30 -0700)
>
> ----------------------------------------------------------------
> Queued misc tcg patches
>
> ----------------------------------------------------------------
> Richard Henderson (3):
>       tcg/arm: Fix runtime overalignment test
>       target/s390x: Fix CSST for 16-byte store
>       tcg: Increase minimum alignment from tcg_malloc to 8
>

Applied, thanks.

-- PMM