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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	Richard Henderson <rth@twiddle.net>,
	patches@linaro.org
Subject: Re: [Qemu-devel] [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook
Date: Sat, 5 Aug 2017 03:44:55 +0200	[thread overview]
Message-ID: <20170805014455.GF4859@toto> (raw)
In-Reply-To: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org>

On Fri, Aug 04, 2017 at 06:20:49PM +0100, Peter Maydell wrote:
> Implement the new do_transaction_failed hook for ARM, which should
> cause the CPU to take a prefetch abort or data abort.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  target/arm/internals.h | 10 ++++++++++
>  target/arm/cpu.c       |  1 +
>  target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 54 insertions(+)
> 
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index a3adbd8..13bb001 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>                                   MMUAccessType access_type,
>                                   int mmu_idx, uintptr_t retaddr);
>  
> +/* arm_cpu_do_transaction_failed: handle a memory system error response
> + * (eg "no device/memory present at address") by raising an external abort
> + * exception
> + */
> +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> +                                   vaddr addr, unsigned size,
> +                                   MMUAccessType access_type,
> +                                   int mmu_idx, MemTxAttrs attrs,
> +                                   MemTxResult response, uintptr_t retaddr);
> +
>  /* Call the EL change hook if one has been registered */
>  static inline void arm_call_el_change_hook(ARMCPU *cpu)
>  {
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 05c038b..6baede0 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
>  #else
>      cc->do_interrupt = arm_cpu_do_interrupt;
>      cc->do_unaligned_access = arm_cpu_do_unaligned_access;
> +    cc->do_transaction_failed = arm_cpu_do_transaction_failed;
>      cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
>      cc->asidx_from_attrs = arm_asidx_from_attrs;
>      cc->vmsd = &vmstate_arm_cpu;
> diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
> index 7eac272..54b6dd8 100644
> --- a/target/arm/op_helper.c
> +++ b/target/arm/op_helper.c
> @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
>      deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi);
>  }
>  
> +/* arm_cpu_do_transaction_failed: handle a memory system error response
> + * (eg "no device/memory present at address") by raising an external abort
> + * exception
> + */
> +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> +                                   vaddr addr, unsigned size,
> +                                   MMUAccessType access_type,
> +                                   int mmu_idx, MemTxAttrs attrs,
> +                                   MemTxResult response, uintptr_t retaddr)
> +{
> +    ARMCPU *cpu = ARM_CPU(cs);
> +    CPUARMState *env = &cpu->env;
> +    uint32_t fsr, fsc;
> +    ARMMMUFaultInfo fi = {};
> +    ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx);
> +
> +    if (retaddr) {
> +        /* now we have a real cpu fault */
> +        cpu_restore_state(cs, retaddr);
> +    }
> +
> +    /* The EA bit in syndromes and fault status registers is an
> +     * IMPDEF classification of external aborts. ARM implementations
> +     * usually use this to indicate AXI bus Decode error (0) or
> +     * Slave error (1); in QEMU we follow that.
> +     */
> +    fi.ea = (response != MEMTX_DECODE_ERROR);
> +
> +    /* The fault status register format depends on whether we're using
> +     * the LPAE long descriptor format, or the short descriptor format.
> +     */
> +    if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) {
> +        /* long descriptor form, STATUS 0b010000: synchronous ext abort */
> +        fsr = (fi.ea << 12) | (1 << 9) | 0x10;
> +    } else {
> +        /* short descriptor form, FSR 0b01000 : synchronous ext abort */
> +        fsr = (fi.ea << 12) | 0x8;
> +    }
> +    fsc = 0x10;
> +
> +    deliver_fault(cpu, addr, access_type, fsr, fsc, &fi);
> +}
> +
>  #endif /* !defined(CONFIG_USER_ONLY) */
>  
>  uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
> -- 
> 2.7.4
> 
> 

      parent reply	other threads:[~2017-08-05  1:45 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-04 17:20 [Qemu-devel] [PATCH 0/8] Implement ARM external abort handling Peter Maydell
2017-08-04 17:20 ` [Qemu-devel] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h Peter Maydell
2017-08-04 17:47   ` Richard Henderson
2017-08-05  0:59   ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2017-08-07 23:11     ` Alistair Francis
2017-08-04 17:20 ` [Qemu-devel] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook Peter Maydell
2017-08-04 18:42   ` Richard Henderson
2017-08-05  1:06   ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2017-08-05 16:51     ` Peter Maydell
2017-08-05  1:12   ` Edgar E. Iglesias
2017-08-05 17:18     ` Peter Maydell
2017-08-04 17:20 ` [Qemu-devel] [PATCH 3/8] cputlb: Support generating CPU exceptions on memory transaction failures Peter Maydell
2017-08-05  1:15   ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2017-12-13 16:39   ` Peter Maydell
2017-12-14  9:03     ` Paolo Bonzini
2017-08-04 17:20 ` [Qemu-devel] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures Peter Maydell
2017-08-04 18:09   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2017-08-04 19:23     ` Richard Henderson
2017-08-05 10:13       ` Peter Maydell
2017-08-17 10:25         ` Peter Maydell
2017-08-22  3:45           ` Philippe Mathieu-Daudé
2017-08-22  8:36             ` Peter Maydell
     [not found]               ` <CAFEAcA_rSqsrfd_qJijtPFRe1qKEA=JiyHE+3J5atAgxAX8NBg@mail.gmail.com>
2017-08-24 20:28                 ` Richard Henderson
2017-08-25 12:02                   ` Peter Maydell
2017-08-05 10:29     ` Peter Maydell
2017-08-05  1:23   ` Edgar E. Iglesias
2017-08-04 17:20 ` [Qemu-devel] [PATCH 5/8] hw/arm: Set ignore_memory_transaction_failures for most ARM boards Peter Maydell
2017-08-05  1:24   ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2017-08-04 17:20 ` [Qemu-devel] [PATCH 6/8] target/arm: Factor out fault delivery code Peter Maydell
2017-08-04 20:10   ` Richard Henderson
2017-08-05  1:40   ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2017-08-04 17:20 ` [Qemu-devel] [PATCH 7/8] target/arm: Allow deliver_fault() caller to specify EA bit Peter Maydell
2017-08-04 20:15   ` Richard Henderson
2017-08-05  1:45   ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2017-08-04 17:20 ` [Qemu-devel] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook Peter Maydell
2017-08-04 20:26   ` Richard Henderson
2017-08-05  1:44   ` Edgar E. Iglesias [this message]

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