From: Greg Kurz <groug@kaod.org>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: David Gibson <david@gibson.dropbear.id.au>,
mdroth@linux.vnet.ibm.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org, aik@ozlabs.ru, agraf@suse.de
Subject: Re: [Qemu-devel] [PATCH for-2.10 2/2] target/ppc: Add stub implementation of the PSSCR
Date: Tue, 8 Aug 2017 12:54:51 +0200 [thread overview]
Message-ID: <20170808125451.3281c2ce@bahia.lan> (raw)
In-Reply-To: <96975486-48cd-1ccc-209c-3f06f73f5d0e@kaod.org>
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On Tue, 8 Aug 2017 11:19:58 +0200
Cédric Le Goater <clg@kaod.org> wrote:
> On 08/08/2017 08:08 AM, David Gibson wrote:
> > The PSSCR register added in POWER9 controls certain power saving mode
> > behaviours. Mostly, it's not relevant to TCG, however because qemu
> > doesn't know about it yet, it doesn't synchronize the state with KVM,
> > and thus it doesn't get migrated.
> >
> > To fix that, this adds a minimal stub implementation of the register.
> > This isn't complete, even to the extent that an implementation is
> > possible in TCG, just enough to get migration working. We need to
> > come back later and at least properly filter the various fields in the
> > register based on privilege level.
>
> yes a lot of the fields are only accessible to the hypervisor, and the
> hypervisor also uses a different SPR number to access the PSSCR bits.
>
This patch uses 0x357 (855) which is the SPR number for hypervisor state
access. But, yes, part of the register is also accessible in privileged
non-hypervisor state with SPR number 0x337 (823). This will have to be
covered later, but for now:
Reviewed-by: Greg Kurz <groug@kaod.org>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>
> C.
>
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > target/ppc/cpu.h | 1 +
> > target/ppc/translate_init.c | 5 +++++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index f6e5413fad..46d3dd88f6 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -1771,6 +1771,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
> > #define SPR_IC (0x350)
> > #define SPR_VTB (0x351)
> > #define SPR_MMCRC (0x353)
> > +#define SPR_PSSCR (0x357)
> > #define SPR_440_INV0 (0x370)
> > #define SPR_440_INV1 (0x371)
> > #define SPR_440_INV2 (0x372)
> > diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> > index 94800cd29d..8fb407ed73 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -8846,6 +8846,11 @@ static void init_proc_POWER9(CPUPPCState *env)
> > spr_read_generic, spr_write_generic,
> > KVM_REG_PPC_TIDR, 0);
> >
> > + /* FIXME: Filter fields properly based on privilege level */
> > + spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
> > + spr_read_generic, spr_write_generic,
> > + KVM_REG_PPC_PSSCR, 0);
> > +
> > /* env variables */
> > #if !defined(CONFIG_USER_ONLY)
> > env->slb_nr = 32;
> >
>
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next prev parent reply other threads:[~2017-08-08 10:55 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-08 6:08 [Qemu-devel] [PATCH for-2.10 0/2] Add some missing POWER9 SPRs for migration David Gibson
2017-08-08 6:08 ` [Qemu-devel] [PATCH for-2.10 1/2] target/ppc: Implement TIDR David Gibson
2017-08-08 9:13 ` Cédric Le Goater
2017-08-08 10:23 ` Greg Kurz
2017-08-08 11:08 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
2017-08-08 6:08 ` [Qemu-devel] [PATCH for-2.10 2/2] target/ppc: Add stub implementation of the PSSCR David Gibson
2017-08-08 9:19 ` Cédric Le Goater
2017-08-08 10:54 ` Greg Kurz [this message]
2017-08-08 12:44 ` David Gibson
2017-08-08 11:49 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
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