* [Qemu-devel] [PATCH 1/8] mips: move hw/mips/cputimer.c to target/mips/
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
@ 2017-08-17 4:30 ` Philippe Mathieu-Daudé
2017-08-17 4:30 ` [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h Philippe Mathieu-Daudé
` (8 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:30 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: Philippe Mathieu-Daudé, qemu-devel, Eduardo Habkost,
James Hogan, Thomas Huth, Peter Maydell
This timer is a required part of the MIPS32/MIPS64 System Control coprocessor
(CP0). Moving it with the other architecture related files will allow an opaque
use of CPUMIPSState* in the next commit (introduce "internal.h").
also remove it from 'user' targets, remove an unnecessary include.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/cputimer.c => target/mips/cp0_timer.c | 1 -
hw/mips/Makefile.objs | 2 +-
target/mips/Makefile.objs | 2 +-
3 files changed, 2 insertions(+), 3 deletions(-)
rename hw/mips/cputimer.c => target/mips/cp0_timer.c (99%)
diff --git a/hw/mips/cputimer.c b/target/mips/cp0_timer.c
similarity index 99%
rename from hw/mips/cputimer.c
rename to target/mips/cp0_timer.c
index 8a166b3ea7..a9a58c5604 100644
--- a/hw/mips/cputimer.c
+++ b/target/mips/cp0_timer.c
@@ -21,7 +21,6 @@
*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
#include "hw/mips/cpudevs.h"
#include "qemu/timer.h"
#include "sysemu/kvm.h"
diff --git a/hw/mips/Makefile.objs b/hw/mips/Makefile.objs
index 48cd2ef50e..17a311aaba 100644
--- a/hw/mips/Makefile.objs
+++ b/hw/mips/Makefile.objs
@@ -1,5 +1,5 @@
obj-y += mips_r4k.o mips_malta.o mips_mipssim.o
-obj-y += addr.o cputimer.o mips_int.o
+obj-y += addr.o mips_int.o
obj-$(CONFIG_JAZZ) += mips_jazz.o
obj-$(CONFIG_FULONG) += mips_fulong2e.o
obj-y += gt64xxx_pci.o
diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs
index bc5ed8511f..651f36f517 100644
--- a/target/mips/Makefile.objs
+++ b/target/mips/Makefile.objs
@@ -1,4 +1,4 @@
obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o
obj-y += gdbstub.o msa_helper.o mips-semi.o
-obj-$(CONFIG_SOFTMMU) += machine.o
+obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o
obj-$(CONFIG_KVM) += kvm.o
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
2017-08-17 4:30 ` [Qemu-devel] [PATCH 1/8] mips: move hw/mips/cputimer.c to target/mips/ Philippe Mathieu-Daudé
@ 2017-08-17 4:30 ` Philippe Mathieu-Daudé
2017-08-17 14:38 ` Igor Mammedov
2017-08-17 4:30 ` [Qemu-devel] [PATCH 3/8] mips: split cpu_mips_realize_env() out of cpu_mips_init() Philippe Mathieu-Daudé
` (7 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:30 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: Philippe Mathieu-Daudé, qemu-devel, Eduardo Habkost,
James Hogan, Thomas Huth, Peter Maydell
no logical change, only code movement (and fix a comment typo).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 354 +--------------------------------------------
target/mips/internal.h | 362 +++++++++++++++++++++++++++++++++++++++++++++++
target/mips/cp0_timer.c | 1 +
target/mips/cpu.c | 1 +
target/mips/gdbstub.c | 1 +
target/mips/helper.c | 1 +
target/mips/kvm.c | 1 +
target/mips/machine.c | 1 +
target/mips/msa_helper.c | 1 +
target/mips/op_helper.c | 1 +
target/mips/translate.c | 1 +
11 files changed, 372 insertions(+), 353 deletions(-)
create mode 100644 target/mips/internal.h
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 74f6a5b098..2f81e0f950 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1,8 +1,6 @@
#ifndef MIPS_CPU_H
#define MIPS_CPU_H
-//#define DEBUG_OP
-
#define ALIGNED_ONLY
#define CPUArchState struct CPUMIPSState
@@ -15,56 +13,11 @@
struct CPUMIPSState;
-typedef struct r4k_tlb_t r4k_tlb_t;
-struct r4k_tlb_t {
- target_ulong VPN;
- uint32_t PageMask;
- uint16_t ASID;
- unsigned int G:1;
- unsigned int C0:3;
- unsigned int C1:3;
- unsigned int V0:1;
- unsigned int V1:1;
- unsigned int D0:1;
- unsigned int D1:1;
- unsigned int XI0:1;
- unsigned int XI1:1;
- unsigned int RI0:1;
- unsigned int RI1:1;
- unsigned int EHINV:1;
- uint64_t PFN[2];
-};
-
-#if !defined(CONFIG_USER_ONLY)
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
-struct CPUMIPSTLBContext {
- uint32_t nb_tlb;
- uint32_t tlb_in_use;
- int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
- void (*helper_tlbwi)(struct CPUMIPSState *env);
- void (*helper_tlbwr)(struct CPUMIPSState *env);
- void (*helper_tlbp)(struct CPUMIPSState *env);
- void (*helper_tlbr)(struct CPUMIPSState *env);
- void (*helper_tlbinv)(struct CPUMIPSState *env);
- void (*helper_tlbinvf)(struct CPUMIPSState *env);
- union {
- struct {
- r4k_tlb_t tlb[MIPS_TLB_MAX];
- } r4k;
- } mmu;
-};
-#endif
/* MSA Context */
#define MSA_WRLEN (128)
-enum CPUMIPSMSADataFormat {
- DF_BYTE = 0,
- DF_HALF,
- DF_WORD,
- DF_DOUBLE
-};
-
typedef union wr_t wr_t;
union wr_t {
int8_t b[MSA_WRLEN/8];
@@ -682,40 +635,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
#define ENV_OFFSET offsetof(MIPSCPU, env)
-#ifndef CONFIG_USER_ONLY
-extern const struct VMStateDescription vmstate_mips_cpu;
-#endif
-
-void mips_cpu_do_interrupt(CPUState *cpu);
-bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
-void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
- int flags);
-hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
-int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
-int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
- MMUAccessType access_type,
- int mmu_idx, uintptr_t retaddr);
-
-#if !defined(CONFIG_USER_ONLY)
-int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type);
-int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type);
-int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type);
-void r4k_helper_tlbwi(CPUMIPSState *env);
-void r4k_helper_tlbwr(CPUMIPSState *env);
-void r4k_helper_tlbp(CPUMIPSState *env);
-void r4k_helper_tlbr(CPUMIPSState *env);
-void r4k_helper_tlbinv(CPUMIPSState *env);
-void r4k_helper_tlbinvf(CPUMIPSState *env);
-
-void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
- bool is_write, bool is_exec, int unused,
- unsigned size);
-#endif
-
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler cpu_mips_signal_handler
@@ -746,42 +665,6 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
-static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
-{
- return (env->CP0_Status & (1 << CP0St_IE)) &&
- !(env->CP0_Status & (1 << CP0St_EXL)) &&
- !(env->CP0_Status & (1 << CP0St_ERL)) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- /* Note that the TCStatus IXMT field is initialized to zero,
- and only MT capable cores can set it to one. So we don't
- need to check for MT capabilities here. */
- !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
-}
-
-/* Check if there is pending and not masked out interrupt */
-static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
-{
- int32_t pending;
- int32_t status;
- bool r;
-
- pending = env->CP0_Cause & CP0Ca_IP_mask;
- status = env->CP0_Status & CP0Ca_IP_mask;
-
- if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
- /* A MIPS configured with a vectorizing external interrupt controller
- will feed a vector into the Cause pending lines. The core treats
- the status lines as a vector level, not as indiviual masks. */
- r = pending > status;
- } else {
- /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
- treats the pending lines as individual interrupt lines, the status
- lines are individual masks. */
- r = (pending & status) != 0;
- }
- return r;
-}
-
#include "exec/cpu-all.h"
/* Memory access type :
@@ -847,14 +730,13 @@ enum {
#define EXCP_SC 0x100
/*
- * This is an interrnally generated WAKE request line.
+ * This is an internally generated WAKE request line.
* It is driven by the CPU itself. Raised when the MT
* block wants to wake a VPE from an inactive state and
* cleared when VPE goes from active to inactive.
*/
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
-void mips_tcg_init(void);
MIPSCPU *cpu_mips_init(const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
@@ -863,84 +745,18 @@ bool cpu_supports_cps_smp(const char *cpu_model);
bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
-/* TODO QOM'ify CPU reset and remove */
-void cpu_state_reset(CPUMIPSState *s);
-
-/* mips_timer.c */
-uint32_t cpu_mips_get_random (CPUMIPSState *env);
-uint32_t cpu_mips_get_count (CPUMIPSState *env);
-void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
-void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
-void cpu_mips_start_count(CPUMIPSState *env);
-void cpu_mips_stop_count(CPUMIPSState *env);
-
/* mips_int.c */
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* helper.c */
-int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
- int mmu_idx);
-
-/* op_helper.c */
-uint32_t float_class_s(uint32_t arg, float_status *fst);
-uint64_t float_class_d(uint64_t arg, float_status *fst);
-
-#if !defined(CONFIG_USER_ONLY)
-void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
-hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
- int rw);
-#endif
target_ulong exception_resume_pc (CPUMIPSState *env);
-/* op_helper.c */
-extern unsigned int ieee_rm[];
-int ieee_ex_to_mips(int xcpt);
-
-static inline void restore_rounding_mode(CPUMIPSState *env)
-{
- set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
- &env->active_fpu.fp_status);
-}
-
-static inline void restore_flush_mode(CPUMIPSState *env)
-{
- set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
- &env->active_fpu.fp_status);
-}
-
static inline void restore_snan_bit_mode(CPUMIPSState *env)
{
set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
&env->active_fpu.fp_status);
}
-static inline void restore_fp_status(CPUMIPSState *env)
-{
- restore_rounding_mode(env);
- restore_flush_mode(env);
- restore_snan_bit_mode(env);
-}
-
-static inline void restore_msa_fp_status(CPUMIPSState *env)
-{
- float_status *status = &env->active_tc.msa_fp_status;
- int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
- bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
-
- set_float_rounding_mode(ieee_rm[rounding_mode], status);
- set_flush_to_zero(flush_to_zero, status);
- set_flush_inputs_to_zero(flush_to_zero, status);
-}
-
-static inline void restore_pamask(CPUMIPSState *env)
-{
- if (env->hflags & MIPS_HFLAG_ELPA) {
- env->PAMask = (1ULL << env->PABITS) - 1;
- } else {
- env->PAMask = PAMASK_BASE;
- }
-}
-
static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
@@ -950,172 +766,4 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
MIPS_HFLAG_HWRENA_ULR);
}
-static inline int mips_vpe_active(CPUMIPSState *env)
-{
- int active = 1;
-
- /* Check that the VPE is enabled. */
- if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
- active = 0;
- }
- /* Check that the VPE is activated. */
- if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
- active = 0;
- }
-
- /* Now verify that there are active thread contexts in the VPE.
-
- This assumes the CPU model will internally reschedule threads
- if the active one goes to sleep. If there are no threads available
- the active one will be in a sleeping state, and we can turn off
- the entire VPE. */
- if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
- /* TC is not activated. */
- active = 0;
- }
- if (env->active_tc.CP0_TCHalt & 1) {
- /* TC is in halt state. */
- active = 0;
- }
-
- return active;
-}
-
-static inline int mips_vp_active(CPUMIPSState *env)
-{
- CPUState *other_cs = first_cpu;
-
- /* Check if the VP disabled other VPs (which means the VP is enabled) */
- if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
- return 1;
- }
-
- /* Check if the virtual processor is disabled due to a DVP */
- CPU_FOREACH(other_cs) {
- MIPSCPU *other_cpu = MIPS_CPU(other_cs);
- if ((&other_cpu->env != env) &&
- ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
- return 0;
- }
- }
- return 1;
-}
-
-static inline void compute_hflags(CPUMIPSState *env)
-{
- env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
- MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
- MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
- MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
- MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
- if (env->CP0_Status & (1 << CP0St_ERL)) {
- env->hflags |= MIPS_HFLAG_ERL;
- }
- if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
- !(env->CP0_Status & (1 << CP0St_ERL)) &&
- !(env->hflags & MIPS_HFLAG_DM)) {
- env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
- }
-#if defined(TARGET_MIPS64)
- if ((env->insn_flags & ISA_MIPS3) &&
- (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
- (env->CP0_Status & (1 << CP0St_PX)) ||
- (env->CP0_Status & (1 << CP0St_UX)))) {
- env->hflags |= MIPS_HFLAG_64;
- }
-
- if (!(env->insn_flags & ISA_MIPS3)) {
- env->hflags |= MIPS_HFLAG_AWRAP;
- } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
- !(env->CP0_Status & (1 << CP0St_UX))) {
- env->hflags |= MIPS_HFLAG_AWRAP;
- } else if (env->insn_flags & ISA_MIPS64R6) {
- /* Address wrapping for Supervisor and Kernel is specified in R6 */
- if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
- !(env->CP0_Status & (1 << CP0St_SX))) ||
- (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
- !(env->CP0_Status & (1 << CP0St_KX)))) {
- env->hflags |= MIPS_HFLAG_AWRAP;
- }
- }
-#endif
- if (((env->CP0_Status & (1 << CP0St_CU0)) &&
- !(env->insn_flags & ISA_MIPS32R6)) ||
- !(env->hflags & MIPS_HFLAG_KSU)) {
- env->hflags |= MIPS_HFLAG_CP0;
- }
- if (env->CP0_Status & (1 << CP0St_CU1)) {
- env->hflags |= MIPS_HFLAG_FPU;
- }
- if (env->CP0_Status & (1 << CP0St_FR)) {
- env->hflags |= MIPS_HFLAG_F64;
- }
- if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
- (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
- env->hflags |= MIPS_HFLAG_SBRI;
- }
- if (env->insn_flags & ASE_DSPR2) {
- /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
- so enable to access DSPR2 resources. */
- if (env->CP0_Status & (1 << CP0St_MX)) {
- env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
- }
-
- } else if (env->insn_flags & ASE_DSP) {
- /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
- so enable to access DSP resources. */
- if (env->CP0_Status & (1 << CP0St_MX)) {
- env->hflags |= MIPS_HFLAG_DSP;
- }
-
- }
- if (env->insn_flags & ISA_MIPS32R2) {
- if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
- env->hflags |= MIPS_HFLAG_COP1X;
- }
- } else if (env->insn_flags & ISA_MIPS32) {
- if (env->hflags & MIPS_HFLAG_64) {
- env->hflags |= MIPS_HFLAG_COP1X;
- }
- } else if (env->insn_flags & ISA_MIPS4) {
- /* All supported MIPS IV CPUs use the XX (CU3) to enable
- and disable the MIPS IV extensions to the MIPS III ISA.
- Some other MIPS IV CPUs ignore the bit, so the check here
- would be too restrictive for them. */
- if (env->CP0_Status & (1U << CP0St_CU3)) {
- env->hflags |= MIPS_HFLAG_COP1X;
- }
- }
- if (env->insn_flags & ASE_MSA) {
- if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
- env->hflags |= MIPS_HFLAG_MSA;
- }
- }
- if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
- if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
- env->hflags |= MIPS_HFLAG_FRE;
- }
- }
- if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
- if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
- env->hflags |= MIPS_HFLAG_ELPA;
- }
- }
-}
-
-void cpu_mips_tlb_flush(CPUMIPSState *env);
-void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
-void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
-void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
-
-void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
- int error_code, uintptr_t pc);
-
-static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
- uint32_t exception,
- uintptr_t pc)
-{
- do_raise_exception_err(env, exception, 0, pc);
-}
-
#endif /* MIPS_CPU_H */
diff --git a/target/mips/internal.h b/target/mips/internal.h
new file mode 100644
index 0000000000..91c2df4537
--- /dev/null
+++ b/target/mips/internal.h
@@ -0,0 +1,362 @@
+/* mips internal definitions and helpers
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef MIPS_INTERNAL_H
+#define MIPS_INTERNAL_H
+
+enum CPUMIPSMSADataFormat {
+ DF_BYTE = 0,
+ DF_HALF,
+ DF_WORD,
+ DF_DOUBLE
+};
+
+void mips_cpu_do_interrupt(CPUState *cpu);
+bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
+void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
+ int flags);
+hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
+int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
+int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
+void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
+ MMUAccessType access_type,
+ int mmu_idx, uintptr_t retaddr);
+
+#if !defined(CONFIG_USER_ONLY)
+
+typedef struct r4k_tlb_t r4k_tlb_t;
+struct r4k_tlb_t {
+ target_ulong VPN;
+ uint32_t PageMask;
+ uint16_t ASID;
+ unsigned int G:1;
+ unsigned int C0:3;
+ unsigned int C1:3;
+ unsigned int V0:1;
+ unsigned int V1:1;
+ unsigned int D0:1;
+ unsigned int D1:1;
+ unsigned int XI0:1;
+ unsigned int XI1:1;
+ unsigned int RI0:1;
+ unsigned int RI1:1;
+ unsigned int EHINV:1;
+ uint64_t PFN[2];
+};
+
+struct CPUMIPSTLBContext {
+ uint32_t nb_tlb;
+ uint32_t tlb_in_use;
+ int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type);
+ void (*helper_tlbwi)(struct CPUMIPSState *env);
+ void (*helper_tlbwr)(struct CPUMIPSState *env);
+ void (*helper_tlbp)(struct CPUMIPSState *env);
+ void (*helper_tlbr)(struct CPUMIPSState *env);
+ void (*helper_tlbinv)(struct CPUMIPSState *env);
+ void (*helper_tlbinvf)(struct CPUMIPSState *env);
+ union {
+ struct {
+ r4k_tlb_t tlb[MIPS_TLB_MAX];
+ } r4k;
+ } mmu;
+};
+
+int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type);
+int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type);
+int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type);
+void r4k_helper_tlbwi(CPUMIPSState *env);
+void r4k_helper_tlbwr(CPUMIPSState *env);
+void r4k_helper_tlbp(CPUMIPSState *env);
+void r4k_helper_tlbr(CPUMIPSState *env);
+void r4k_helper_tlbinv(CPUMIPSState *env);
+void r4k_helper_tlbinvf(CPUMIPSState *env);
+void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
+
+void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
+ bool is_write, bool is_exec, int unused,
+ unsigned size);
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
+ int rw);
+#endif
+
+#define cpu_signal_handler cpu_mips_signal_handler
+
+#ifndef CONFIG_USER_ONLY
+extern const struct VMStateDescription vmstate_mips_cpu;
+#endif
+
+static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
+{
+ return (env->CP0_Status & (1 << CP0St_IE)) &&
+ !(env->CP0_Status & (1 << CP0St_EXL)) &&
+ !(env->CP0_Status & (1 << CP0St_ERL)) &&
+ !(env->hflags & MIPS_HFLAG_DM) &&
+ /* Note that the TCStatus IXMT field is initialized to zero,
+ and only MT capable cores can set it to one. So we don't
+ need to check for MT capabilities here. */
+ !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
+}
+
+/* Check if there is pending and not masked out interrupt */
+static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
+{
+ int32_t pending;
+ int32_t status;
+ bool r;
+
+ pending = env->CP0_Cause & CP0Ca_IP_mask;
+ status = env->CP0_Status & CP0Ca_IP_mask;
+
+ if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
+ /* A MIPS configured with a vectorizing external interrupt controller
+ will feed a vector into the Cause pending lines. The core treats
+ the status lines as a vector level, not as indiviual masks. */
+ r = pending > status;
+ } else {
+ /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
+ treats the pending lines as individual interrupt lines, the status
+ lines are individual masks. */
+ r = (pending & status) != 0;
+ }
+ return r;
+}
+
+void mips_tcg_init(void);
+
+/* TODO QOM'ify CPU reset and remove */
+void cpu_state_reset(CPUMIPSState *s);
+
+/* cp0_timer.c */
+uint32_t cpu_mips_get_random(CPUMIPSState *env);
+uint32_t cpu_mips_get_count(CPUMIPSState *env);
+void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
+void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
+void cpu_mips_start_count(CPUMIPSState *env);
+void cpu_mips_stop_count(CPUMIPSState *env);
+
+/* helper.c */
+int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
+
+/* op_helper.c */
+uint32_t float_class_s(uint32_t arg, float_status *fst);
+uint64_t float_class_d(uint64_t arg, float_status *fst);
+
+extern unsigned int ieee_rm[];
+int ieee_ex_to_mips(int xcpt);
+
+static inline void restore_rounding_mode(CPUMIPSState *env)
+{
+ set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_flush_mode(CPUMIPSState *env)
+{
+ set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
+ &env->active_fpu.fp_status);
+}
+
+static inline void restore_fp_status(CPUMIPSState *env)
+{
+ restore_rounding_mode(env);
+ restore_flush_mode(env);
+ restore_snan_bit_mode(env);
+}
+
+static inline void restore_msa_fp_status(CPUMIPSState *env)
+{
+ float_status *status = &env->active_tc.msa_fp_status;
+ int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
+ bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
+
+ set_float_rounding_mode(ieee_rm[rounding_mode], status);
+ set_flush_to_zero(flush_to_zero, status);
+ set_flush_inputs_to_zero(flush_to_zero, status);
+}
+
+static inline void restore_pamask(CPUMIPSState *env)
+{
+ if (env->hflags & MIPS_HFLAG_ELPA) {
+ env->PAMask = (1ULL << env->PABITS) - 1;
+ } else {
+ env->PAMask = PAMASK_BASE;
+ }
+}
+
+static inline int mips_vpe_active(CPUMIPSState *env)
+{
+ int active = 1;
+
+ /* Check that the VPE is enabled. */
+ if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
+ active = 0;
+ }
+ /* Check that the VPE is activated. */
+ if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
+ active = 0;
+ }
+
+ /* Now verify that there are active thread contexts in the VPE.
+
+ This assumes the CPU model will internally reschedule threads
+ if the active one goes to sleep. If there are no threads available
+ the active one will be in a sleeping state, and we can turn off
+ the entire VPE. */
+ if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
+ /* TC is not activated. */
+ active = 0;
+ }
+ if (env->active_tc.CP0_TCHalt & 1) {
+ /* TC is in halt state. */
+ active = 0;
+ }
+
+ return active;
+}
+
+static inline int mips_vp_active(CPUMIPSState *env)
+{
+ CPUState *other_cs = first_cpu;
+
+ /* Check if the VP disabled other VPs (which means the VP is enabled) */
+ if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
+ return 1;
+ }
+
+ /* Check if the virtual processor is disabled due to a DVP */
+ CPU_FOREACH(other_cs) {
+ MIPSCPU *other_cpu = MIPS_CPU(other_cs);
+ if ((&other_cpu->env != env) &&
+ ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static inline void compute_hflags(CPUMIPSState *env)
+{
+ env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
+ MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
+ MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
+ MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
+ MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
+ env->hflags |= MIPS_HFLAG_ERL;
+ }
+ if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
+ !(env->CP0_Status & (1 << CP0St_ERL)) &&
+ !(env->hflags & MIPS_HFLAG_DM)) {
+ env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
+ }
+#if defined(TARGET_MIPS64)
+ if ((env->insn_flags & ISA_MIPS3) &&
+ (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
+ (env->CP0_Status & (1 << CP0St_PX)) ||
+ (env->CP0_Status & (1 << CP0St_UX)))) {
+ env->hflags |= MIPS_HFLAG_64;
+ }
+
+ if (!(env->insn_flags & ISA_MIPS3)) {
+ env->hflags |= MIPS_HFLAG_AWRAP;
+ } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
+ !(env->CP0_Status & (1 << CP0St_UX))) {
+ env->hflags |= MIPS_HFLAG_AWRAP;
+ } else if (env->insn_flags & ISA_MIPS64R6) {
+ /* Address wrapping for Supervisor and Kernel is specified in R6 */
+ if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
+ !(env->CP0_Status & (1 << CP0St_SX))) ||
+ (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
+ !(env->CP0_Status & (1 << CP0St_KX)))) {
+ env->hflags |= MIPS_HFLAG_AWRAP;
+ }
+ }
+#endif
+ if (((env->CP0_Status & (1 << CP0St_CU0)) &&
+ !(env->insn_flags & ISA_MIPS32R6)) ||
+ !(env->hflags & MIPS_HFLAG_KSU)) {
+ env->hflags |= MIPS_HFLAG_CP0;
+ }
+ if (env->CP0_Status & (1 << CP0St_CU1)) {
+ env->hflags |= MIPS_HFLAG_FPU;
+ }
+ if (env->CP0_Status & (1 << CP0St_FR)) {
+ env->hflags |= MIPS_HFLAG_F64;
+ }
+ if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
+ (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
+ env->hflags |= MIPS_HFLAG_SBRI;
+ }
+ if (env->insn_flags & ASE_DSPR2) {
+ /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
+ so enable to access DSPR2 resources. */
+ if (env->CP0_Status & (1 << CP0St_MX)) {
+ env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
+ }
+
+ } else if (env->insn_flags & ASE_DSP) {
+ /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
+ so enable to access DSP resources. */
+ if (env->CP0_Status & (1 << CP0St_MX)) {
+ env->hflags |= MIPS_HFLAG_DSP;
+ }
+
+ }
+ if (env->insn_flags & ISA_MIPS32R2) {
+ if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
+ env->hflags |= MIPS_HFLAG_COP1X;
+ }
+ } else if (env->insn_flags & ISA_MIPS32) {
+ if (env->hflags & MIPS_HFLAG_64) {
+ env->hflags |= MIPS_HFLAG_COP1X;
+ }
+ } else if (env->insn_flags & ISA_MIPS4) {
+ /* All supported MIPS IV CPUs use the XX (CU3) to enable
+ and disable the MIPS IV extensions to the MIPS III ISA.
+ Some other MIPS IV CPUs ignore the bit, so the check here
+ would be too restrictive for them. */
+ if (env->CP0_Status & (1U << CP0St_CU3)) {
+ env->hflags |= MIPS_HFLAG_COP1X;
+ }
+ }
+ if (env->insn_flags & ASE_MSA) {
+ if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
+ env->hflags |= MIPS_HFLAG_MSA;
+ }
+ }
+ if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
+ if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
+ env->hflags |= MIPS_HFLAG_FRE;
+ }
+ }
+ if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
+ if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
+ env->hflags |= MIPS_HFLAG_ELPA;
+ }
+ }
+}
+
+void cpu_mips_tlb_flush(CPUMIPSState *env);
+void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
+void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
+void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
+
+void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
+ int error_code, uintptr_t pc);
+
+static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
+ uint32_t exception,
+ uintptr_t pc)
+{
+ do_raise_exception_err(env, exception, 0, pc);
+}
+
+#endif
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
index a9a58c5604..f4716395df 100644
--- a/target/mips/cp0_timer.c
+++ b/target/mips/cp0_timer.c
@@ -24,6 +24,7 @@
#include "hw/mips/cpudevs.h"
#include "qemu/timer.h"
#include "sysemu/kvm.h"
+#include "internal.h"
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1bb66b7a5a..68bf423e9d 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
+#include "internal.h"
#include "kvm_mips.h"
#include "qemu-common.h"
#include "sysemu/kvm.h"
diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
index 7c682289c2..6d1fb70f2c 100644
--- a/target/mips/gdbstub.c
+++ b/target/mips/gdbstub.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
+#include "internal.h"
#include "exec/gdbstub.h"
int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index ca39aca08a..ea076261af 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "internal.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h"
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 3317905e71..e604aa8b12 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -16,6 +16,7 @@
#include "qemu-common.h"
#include "cpu.h"
+#include "internal.h"
#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 898825de3b..20100d5adb 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -1,6 +1,7 @@
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "cpu.h"
+#include "internal.h"
#include "hw/hw.h"
#include "migration/cpu.h"
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 1fdb0d9792..f167a42655 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "internal.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 320f2b0dc4..e537a8bfd8 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "internal.h"
#include "qemu/host-utils.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c78d27294c..f0febaf1b2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23,6 +23,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "internal.h"
#include "disas/disas.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h
2017-08-17 4:30 ` [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h Philippe Mathieu-Daudé
@ 2017-08-17 14:38 ` Igor Mammedov
2017-08-17 15:06 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 24+ messages in thread
From: Igor Mammedov @ 2017-08-17 14:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Hervé Poussineau, Aurelien Jarno, Yongbok Kim, qemu-devel,
Eduardo Habkost, James Hogan, Thomas Huth, Peter Maydell
On Thu, 17 Aug 2017 01:30:56 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> no logical change, only code movement (and fix a comment typo).
while at that fix checkpatch errors or
first fix checkpatch noted issues in cpu.h and then move it in next patch to internal.h
>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.h | 354 +--------------------------------------------
> target/mips/internal.h | 362 +++++++++++++++++++++++++++++++++++++++++++++++
> target/mips/cp0_timer.c | 1 +
> target/mips/cpu.c | 1 +
> target/mips/gdbstub.c | 1 +
> target/mips/helper.c | 1 +
> target/mips/kvm.c | 1 +
> target/mips/machine.c | 1 +
> target/mips/msa_helper.c | 1 +
> target/mips/op_helper.c | 1 +
> target/mips/translate.c | 1 +
> 11 files changed, 372 insertions(+), 353 deletions(-)
> create mode 100644 target/mips/internal.h
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 74f6a5b098..2f81e0f950 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1,8 +1,6 @@
> #ifndef MIPS_CPU_H
> #define MIPS_CPU_H
>
> -//#define DEBUG_OP
> -
> #define ALIGNED_ONLY
>
> #define CPUArchState struct CPUMIPSState
> @@ -15,56 +13,11 @@
>
> struct CPUMIPSState;
>
> -typedef struct r4k_tlb_t r4k_tlb_t;
> -struct r4k_tlb_t {
> - target_ulong VPN;
> - uint32_t PageMask;
> - uint16_t ASID;
> - unsigned int G:1;
> - unsigned int C0:3;
> - unsigned int C1:3;
> - unsigned int V0:1;
> - unsigned int V1:1;
> - unsigned int D0:1;
> - unsigned int D1:1;
> - unsigned int XI0:1;
> - unsigned int XI1:1;
> - unsigned int RI0:1;
> - unsigned int RI1:1;
> - unsigned int EHINV:1;
> - uint64_t PFN[2];
> -};
> -
> -#if !defined(CONFIG_USER_ONLY)
> typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
> -struct CPUMIPSTLBContext {
> - uint32_t nb_tlb;
> - uint32_t tlb_in_use;
> - int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
> - void (*helper_tlbwi)(struct CPUMIPSState *env);
> - void (*helper_tlbwr)(struct CPUMIPSState *env);
> - void (*helper_tlbp)(struct CPUMIPSState *env);
> - void (*helper_tlbr)(struct CPUMIPSState *env);
> - void (*helper_tlbinv)(struct CPUMIPSState *env);
> - void (*helper_tlbinvf)(struct CPUMIPSState *env);
> - union {
> - struct {
> - r4k_tlb_t tlb[MIPS_TLB_MAX];
> - } r4k;
> - } mmu;
> -};
> -#endif
>
> /* MSA Context */
> #define MSA_WRLEN (128)
>
> -enum CPUMIPSMSADataFormat {
> - DF_BYTE = 0,
> - DF_HALF,
> - DF_WORD,
> - DF_DOUBLE
> -};
> -
> typedef union wr_t wr_t;
> union wr_t {
> int8_t b[MSA_WRLEN/8];
> @@ -682,40 +635,6 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
>
> #define ENV_OFFSET offsetof(MIPSCPU, env)
>
> -#ifndef CONFIG_USER_ONLY
> -extern const struct VMStateDescription vmstate_mips_cpu;
> -#endif
> -
> -void mips_cpu_do_interrupt(CPUState *cpu);
> -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
> -void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
> - int flags);
> -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> -int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> -int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> - MMUAccessType access_type,
> - int mmu_idx, uintptr_t retaddr);
> -
> -#if !defined(CONFIG_USER_ONLY)
> -int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> - target_ulong address, int rw, int access_type);
> -int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> - target_ulong address, int rw, int access_type);
> -int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
> - target_ulong address, int rw, int access_type);
> -void r4k_helper_tlbwi(CPUMIPSState *env);
> -void r4k_helper_tlbwr(CPUMIPSState *env);
> -void r4k_helper_tlbp(CPUMIPSState *env);
> -void r4k_helper_tlbr(CPUMIPSState *env);
> -void r4k_helper_tlbinv(CPUMIPSState *env);
> -void r4k_helper_tlbinvf(CPUMIPSState *env);
> -
> -void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
> - bool is_write, bool is_exec, int unused,
> - unsigned size);
> -#endif
> -
> void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
>
> #define cpu_signal_handler cpu_mips_signal_handler
> @@ -746,42 +665,6 @@ static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
> return hflags_mmu_index(env->hflags);
> }
>
> -static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
> -{
> - return (env->CP0_Status & (1 << CP0St_IE)) &&
> - !(env->CP0_Status & (1 << CP0St_EXL)) &&
> - !(env->CP0_Status & (1 << CP0St_ERL)) &&
> - !(env->hflags & MIPS_HFLAG_DM) &&
> - /* Note that the TCStatus IXMT field is initialized to zero,
> - and only MT capable cores can set it to one. So we don't
> - need to check for MT capabilities here. */
> - !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
> -}
> -
> -/* Check if there is pending and not masked out interrupt */
> -static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
> -{
> - int32_t pending;
> - int32_t status;
> - bool r;
> -
> - pending = env->CP0_Cause & CP0Ca_IP_mask;
> - status = env->CP0_Status & CP0Ca_IP_mask;
> -
> - if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
> - /* A MIPS configured with a vectorizing external interrupt controller
> - will feed a vector into the Cause pending lines. The core treats
> - the status lines as a vector level, not as indiviual masks. */
> - r = pending > status;
> - } else {
> - /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
> - treats the pending lines as individual interrupt lines, the status
> - lines are individual masks. */
> - r = (pending & status) != 0;
> - }
> - return r;
> -}
> -
> #include "exec/cpu-all.h"
>
> /* Memory access type :
> @@ -847,14 +730,13 @@ enum {
> #define EXCP_SC 0x100
>
> /*
> - * This is an interrnally generated WAKE request line.
> + * This is an internally generated WAKE request line.
> * It is driven by the CPU itself. Raised when the MT
> * block wants to wake a VPE from an inactive state and
> * cleared when VPE goes from active to inactive.
> */
> #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
>
> -void mips_tcg_init(void);
> MIPSCPU *cpu_mips_init(const char *cpu_model);
> int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
>
> @@ -863,84 +745,18 @@ bool cpu_supports_cps_smp(const char *cpu_model);
> bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
> void cpu_set_exception_base(int vp_index, target_ulong address);
>
> -/* TODO QOM'ify CPU reset and remove */
> -void cpu_state_reset(CPUMIPSState *s);
> -
> -/* mips_timer.c */
> -uint32_t cpu_mips_get_random (CPUMIPSState *env);
> -uint32_t cpu_mips_get_count (CPUMIPSState *env);
> -void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
> -void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
> -void cpu_mips_start_count(CPUMIPSState *env);
> -void cpu_mips_stop_count(CPUMIPSState *env);
> -
> /* mips_int.c */
> void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
>
> /* helper.c */
> -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> - int mmu_idx);
> -
> -/* op_helper.c */
> -uint32_t float_class_s(uint32_t arg, float_status *fst);
> -uint64_t float_class_d(uint64_t arg, float_status *fst);
> -
> -#if !defined(CONFIG_USER_ONLY)
> -void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
> -hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
> - int rw);
> -#endif
> target_ulong exception_resume_pc (CPUMIPSState *env);
>
> -/* op_helper.c */
> -extern unsigned int ieee_rm[];
> -int ieee_ex_to_mips(int xcpt);
> -
> -static inline void restore_rounding_mode(CPUMIPSState *env)
> -{
> - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
> - &env->active_fpu.fp_status);
> -}
> -
> -static inline void restore_flush_mode(CPUMIPSState *env)
> -{
> - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
> - &env->active_fpu.fp_status);
> -}
> -
> static inline void restore_snan_bit_mode(CPUMIPSState *env)
> {
> set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
> &env->active_fpu.fp_status);
> }
>
> -static inline void restore_fp_status(CPUMIPSState *env)
> -{
> - restore_rounding_mode(env);
> - restore_flush_mode(env);
> - restore_snan_bit_mode(env);
> -}
> -
> -static inline void restore_msa_fp_status(CPUMIPSState *env)
> -{
> - float_status *status = &env->active_tc.msa_fp_status;
> - int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
> - bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
> -
> - set_float_rounding_mode(ieee_rm[rounding_mode], status);
> - set_flush_to_zero(flush_to_zero, status);
> - set_flush_inputs_to_zero(flush_to_zero, status);
> -}
> -
> -static inline void restore_pamask(CPUMIPSState *env)
> -{
> - if (env->hflags & MIPS_HFLAG_ELPA) {
> - env->PAMask = (1ULL << env->PABITS) - 1;
> - } else {
> - env->PAMask = PAMASK_BASE;
> - }
> -}
> -
> static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t *flags)
> {
> @@ -950,172 +766,4 @@ static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
> MIPS_HFLAG_HWRENA_ULR);
> }
>
> -static inline int mips_vpe_active(CPUMIPSState *env)
> -{
> - int active = 1;
> -
> - /* Check that the VPE is enabled. */
> - if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
> - active = 0;
> - }
> - /* Check that the VPE is activated. */
> - if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
> - active = 0;
> - }
> -
> - /* Now verify that there are active thread contexts in the VPE.
> -
> - This assumes the CPU model will internally reschedule threads
> - if the active one goes to sleep. If there are no threads available
> - the active one will be in a sleeping state, and we can turn off
> - the entire VPE. */
> - if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
> - /* TC is not activated. */
> - active = 0;
> - }
> - if (env->active_tc.CP0_TCHalt & 1) {
> - /* TC is in halt state. */
> - active = 0;
> - }
> -
> - return active;
> -}
> -
> -static inline int mips_vp_active(CPUMIPSState *env)
> -{
> - CPUState *other_cs = first_cpu;
> -
> - /* Check if the VP disabled other VPs (which means the VP is enabled) */
> - if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
> - return 1;
> - }
> -
> - /* Check if the virtual processor is disabled due to a DVP */
> - CPU_FOREACH(other_cs) {
> - MIPSCPU *other_cpu = MIPS_CPU(other_cs);
> - if ((&other_cpu->env != env) &&
> - ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
> - return 0;
> - }
> - }
> - return 1;
> -}
> -
> -static inline void compute_hflags(CPUMIPSState *env)
> -{
> - env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
> - MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
> - MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
> - MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
> - MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
> - if (env->CP0_Status & (1 << CP0St_ERL)) {
> - env->hflags |= MIPS_HFLAG_ERL;
> - }
> - if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
> - !(env->CP0_Status & (1 << CP0St_ERL)) &&
> - !(env->hflags & MIPS_HFLAG_DM)) {
> - env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
> - }
> -#if defined(TARGET_MIPS64)
> - if ((env->insn_flags & ISA_MIPS3) &&
> - (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
> - (env->CP0_Status & (1 << CP0St_PX)) ||
> - (env->CP0_Status & (1 << CP0St_UX)))) {
> - env->hflags |= MIPS_HFLAG_64;
> - }
> -
> - if (!(env->insn_flags & ISA_MIPS3)) {
> - env->hflags |= MIPS_HFLAG_AWRAP;
> - } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
> - !(env->CP0_Status & (1 << CP0St_UX))) {
> - env->hflags |= MIPS_HFLAG_AWRAP;
> - } else if (env->insn_flags & ISA_MIPS64R6) {
> - /* Address wrapping for Supervisor and Kernel is specified in R6 */
> - if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
> - !(env->CP0_Status & (1 << CP0St_SX))) ||
> - (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
> - !(env->CP0_Status & (1 << CP0St_KX)))) {
> - env->hflags |= MIPS_HFLAG_AWRAP;
> - }
> - }
> -#endif
> - if (((env->CP0_Status & (1 << CP0St_CU0)) &&
> - !(env->insn_flags & ISA_MIPS32R6)) ||
> - !(env->hflags & MIPS_HFLAG_KSU)) {
> - env->hflags |= MIPS_HFLAG_CP0;
> - }
> - if (env->CP0_Status & (1 << CP0St_CU1)) {
> - env->hflags |= MIPS_HFLAG_FPU;
> - }
> - if (env->CP0_Status & (1 << CP0St_FR)) {
> - env->hflags |= MIPS_HFLAG_F64;
> - }
> - if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
> - (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
> - env->hflags |= MIPS_HFLAG_SBRI;
> - }
> - if (env->insn_flags & ASE_DSPR2) {
> - /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
> - so enable to access DSPR2 resources. */
> - if (env->CP0_Status & (1 << CP0St_MX)) {
> - env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
> - }
> -
> - } else if (env->insn_flags & ASE_DSP) {
> - /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
> - so enable to access DSP resources. */
> - if (env->CP0_Status & (1 << CP0St_MX)) {
> - env->hflags |= MIPS_HFLAG_DSP;
> - }
> -
> - }
> - if (env->insn_flags & ISA_MIPS32R2) {
> - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
> - env->hflags |= MIPS_HFLAG_COP1X;
> - }
> - } else if (env->insn_flags & ISA_MIPS32) {
> - if (env->hflags & MIPS_HFLAG_64) {
> - env->hflags |= MIPS_HFLAG_COP1X;
> - }
> - } else if (env->insn_flags & ISA_MIPS4) {
> - /* All supported MIPS IV CPUs use the XX (CU3) to enable
> - and disable the MIPS IV extensions to the MIPS III ISA.
> - Some other MIPS IV CPUs ignore the bit, so the check here
> - would be too restrictive for them. */
> - if (env->CP0_Status & (1U << CP0St_CU3)) {
> - env->hflags |= MIPS_HFLAG_COP1X;
> - }
> - }
> - if (env->insn_flags & ASE_MSA) {
> - if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
> - env->hflags |= MIPS_HFLAG_MSA;
> - }
> - }
> - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
> - if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
> - env->hflags |= MIPS_HFLAG_FRE;
> - }
> - }
> - if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
> - if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
> - env->hflags |= MIPS_HFLAG_ELPA;
> - }
> - }
> -}
> -
> -void cpu_mips_tlb_flush(CPUMIPSState *env);
> -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
> -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
> -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
> -
> -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
> - int error_code, uintptr_t pc);
> -
> -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
> - uint32_t exception,
> - uintptr_t pc)
> -{
> - do_raise_exception_err(env, exception, 0, pc);
> -}
> -
> #endif /* MIPS_CPU_H */
> diff --git a/target/mips/internal.h b/target/mips/internal.h
> new file mode 100644
> index 0000000000..91c2df4537
> --- /dev/null
> +++ b/target/mips/internal.h
> @@ -0,0 +1,362 @@
> +/* mips internal definitions and helpers
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or later.
> + * See the COPYING file in the top-level directory.
> + */
> +
> +#ifndef MIPS_INTERNAL_H
> +#define MIPS_INTERNAL_H
> +
> +enum CPUMIPSMSADataFormat {
> + DF_BYTE = 0,
> + DF_HALF,
> + DF_WORD,
> + DF_DOUBLE
> +};
> +
> +void mips_cpu_do_interrupt(CPUState *cpu);
> +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
> +void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
> + int flags);
> +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> +int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> +int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
> + MMUAccessType access_type,
> + int mmu_idx, uintptr_t retaddr);
> +
> +#if !defined(CONFIG_USER_ONLY)
> +
> +typedef struct r4k_tlb_t r4k_tlb_t;
> +struct r4k_tlb_t {
> + target_ulong VPN;
> + uint32_t PageMask;
> + uint16_t ASID;
> + unsigned int G:1;
> + unsigned int C0:3;
> + unsigned int C1:3;
> + unsigned int V0:1;
> + unsigned int V1:1;
> + unsigned int D0:1;
> + unsigned int D1:1;
> + unsigned int XI0:1;
> + unsigned int XI1:1;
> + unsigned int RI0:1;
> + unsigned int RI1:1;
> + unsigned int EHINV:1;
> + uint64_t PFN[2];
> +};
> +
> +struct CPUMIPSTLBContext {
> + uint32_t nb_tlb;
> + uint32_t tlb_in_use;
> + int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type);
> + void (*helper_tlbwi)(struct CPUMIPSState *env);
> + void (*helper_tlbwr)(struct CPUMIPSState *env);
> + void (*helper_tlbp)(struct CPUMIPSState *env);
> + void (*helper_tlbr)(struct CPUMIPSState *env);
> + void (*helper_tlbinv)(struct CPUMIPSState *env);
> + void (*helper_tlbinvf)(struct CPUMIPSState *env);
> + union {
> + struct {
> + r4k_tlb_t tlb[MIPS_TLB_MAX];
> + } r4k;
> + } mmu;
> +};
> +
> +int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type);
> +int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type);
> +int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
> + target_ulong address, int rw, int access_type);
> +void r4k_helper_tlbwi(CPUMIPSState *env);
> +void r4k_helper_tlbwr(CPUMIPSState *env);
> +void r4k_helper_tlbp(CPUMIPSState *env);
> +void r4k_helper_tlbr(CPUMIPSState *env);
> +void r4k_helper_tlbinv(CPUMIPSState *env);
> +void r4k_helper_tlbinvf(CPUMIPSState *env);
> +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
> +
> +void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
> + bool is_write, bool is_exec, int unused,
> + unsigned size);
> +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
> + int rw);
> +#endif
> +
> +#define cpu_signal_handler cpu_mips_signal_handler
> +
> +#ifndef CONFIG_USER_ONLY
> +extern const struct VMStateDescription vmstate_mips_cpu;
> +#endif
> +
> +static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
> +{
> + return (env->CP0_Status & (1 << CP0St_IE)) &&
> + !(env->CP0_Status & (1 << CP0St_EXL)) &&
> + !(env->CP0_Status & (1 << CP0St_ERL)) &&
> + !(env->hflags & MIPS_HFLAG_DM) &&
> + /* Note that the TCStatus IXMT field is initialized to zero,
> + and only MT capable cores can set it to one. So we don't
> + need to check for MT capabilities here. */
> + !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
> +}
> +
> +/* Check if there is pending and not masked out interrupt */
> +static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
> +{
> + int32_t pending;
> + int32_t status;
> + bool r;
> +
> + pending = env->CP0_Cause & CP0Ca_IP_mask;
> + status = env->CP0_Status & CP0Ca_IP_mask;
> +
> + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
> + /* A MIPS configured with a vectorizing external interrupt controller
> + will feed a vector into the Cause pending lines. The core treats
> + the status lines as a vector level, not as indiviual masks. */
> + r = pending > status;
> + } else {
> + /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
> + treats the pending lines as individual interrupt lines, the status
> + lines are individual masks. */
> + r = (pending & status) != 0;
> + }
> + return r;
> +}
> +
> +void mips_tcg_init(void);
> +
> +/* TODO QOM'ify CPU reset and remove */
> +void cpu_state_reset(CPUMIPSState *s);
> +
> +/* cp0_timer.c */
> +uint32_t cpu_mips_get_random(CPUMIPSState *env);
> +uint32_t cpu_mips_get_count(CPUMIPSState *env);
> +void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
> +void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
> +void cpu_mips_start_count(CPUMIPSState *env);
> +void cpu_mips_stop_count(CPUMIPSState *env);
> +
> +/* helper.c */
> +int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
> +
> +/* op_helper.c */
> +uint32_t float_class_s(uint32_t arg, float_status *fst);
> +uint64_t float_class_d(uint64_t arg, float_status *fst);
> +
> +extern unsigned int ieee_rm[];
> +int ieee_ex_to_mips(int xcpt);
> +
> +static inline void restore_rounding_mode(CPUMIPSState *env)
> +{
> + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
> + &env->active_fpu.fp_status);
> +}
> +
> +static inline void restore_flush_mode(CPUMIPSState *env)
> +{
> + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
> + &env->active_fpu.fp_status);
> +}
> +
> +static inline void restore_fp_status(CPUMIPSState *env)
> +{
> + restore_rounding_mode(env);
> + restore_flush_mode(env);
> + restore_snan_bit_mode(env);
> +}
> +
> +static inline void restore_msa_fp_status(CPUMIPSState *env)
> +{
> + float_status *status = &env->active_tc.msa_fp_status;
> + int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
> + bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
> +
> + set_float_rounding_mode(ieee_rm[rounding_mode], status);
> + set_flush_to_zero(flush_to_zero, status);
> + set_flush_inputs_to_zero(flush_to_zero, status);
> +}
> +
> +static inline void restore_pamask(CPUMIPSState *env)
> +{
> + if (env->hflags & MIPS_HFLAG_ELPA) {
> + env->PAMask = (1ULL << env->PABITS) - 1;
> + } else {
> + env->PAMask = PAMASK_BASE;
> + }
> +}
> +
> +static inline int mips_vpe_active(CPUMIPSState *env)
> +{
> + int active = 1;
> +
> + /* Check that the VPE is enabled. */
> + if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
> + active = 0;
> + }
> + /* Check that the VPE is activated. */
> + if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
> + active = 0;
> + }
> +
> + /* Now verify that there are active thread contexts in the VPE.
> +
> + This assumes the CPU model will internally reschedule threads
> + if the active one goes to sleep. If there are no threads available
> + the active one will be in a sleeping state, and we can turn off
> + the entire VPE. */
> + if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
> + /* TC is not activated. */
> + active = 0;
> + }
> + if (env->active_tc.CP0_TCHalt & 1) {
> + /* TC is in halt state. */
> + active = 0;
> + }
> +
> + return active;
> +}
> +
> +static inline int mips_vp_active(CPUMIPSState *env)
> +{
> + CPUState *other_cs = first_cpu;
> +
> + /* Check if the VP disabled other VPs (which means the VP is enabled) */
> + if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
> + return 1;
> + }
> +
> + /* Check if the virtual processor is disabled due to a DVP */
> + CPU_FOREACH(other_cs) {
> + MIPSCPU *other_cpu = MIPS_CPU(other_cs);
> + if ((&other_cpu->env != env) &&
> + ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
> + return 0;
> + }
> + }
> + return 1;
> +}
> +
> +static inline void compute_hflags(CPUMIPSState *env)
> +{
> + env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
> + MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
> + MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
> + MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
> + MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
> + if (env->CP0_Status & (1 << CP0St_ERL)) {
> + env->hflags |= MIPS_HFLAG_ERL;
> + }
> + if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
> + !(env->CP0_Status & (1 << CP0St_ERL)) &&
> + !(env->hflags & MIPS_HFLAG_DM)) {
> + env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
> + }
> +#if defined(TARGET_MIPS64)
> + if ((env->insn_flags & ISA_MIPS3) &&
> + (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
> + (env->CP0_Status & (1 << CP0St_PX)) ||
> + (env->CP0_Status & (1 << CP0St_UX)))) {
> + env->hflags |= MIPS_HFLAG_64;
> + }
> +
> + if (!(env->insn_flags & ISA_MIPS3)) {
> + env->hflags |= MIPS_HFLAG_AWRAP;
> + } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
> + !(env->CP0_Status & (1 << CP0St_UX))) {
> + env->hflags |= MIPS_HFLAG_AWRAP;
> + } else if (env->insn_flags & ISA_MIPS64R6) {
> + /* Address wrapping for Supervisor and Kernel is specified in R6 */
> + if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
> + !(env->CP0_Status & (1 << CP0St_SX))) ||
> + (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
> + !(env->CP0_Status & (1 << CP0St_KX)))) {
> + env->hflags |= MIPS_HFLAG_AWRAP;
> + }
> + }
> +#endif
> + if (((env->CP0_Status & (1 << CP0St_CU0)) &&
> + !(env->insn_flags & ISA_MIPS32R6)) ||
> + !(env->hflags & MIPS_HFLAG_KSU)) {
> + env->hflags |= MIPS_HFLAG_CP0;
> + }
> + if (env->CP0_Status & (1 << CP0St_CU1)) {
> + env->hflags |= MIPS_HFLAG_FPU;
> + }
> + if (env->CP0_Status & (1 << CP0St_FR)) {
> + env->hflags |= MIPS_HFLAG_F64;
> + }
> + if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
> + (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
> + env->hflags |= MIPS_HFLAG_SBRI;
> + }
> + if (env->insn_flags & ASE_DSPR2) {
> + /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
> + so enable to access DSPR2 resources. */
> + if (env->CP0_Status & (1 << CP0St_MX)) {
> + env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
> + }
> +
> + } else if (env->insn_flags & ASE_DSP) {
> + /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
> + so enable to access DSP resources. */
> + if (env->CP0_Status & (1 << CP0St_MX)) {
> + env->hflags |= MIPS_HFLAG_DSP;
> + }
> +
> + }
> + if (env->insn_flags & ISA_MIPS32R2) {
> + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
> + env->hflags |= MIPS_HFLAG_COP1X;
> + }
> + } else if (env->insn_flags & ISA_MIPS32) {
> + if (env->hflags & MIPS_HFLAG_64) {
> + env->hflags |= MIPS_HFLAG_COP1X;
> + }
> + } else if (env->insn_flags & ISA_MIPS4) {
> + /* All supported MIPS IV CPUs use the XX (CU3) to enable
> + and disable the MIPS IV extensions to the MIPS III ISA.
> + Some other MIPS IV CPUs ignore the bit, so the check here
> + would be too restrictive for them. */
> + if (env->CP0_Status & (1U << CP0St_CU3)) {
> + env->hflags |= MIPS_HFLAG_COP1X;
> + }
> + }
> + if (env->insn_flags & ASE_MSA) {
> + if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
> + env->hflags |= MIPS_HFLAG_MSA;
> + }
> + }
> + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
> + if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
> + env->hflags |= MIPS_HFLAG_FRE;
> + }
> + }
> + if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
> + if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
> + env->hflags |= MIPS_HFLAG_ELPA;
> + }
> + }
> +}
> +
> +void cpu_mips_tlb_flush(CPUMIPSState *env);
> +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
> +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
> +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
> +
> +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
> + int error_code, uintptr_t pc);
> +
> +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
> + uint32_t exception,
> + uintptr_t pc)
> +{
> + do_raise_exception_err(env, exception, 0, pc);
> +}
> +
> +#endif
> diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
> index a9a58c5604..f4716395df 100644
> --- a/target/mips/cp0_timer.c
> +++ b/target/mips/cp0_timer.c
> @@ -24,6 +24,7 @@
> #include "hw/mips/cpudevs.h"
> #include "qemu/timer.h"
> #include "sysemu/kvm.h"
> +#include "internal.h"
>
> #define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index 1bb66b7a5a..68bf423e9d 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -21,6 +21,7 @@
> #include "qemu/osdep.h"
> #include "qapi/error.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "kvm_mips.h"
> #include "qemu-common.h"
> #include "sysemu/kvm.h"
> diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c
> index 7c682289c2..6d1fb70f2c 100644
> --- a/target/mips/gdbstub.c
> +++ b/target/mips/gdbstub.c
> @@ -20,6 +20,7 @@
> #include "qemu/osdep.h"
> #include "qemu-common.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "exec/gdbstub.h"
>
> int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index ca39aca08a..ea076261af 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -19,6 +19,7 @@
> #include "qemu/osdep.h"
>
> #include "cpu.h"
> +#include "internal.h"
> #include "exec/exec-all.h"
> #include "exec/cpu_ldst.h"
> #include "exec/log.h"
> diff --git a/target/mips/kvm.c b/target/mips/kvm.c
> index 3317905e71..e604aa8b12 100644
> --- a/target/mips/kvm.c
> +++ b/target/mips/kvm.c
> @@ -16,6 +16,7 @@
>
> #include "qemu-common.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "qemu/error-report.h"
> #include "qemu/timer.h"
> #include "sysemu/sysemu.h"
> diff --git a/target/mips/machine.c b/target/mips/machine.c
> index 898825de3b..20100d5adb 100644
> --- a/target/mips/machine.c
> +++ b/target/mips/machine.c
> @@ -1,6 +1,7 @@
> #include "qemu/osdep.h"
> #include "qemu-common.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "hw/hw.h"
> #include "migration/cpu.h"
>
> diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
> index 1fdb0d9792..f167a42655 100644
> --- a/target/mips/msa_helper.c
> +++ b/target/mips/msa_helper.c
> @@ -19,6 +19,7 @@
>
> #include "qemu/osdep.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "exec/exec-all.h"
> #include "exec/helper-proto.h"
>
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 320f2b0dc4..e537a8bfd8 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -19,6 +19,7 @@
> #include "qemu/osdep.h"
> #include "qemu/main-loop.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "qemu/host-utils.h"
> #include "exec/helper-proto.h"
> #include "exec/exec-all.h"
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index c78d27294c..f0febaf1b2 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -23,6 +23,7 @@
>
> #include "qemu/osdep.h"
> #include "cpu.h"
> +#include "internal.h"
> #include "disas/disas.h"
> #include "exec/exec-all.h"
> #include "tcg-op.h"
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h
2017-08-17 14:38 ` Igor Mammedov
@ 2017-08-17 15:06 ` Philippe Mathieu-Daudé
2017-08-18 20:03 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 15:06 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
>> no logical change, only code movement (and fix a comment typo).
> while at that fix checkpatch errors or
> first fix checkpatch noted issues in cpu.h and then move it in next patch to internal.h
ok will do!
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h
2017-08-17 15:06 ` Philippe Mathieu-Daudé
@ 2017-08-18 20:03 ` Philippe Mathieu-Daudé
2017-08-21 8:57 ` Igor Mammedov
0 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-18 20:03 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
Hi Igor,
On 08/17/2017 12:06 PM, Philippe Mathieu-Daudé wrote:
>>> no logical change, only code movement (and fix a comment typo).
>
>> while at that fix checkpatch errors or
>> first fix checkpatch noted issues in cpu.h and then move it in next
>> patch to internal.h
After asking confirmation on IRC these 3 checkpatch issues are false
positives, and I'm not fluent in Perl to fix it, so I'll add a comment
about it in the next series cover.
Regards,
Phil.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h
2017-08-18 20:03 ` Philippe Mathieu-Daudé
@ 2017-08-21 8:57 ` Igor Mammedov
0 siblings, 0 replies; 24+ messages in thread
From: Igor Mammedov @ 2017-08-21 8:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
On Fri, 18 Aug 2017 17:03:03 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Hi Igor,
>
> On 08/17/2017 12:06 PM, Philippe Mathieu-Daudé wrote:
> >>> no logical change, only code movement (and fix a comment typo).
> >
> >> while at that fix checkpatch errors or
> >> first fix checkpatch noted issues in cpu.h and then move it in next
> >> patch to internal.h
>
> After asking confirmation on IRC these 3 checkpatch issues are false
> positives, and I'm not fluent in Perl to fix it, so I'll add a comment
> about it in the next series cover.
fine by me
>
> Regards,
>
> Phil.
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 3/8] mips: split cpu_mips_realize_env() out of cpu_mips_init()
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
2017-08-17 4:30 ` [Qemu-devel] [PATCH 1/8] mips: move hw/mips/cputimer.c to target/mips/ Philippe Mathieu-Daudé
2017-08-17 4:30 ` [Qemu-devel] [PATCH 2/8] mips: introduce internal.h and cleanup cpu.h Philippe Mathieu-Daudé
@ 2017-08-17 4:30 ` Philippe Mathieu-Daudé
2017-08-17 4:30 ` [Qemu-devel] [PATCH 4/8] mips: call cpu_mips_realize_env() from mips_cpu_realizefn() Philippe Mathieu-Daudé
` (6 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:30 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: Philippe Mathieu-Daudé, qemu-devel, Eduardo Habkost,
James Hogan, Thomas Huth, Peter Maydell
so it can be used in mips_cpu_realizefn() in the next commit
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 1 +
target/mips/translate.c | 19 ++++++++++++-------
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 91c2df4537..cf4c9db427 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -132,6 +132,7 @@ void mips_tcg_init(void);
/* TODO QOM'ify CPU reset and remove */
void cpu_state_reset(CPUMIPSState *s);
+void cpu_mips_realize_env(CPUMIPSState *env);
/* cp0_timer.c */
uint32_t cpu_mips_get_random(CPUMIPSState *env);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f0febaf1b2..5fc7979ac5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20512,6 +20512,17 @@ void mips_tcg_init(void)
#include "translate_init.c"
+void cpu_mips_realize_env(CPUMIPSState *env)
+{
+ env->exception_base = (int32_t)0xBFC00000;
+
+#ifndef CONFIG_USER_ONLY
+ mmu_init(env, env->cpu_model);
+#endif
+ fpu_init(env, env->cpu_model);
+ mvp_init(env, env->cpu_model);
+}
+
MIPSCPU *cpu_mips_init(const char *cpu_model)
{
MIPSCPU *cpu;
@@ -20524,13 +20535,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
env = &cpu->env;
env->cpu_model = def;
- env->exception_base = (int32_t)0xBFC00000;
-
-#ifndef CONFIG_USER_ONLY
- mmu_init(env, def);
-#endif
- fpu_init(env, def);
- mvp_init(env, def);
+ cpu_mips_realize_env(env);
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Qemu-devel] [PATCH 4/8] mips: call cpu_mips_realize_env() from mips_cpu_realizefn()
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2017-08-17 4:30 ` [Qemu-devel] [PATCH 3/8] mips: split cpu_mips_realize_env() out of cpu_mips_init() Philippe Mathieu-Daudé
@ 2017-08-17 4:30 ` Philippe Mathieu-Daudé
2017-08-17 4:30 ` [Qemu-devel] [PATCH 5/8] mips: MIPSCPU model subclasses Philippe Mathieu-Daudé
` (5 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:30 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: Philippe Mathieu-Daudé, qemu-devel, Eduardo Habkost,
James Hogan, Thomas Huth, Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.c | 3 +++
target/mips/translate.c | 1 -
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 68bf423e9d..e3ef835599 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -123,6 +123,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
+ MIPSCPU *cpu = MIPS_CPU(dev);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
Error *local_err = NULL;
@@ -132,6 +133,8 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
+ cpu_mips_realize_env(&cpu->env);
+
cpu_reset(cs);
qemu_init_vcpu(cs);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5fc7979ac5..94c38e8755 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20535,7 +20535,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
env = &cpu->env;
env->cpu_model = def;
- cpu_mips_realize_env(env);
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Qemu-devel] [PATCH 5/8] mips: MIPSCPU model subclasses
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2017-08-17 4:30 ` [Qemu-devel] [PATCH 4/8] mips: call cpu_mips_realize_env() from mips_cpu_realizefn() Philippe Mathieu-Daudé
@ 2017-08-17 4:30 ` Philippe Mathieu-Daudé
2017-08-17 4:31 ` [Qemu-devel] [RFC PATCH 6/8] !fixup mips: now than MIPSCPU is QOMified, mark it abstract Philippe Mathieu-Daudé
` (4 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:30 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: qemu-devel, Eduardo Habkost, James Hogan, Thomas Huth,
Peter Maydell, Philippe Mathieu-Daudé
From: Igor Mammedov <imammedo@redhat.com>
Register separate QOM types for each mips cpu model,
so it would be possible to reuse generic CPU creation
routines.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: use internal.h, use void* to hold cpu_def in MIPSCPUClass]
---
target/mips/cpu-qom.h | 1 +
target/mips/internal.h | 59 ++++++++++++++++++++++++++++++++++++++++++++
target/mips/cpu.c | 51 ++++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 13 +++++-----
target/mips/translate_init.c | 58 ++-----------------------------------------
5 files changed, 119 insertions(+), 63 deletions(-)
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 3f5bf23823..085711d8f9 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -49,6 +49,7 @@ typedef struct MIPSCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+ const void *cpu_def;
} MIPSCPUClass;
typedef struct MIPSCPU MIPSCPU;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index cf4c9db427..45ded3484c 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -7,6 +7,65 @@
#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H
+
+/* MMU types, the first four entries have the same layout as the
+ CP0C0_MT field. */
+enum mips_mmu_types {
+ MMU_TYPE_NONE,
+ MMU_TYPE_R4000,
+ MMU_TYPE_RESERVED,
+ MMU_TYPE_FMT,
+ MMU_TYPE_R3000,
+ MMU_TYPE_R6000,
+ MMU_TYPE_R8000
+};
+
+struct mips_def_t {
+ const char *name;
+ int32_t CP0_PRid;
+ int32_t CP0_Config0;
+ int32_t CP0_Config1;
+ int32_t CP0_Config2;
+ int32_t CP0_Config3;
+ int32_t CP0_Config4;
+ int32_t CP0_Config4_rw_bitmask;
+ int32_t CP0_Config5;
+ int32_t CP0_Config5_rw_bitmask;
+ int32_t CP0_Config6;
+ int32_t CP0_Config7;
+ target_ulong CP0_LLAddr_rw_bitmask;
+ int CP0_LLAddr_shift;
+ int32_t SYNCI_Step;
+ int32_t CCRes;
+ int32_t CP0_Status_rw_bitmask;
+ int32_t CP0_TCStatus_rw_bitmask;
+ int32_t CP0_SRSCtl;
+ int32_t CP1_fcr0;
+ int32_t CP1_fcr31_rw_bitmask;
+ int32_t CP1_fcr31;
+ int32_t MSAIR;
+ int32_t SEGBITS;
+ int32_t PABITS;
+ int32_t CP0_SRSConf0_rw_bitmask;
+ int32_t CP0_SRSConf0;
+ int32_t CP0_SRSConf1_rw_bitmask;
+ int32_t CP0_SRSConf1;
+ int32_t CP0_SRSConf2_rw_bitmask;
+ int32_t CP0_SRSConf2;
+ int32_t CP0_SRSConf3_rw_bitmask;
+ int32_t CP0_SRSConf3;
+ int32_t CP0_SRSConf4_rw_bitmask;
+ int32_t CP0_SRSConf4;
+ int32_t CP0_PageGrain_rw_bitmask;
+ int32_t CP0_PageGrain;
+ target_ulong CP0_EBaseWG_rw_bitmask;
+ int insn_flags;
+ enum mips_mmu_types mmu_type;
+};
+
+extern const struct mips_def_t mips_defs[];
+extern const int mips_defs_number;
+
enum CPUMIPSMSADataFormat {
DF_BYTE = 0,
DF_HALF,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e3ef835599..f99cfbde7e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -146,12 +146,37 @@ static void mips_cpu_initfn(Object *obj)
CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(obj);
CPUMIPSState *env = &cpu->env;
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
cs->env_ptr = env;
if (tcg_enabled()) {
mips_tcg_init();
}
+
+ if (mcc->cpu_def) {
+ env->cpu_model = mcc->cpu_def;
+ }
+}
+
+static char *mips_cpu_type_name(const char *cpu_model)
+{
+ return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model);
+}
+
+static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
+{
+ ObjectClass *oc;
+ char *typename;
+
+ if (cpu_model == NULL) {
+ return NULL;
+ }
+
+ typename = mips_cpu_type_name(cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
+ return oc;
}
static void mips_cpu_class_init(ObjectClass *c, void *data)
@@ -166,6 +191,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
mcc->parent_reset = cc->reset;
cc->reset = mips_cpu_reset;
+ cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
@@ -198,9 +224,34 @@ static const TypeInfo mips_cpu_type_info = {
.class_init = mips_cpu_class_init,
};
+static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data)
+{
+ MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc);
+ mcc->cpu_def = data;
+}
+
+static void mips_register_cpudef_type(const struct mips_def_t *def)
+{
+ char *typename = mips_cpu_type_name(def->name);
+ TypeInfo ti = {
+ .name = typename,
+ .parent = TYPE_MIPS_CPU,
+ .class_init = mips_cpu_cpudef_class_init,
+ .class_data = (void *)def,
+ };
+
+ type_register(&ti);
+ g_free(typename);
+}
+
static void mips_cpu_register_types(void)
{
+ int i;
+
type_register_static(&mips_cpu_type_info);
+ for (i = 0; i < mips_defs_number; i++) {
+ mips_register_cpudef_type(&mips_defs[i]);
+ }
}
type_init(mips_cpu_register_types)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 94c38e8755..f7128bc91d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20525,16 +20525,15 @@ void cpu_mips_realize_env(CPUMIPSState *env)
MIPSCPU *cpu_mips_init(const char *cpu_model)
{
+ ObjectClass *oc;
MIPSCPU *cpu;
- CPUMIPSState *env;
- const mips_def_t *def;
- def = cpu_mips_find_by_name(cpu_model);
- if (!def)
+ oc = cpu_class_by_name(TYPE_MIPS_CPU, cpu_model);
+ if (oc == NULL) {
return NULL;
- cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
- env = &cpu->env;
- env->cpu_model = def;
+ }
+
+ cpu = MIPS_CPU(object_new(object_class_get_name(oc)));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c
index 255d25bacd..8bbded46c4 100644
--- a/target/mips/translate_init.c
+++ b/target/mips/translate_init.c
@@ -51,64 +51,9 @@
#define MIPS_CONFIG5 \
((0 << CP0C5_M))
-/* MMU types, the first four entries have the same layout as the
- CP0C0_MT field. */
-enum mips_mmu_types {
- MMU_TYPE_NONE,
- MMU_TYPE_R4000,
- MMU_TYPE_RESERVED,
- MMU_TYPE_FMT,
- MMU_TYPE_R3000,
- MMU_TYPE_R6000,
- MMU_TYPE_R8000
-};
-
-struct mips_def_t {
- const char *name;
- int32_t CP0_PRid;
- int32_t CP0_Config0;
- int32_t CP0_Config1;
- int32_t CP0_Config2;
- int32_t CP0_Config3;
- int32_t CP0_Config4;
- int32_t CP0_Config4_rw_bitmask;
- int32_t CP0_Config5;
- int32_t CP0_Config5_rw_bitmask;
- int32_t CP0_Config6;
- int32_t CP0_Config7;
- target_ulong CP0_LLAddr_rw_bitmask;
- int CP0_LLAddr_shift;
- int32_t SYNCI_Step;
- int32_t CCRes;
- int32_t CP0_Status_rw_bitmask;
- int32_t CP0_TCStatus_rw_bitmask;
- int32_t CP0_SRSCtl;
- int32_t CP1_fcr0;
- int32_t CP1_fcr31_rw_bitmask;
- int32_t CP1_fcr31;
- int32_t MSAIR;
- int32_t SEGBITS;
- int32_t PABITS;
- int32_t CP0_SRSConf0_rw_bitmask;
- int32_t CP0_SRSConf0;
- int32_t CP0_SRSConf1_rw_bitmask;
- int32_t CP0_SRSConf1;
- int32_t CP0_SRSConf2_rw_bitmask;
- int32_t CP0_SRSConf2;
- int32_t CP0_SRSConf3_rw_bitmask;
- int32_t CP0_SRSConf3;
- int32_t CP0_SRSConf4_rw_bitmask;
- int32_t CP0_SRSConf4;
- int32_t CP0_PageGrain_rw_bitmask;
- int32_t CP0_PageGrain;
- target_ulong CP0_EBaseWG_rw_bitmask;
- int insn_flags;
- enum mips_mmu_types mmu_type;
-};
-
/*****************************************************************************/
/* MIPS CPU definitions */
-static const mips_def_t mips_defs[] =
+const mips_def_t mips_defs[] =
{
{
.name = "4Kc",
@@ -808,6 +753,7 @@ static const mips_def_t mips_defs[] =
#endif
};
+const int mips_defs_number = ARRAY_SIZE(mips_defs);
static const mips_def_t *cpu_mips_find_by_name (const char *name)
{
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Qemu-devel] [RFC PATCH 6/8] !fixup mips: now than MIPSCPU is QOMified, mark it abstract
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2017-08-17 4:30 ` [Qemu-devel] [PATCH 5/8] mips: MIPSCPU model subclasses Philippe Mathieu-Daudé
@ 2017-08-17 4:31 ` Philippe Mathieu-Daudé
2017-08-17 15:17 ` Igor Mammedov
2017-08-17 4:31 ` [Qemu-devel] [PATCH 7/8] mips: replace cpu_mips_init() with cpu_generic_init() Philippe Mathieu-Daudé
` (3 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:31 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: Philippe Mathieu-Daudé, qemu-devel, Eduardo Habkost,
James Hogan, Thomas Huth, Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index f99cfbde7e..84b6f8bf68 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -219,7 +219,7 @@ static const TypeInfo mips_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(MIPSCPU),
.instance_init = mips_cpu_initfn,
- .abstract = false,
+ .abstract = true,
.class_size = sizeof(MIPSCPUClass),
.class_init = mips_cpu_class_init,
};
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [Qemu-devel] [RFC PATCH 6/8] !fixup mips: now than MIPSCPU is QOMified, mark it abstract
2017-08-17 4:31 ` [Qemu-devel] [RFC PATCH 6/8] !fixup mips: now than MIPSCPU is QOMified, mark it abstract Philippe Mathieu-Daudé
@ 2017-08-17 15:17 ` Igor Mammedov
0 siblings, 0 replies; 24+ messages in thread
From: Igor Mammedov @ 2017-08-17 15:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Hervé Poussineau, Aurelien Jarno, Yongbok Kim, Peter Maydell,
Thomas Huth, James Hogan, Eduardo Habkost, qemu-devel
On Thu, 17 Aug 2017 01:31:00 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> target/mips/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
looks good, just squash it into previous patch
>
> diff --git a/target/mips/cpu.c b/target/mips/cpu.c
> index f99cfbde7e..84b6f8bf68 100644
> --- a/target/mips/cpu.c
> +++ b/target/mips/cpu.c
> @@ -219,7 +219,7 @@ static const TypeInfo mips_cpu_type_info = {
> .parent = TYPE_CPU,
> .instance_size = sizeof(MIPSCPU),
> .instance_init = mips_cpu_initfn,
> - .abstract = false,
> + .abstract = true,
> .class_size = sizeof(MIPSCPUClass),
> .class_init = mips_cpu_class_init,
> };
^ permalink raw reply [flat|nested] 24+ messages in thread
* [Qemu-devel] [PATCH 7/8] mips: replace cpu_mips_init() with cpu_generic_init()
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2017-08-17 4:31 ` [Qemu-devel] [RFC PATCH 6/8] !fixup mips: now than MIPSCPU is QOMified, mark it abstract Philippe Mathieu-Daudé
@ 2017-08-17 4:31 ` Philippe Mathieu-Daudé
2017-08-17 4:31 ` [Qemu-devel] [PATCH 8/8] mips: update mips_cpu_list() to use object_class_get_list() Philippe Mathieu-Daudé
` (2 subsequent siblings)
9 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:31 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: qemu-devel, Eduardo Habkost, James Hogan, Thomas Huth,
Peter Maydell, Philippe Mathieu-Daudé
From: Igor Mammedov <imammedo@redhat.com>
now cpu_mips_init() reimplements subset of cpu_generic_init()
tasks, so just drop it and use cpu_generic_init() directly.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: use internal.h instead of cpu.h]
---
target/mips/cpu.h | 3 +--
hw/mips/cps.c | 2 +-
hw/mips/mips_fulong2e.c | 2 +-
hw/mips/mips_jazz.c | 2 +-
hw/mips/mips_malta.c | 2 +-
hw/mips/mips_mipssim.c | 2 +-
hw/mips/mips_r4k.c | 2 +-
target/mips/translate.c | 17 -----------------
8 files changed, 7 insertions(+), 25 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2f81e0f950..66265e4eb6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -737,10 +737,9 @@ enum {
*/
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
-MIPSCPU *cpu_mips_init(const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
-#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
+#define cpu_init(cpu_model) cpu_generic_init(TYPE_MIPS_CPU, cpu_model)
bool cpu_supports_cps_smp(const char *cpu_model);
bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 4ef337d5c4..708899cf92 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -71,7 +71,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
bool itu_present = false;
for (i = 0; i < s->num_vp; i++) {
- cpu = cpu_mips_init(s->cpu_model);
+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, s->cpu_model));
if (cpu == NULL) {
error_setg(errp, "%s: CPU initialization failed", __func__);
return;
diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c
index 3532399a13..5d9462ec35 100644
--- a/hw/mips/mips_fulong2e.c
+++ b/hw/mips/mips_fulong2e.c
@@ -280,7 +280,7 @@ static void mips_fulong2e_init(MachineState *machine)
if (cpu_model == NULL) {
cpu_model = "Loongson-2E";
}
- cpu = cpu_mips_init(cpu_model);
+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c
index df2262a2a8..c1402de1ce 100644
--- a/hw/mips/mips_jazz.c
+++ b/hw/mips/mips_jazz.c
@@ -151,7 +151,7 @@ static void mips_jazz_init(MachineState *machine,
if (cpu_model == NULL) {
cpu_model = "R4000";
}
- cpu = cpu_mips_init(cpu_model);
+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index af678f5784..9ecdc818b1 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -931,7 +931,7 @@ static void create_cpu_without_cps(const char *cpu_model,
int i;
for (i = 0; i < smp_cpus; i++) {
- cpu = cpu_mips_init(cpu_model);
+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c
index 07fc4c2300..1166834f54 100644
--- a/hw/mips/mips_mipssim.c
+++ b/hw/mips/mips_mipssim.c
@@ -163,7 +163,7 @@ mips_mipssim_init(MachineState *machine)
cpu_model = "24Kf";
#endif
}
- cpu = cpu_mips_init(cpu_model);
+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index 2f5ced7409..de212f5c13 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -193,7 +193,7 @@ void mips_r4k_init(MachineState *machine)
cpu_model = "24Kf";
#endif
}
- cpu = cpu_mips_init(cpu_model);
+ cpu = MIPS_CPU(cpu_generic_init(TYPE_MIPS_CPU, cpu_model));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f7128bc91d..d16d879df7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20523,23 +20523,6 @@ void cpu_mips_realize_env(CPUMIPSState *env)
mvp_init(env, env->cpu_model);
}
-MIPSCPU *cpu_mips_init(const char *cpu_model)
-{
- ObjectClass *oc;
- MIPSCPU *cpu;
-
- oc = cpu_class_by_name(TYPE_MIPS_CPU, cpu_model);
- if (oc == NULL) {
- return NULL;
- }
-
- cpu = MIPS_CPU(object_new(object_class_get_name(oc)));
-
- object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
-
- return cpu;
-}
-
bool cpu_supports_cps_smp(const char *cpu_model)
{
const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* [Qemu-devel] [PATCH 8/8] mips: update mips_cpu_list() to use object_class_get_list()
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2017-08-17 4:31 ` [Qemu-devel] [PATCH 7/8] mips: replace cpu_mips_init() with cpu_generic_init() Philippe Mathieu-Daudé
@ 2017-08-17 4:31 ` Philippe Mathieu-Daudé
2017-08-17 4:54 ` [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu no-reply
2017-08-17 15:22 ` Igor Mammedov
9 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 4:31 UTC (permalink / raw)
To: Igor Mammedov, Hervé Poussineau, Aurelien Jarno, Yongbok Kim
Cc: Philippe Mathieu-Daudé, qemu-devel, Eduardo Habkost,
James Hogan, Thomas Huth, Peter Maydell
while here, move it from translate_init.c to helper.c
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/helper.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
target/mips/translate_init.c | 10 ----------
2 files changed, 46 insertions(+), 10 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index ea076261af..8d12b0088a 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -1093,3 +1093,49 @@ void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
cpu_loop_exit_restore(cs, pc);
}
+
+/* Sort alphabetically by type name, except for "any". */
+static gint mips_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ ObjectClass *class_a = (ObjectClass *)a;
+ ObjectClass *class_b = (ObjectClass *)b;
+ const char *name_a, *name_b;
+
+ name_a = object_class_get_name(class_a);
+ name_b = object_class_get_name(class_b);
+ if (strcmp(name_a, "any-" TYPE_MIPS_CPU) == 0) {
+ return 1;
+ } else if (strcmp(name_b, "any-" TYPE_MIPS_CPU) == 0) {
+ return -1;
+ } else {
+ return strcmp(name_a, name_b);
+ }
+}
+
+static void mips_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ ObjectClass *oc = data;
+ CPUListState *s = user_data;
+ const char *typename;
+ char *name;
+
+ typename = object_class_get_name(oc);
+ name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_MIPS_CPU));
+ (*s->cpu_fprintf)(s->file, " %s\n", name);
+ g_free(name);
+}
+
+void mips_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+ CPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
+
+ list = object_class_get_list(TYPE_MIPS_CPU, false);
+ list = g_slist_sort(list, mips_cpu_list_compare);
+ (*cpu_fprintf)(f, "Available CPUs:\n");
+ g_slist_foreach(list, mips_cpu_list_entry, &s);
+ g_slist_free(list);
+}
diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c
index 8bbded46c4..b75f4c9065 100644
--- a/target/mips/translate_init.c
+++ b/target/mips/translate_init.c
@@ -767,16 +767,6 @@ static const mips_def_t *cpu_mips_find_by_name (const char *name)
return NULL;
}
-void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
- (*cpu_fprintf)(f, "MIPS '%s'\n",
- mips_defs[i].name);
- }
-}
-
#ifndef CONFIG_USER_ONLY
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
--
2.14.1
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2017-08-17 4:31 ` [Qemu-devel] [PATCH 8/8] mips: update mips_cpu_list() to use object_class_get_list() Philippe Mathieu-Daudé
@ 2017-08-17 4:54 ` no-reply
2017-08-17 16:34 ` Philippe Mathieu-Daudé
2017-08-17 15:22 ` Igor Mammedov
9 siblings, 1 reply; 24+ messages in thread
From: no-reply @ 2017-08-17 4:54 UTC (permalink / raw)
To: f4bug
Cc: famz, imammedo, hpoussin, aurelien, yongbok.kim, peter.maydell,
thuth, james.hogan, ehabkost, qemu-devel
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20170817043102.6322-1-f4bug@amsat.org
Subject: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
1557a1941b mips: update mips_cpu_list() to use object_class_get_list()
fff05e4786 mips: replace cpu_mips_init() with cpu_generic_init()
78afa559f4 !fixup mips: now than MIPSCPU is QOMified, mark it abstract
ff2926570c mips: MIPSCPU model subclasses
36f62a8a0b mips: call cpu_mips_realize_env() from mips_cpu_realizefn()
825094780c mips: split cpu_mips_realize_env() out of cpu_mips_init()
7339de695e mips: introduce internal.h and cleanup cpu.h
011150634e mips: move hw/mips/cputimer.c to target/mips/
=== OUTPUT BEGIN ===
Checking PATCH 1/8: mips: move hw/mips/cputimer.c to target/mips/...
Checking PATCH 2/8: mips: introduce internal.h and cleanup cpu.h...
ERROR: space prohibited after that '&' (ctx:WxW)
#725: FILE: target/mips/internal.h:230:
+ if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#733: FILE: target/mips/internal.h:238:
+ ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#753: FILE: target/mips/internal.h:258:
+ env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
^
total: 3 errors, 0 warnings, 842 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/8: mips: split cpu_mips_realize_env() out of cpu_mips_init()...
Checking PATCH 4/8: mips: call cpu_mips_realize_env() from mips_cpu_realizefn()...
Checking PATCH 5/8: mips: MIPSCPU model subclasses...
Checking PATCH 6/8: !fixup mips: now than MIPSCPU is QOMified, mark it abstract...
Checking PATCH 7/8: mips: replace cpu_mips_init() with cpu_generic_init()...
Checking PATCH 8/8: mips: update mips_cpu_list() to use object_class_get_list()...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-17 4:54 ` [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu no-reply
@ 2017-08-17 16:34 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-17 16:34 UTC (permalink / raw)
To: famz
Cc: qemu-devel, imammedo, hpoussin, aurelien, yongbok.kim,
peter.maydell, thuth, james.hogan, ehabkost, Eric Blake
On 08/17/2017 01:54 AM, no-reply@patchew.org wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: 20170817043102.6322-1-f4bug@amsat.org
> Subject: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
>
[...]
>
> Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
> Switched to a new branch 'test'
> 1557a1941b mips: update mips_cpu_list() to use object_class_get_list()
> fff05e4786 mips: replace cpu_mips_init() with cpu_generic_init()
> 78afa559f4 !fixup mips: now than MIPSCPU is QOMified, mark it abstract
> ff2926570c mips: MIPSCPU model subclasses
> 36f62a8a0b mips: call cpu_mips_realize_env() from mips_cpu_realizefn()
> 825094780c mips: split cpu_mips_realize_env() out of cpu_mips_init()
> 7339de695e mips: introduce internal.h and cleanup cpu.h
> 011150634e mips: move hw/mips/cputimer.c to target/mips/
>
> === OUTPUT BEGIN ===
> Checking PATCH 1/8: mips: move hw/mips/cputimer.c to target/mips/...
> Checking PATCH 2/8: mips: introduce internal.h and cleanup cpu.h...
> ERROR: space prohibited after that '&' (ctx:WxW)
> #725: FILE: target/mips/internal.h:230:
> + if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
> ^
>
I doubt CHECKPATCH is correct here, removing the space it'd look like
handling pointer address...
> ERROR: space prohibited after that '&' (ctx:WxW)
> #733: FILE: target/mips/internal.h:238:
> + ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
> ^
>
> ERROR: space prohibited after that '&' (ctx:WxW)
> #753: FILE: target/mips/internal.h:258:
> + env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
> ^
>
> total: 3 errors, 0 warnings, 842 lines checked
>
> Your patch has style problems, please review. If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
>
> Checking PATCH 3/8: mips: split cpu_mips_realize_env() out of cpu_mips_init()...
> Checking PATCH 4/8: mips: call cpu_mips_realize_env() from mips_cpu_realizefn()...
> Checking PATCH 5/8: mips: MIPSCPU model subclasses...
> Checking PATCH 6/8: !fixup mips: now than MIPSCPU is QOMified, mark it abstract...
> Checking PATCH 7/8: mips: replace cpu_mips_init() with cpu_generic_init()...
> Checking PATCH 8/8: mips: update mips_cpu_list() to use object_class_get_list()...
> === OUTPUT END ===
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-17 4:30 [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2017-08-17 4:54 ` [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu no-reply
@ 2017-08-17 15:22 ` Igor Mammedov
2017-08-18 20:08 ` Philippe Mathieu-Daudé
9 siblings, 1 reply; 24+ messages in thread
From: Igor Mammedov @ 2017-08-17 15:22 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Hervé Poussineau, Aurelien Jarno, Yongbok Kim, qemu-devel,
Eduardo Habkost, James Hogan, Thomas Huth, Peter Maydell
On Thu, 17 Aug 2017 01:30:54 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Hi,
>
> While working with the mips codebase I had to QOMify it.
>
> I then read Igor's series "complete cpu QOMification" [1] and after some IRC
> chat I suggested Igor to rebase his series on mine to avoid code moving
> forward then back.
>
> Since most of Igor's series is reviewed I'm posting this a week before 2.11.
>
> I'm not sure about the TypeInfo.abstract change so it is RFC.
>
> Also I couldn't test it with KVM.
Tested in TCG mode (boots debian mips/mips64 kernel with different cpu types),
and new CPU leaf types show up on QOM tree as expected (QOMifycation is done as expected)
and '-cpu help' also works as expected,
so with checkpatch issues fixed you may add to patches my
Tested-by: Igor Mammedov <imammedo@redhat.com>
>
> Regards,
>
> Phil.
>
> [1]: http://lists.nongnu.org/archive/html/qemu-devel/2017-07/msg04414.html
>
> Igor Mammedov (2):
> mips: MIPSCPU model subclasses
> mips: replace cpu_mips_init() with cpu_generic_init()
>
> Philippe Mathieu-Daudé (6):
> mips: move hw/mips/cputimer.c to target/mips/
> mips: introduce internal.h and cleanup cpu.h
> mips: split cpu_mips_realize_env() out of cpu_mips_init()
> mips: call cpu_mips_realize_env() from mips_cpu_realizefn()
> mips: now than MIPSCPU is QOMified, mark it abstract
> mips: update mips_cpu_list() to use object_class_get_list()
>
> target/mips/cpu-qom.h | 1 +
> target/mips/cpu.h | 357 +---------------------
> target/mips/internal.h | 422 ++++++++++++++++++++++++++
> hw/mips/cps.c | 2 +-
> hw/mips/mips_fulong2e.c | 2 +-
> hw/mips/mips_jazz.c | 2 +-
> hw/mips/mips_malta.c | 2 +-
> hw/mips/mips_mipssim.c | 2 +-
> hw/mips/mips_r4k.c | 2 +-
> hw/mips/cputimer.c => target/mips/cp0_timer.c | 2 +-
> target/mips/cpu.c | 57 +++-
> target/mips/gdbstub.c | 1 +
> target/mips/helper.c | 47 +++
> target/mips/kvm.c | 1 +
> target/mips/machine.c | 1 +
> target/mips/msa_helper.c | 1 +
> target/mips/op_helper.c | 1 +
> target/mips/translate.c | 23 +-
> target/mips/translate_init.c | 68 +----
> hw/mips/Makefile.objs | 2 +-
> target/mips/Makefile.objs | 2 +-
> 21 files changed, 549 insertions(+), 449 deletions(-)
> create mode 100644 target/mips/internal.h
> rename hw/mips/cputimer.c => target/mips/cp0_timer.c (99%)
>
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-17 15:22 ` Igor Mammedov
@ 2017-08-18 20:08 ` Philippe Mathieu-Daudé
2017-08-21 9:02 ` Igor Mammedov
2017-08-30 13:50 ` Igor Mammedov
0 siblings, 2 replies; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-18 20:08 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
On 08/17/2017 12:22 PM, Igor Mammedov wrote:
> On Thu, 17 Aug 2017 01:30:54 -0300
> Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
[...]
>> Also I couldn't test it with KVM.
> Tested in TCG mode (boots debian mips/mips64 kernel with different cpu types),
> and new CPU leaf types show up on QOM tree as expected (QOMifycation is done as expected)
you mean the "info qom-tree" output?
> and '-cpu help' also works as expected,
> so with checkpatch issues fixed you may add to patches my
>
> Tested-by: Igor Mammedov <imammedo@redhat.com>
ok thanks for the testing!
I'll wait to see if there is some KVM feedback from imgtec folks before
spaming a v2.
>> Igor Mammedov (2):
>> mips: MIPSCPU model subclasses
>> mips: replace cpu_mips_init() with cpu_generic_init()
>>
>> Philippe Mathieu-Daudé (6):
>> mips: move hw/mips/cputimer.c to target/mips/
>> mips: introduce internal.h and cleanup cpu.h
>> mips: split cpu_mips_realize_env() out of cpu_mips_init()
>> mips: call cpu_mips_realize_env() from mips_cpu_realizefn()
>> mips: now than MIPSCPU is QOMified, mark it abstract
>> mips: update mips_cpu_list() to use object_class_get_list()
>>
>> target/mips/cpu-qom.h | 1 +
>> target/mips/cpu.h | 357 +---------------------
>> target/mips/internal.h | 422 ++++++++++++++++++++++++++
>> hw/mips/cps.c | 2 +-
>> hw/mips/mips_fulong2e.c | 2 +-
>> hw/mips/mips_jazz.c | 2 +-
>> hw/mips/mips_malta.c | 2 +-
>> hw/mips/mips_mipssim.c | 2 +-
>> hw/mips/mips_r4k.c | 2 +-
>> hw/mips/cputimer.c => target/mips/cp0_timer.c | 2 +-
>> target/mips/cpu.c | 57 +++-
>> target/mips/gdbstub.c | 1 +
>> target/mips/helper.c | 47 +++
>> target/mips/kvm.c | 1 +
>> target/mips/machine.c | 1 +
>> target/mips/msa_helper.c | 1 +
>> target/mips/op_helper.c | 1 +
>> target/mips/translate.c | 23 +-
>> target/mips/translate_init.c | 68 +----
>> hw/mips/Makefile.objs | 2 +-
>> target/mips/Makefile.objs | 2 +-
>> 21 files changed, 549 insertions(+), 449 deletions(-)
>> create mode 100644 target/mips/internal.h
>> rename hw/mips/cputimer.c => target/mips/cp0_timer.c (99%)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-18 20:08 ` Philippe Mathieu-Daudé
@ 2017-08-21 9:02 ` Igor Mammedov
2017-08-30 13:50 ` Igor Mammedov
1 sibling, 0 replies; 24+ messages in thread
From: Igor Mammedov @ 2017-08-21 9:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
On Fri, 18 Aug 2017 17:08:29 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 08/17/2017 12:22 PM, Igor Mammedov wrote:
> > On Thu, 17 Aug 2017 01:30:54 -0300
> > Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> [...]
> >> Also I couldn't test it with KVM.
> > Tested in TCG mode (boots debian mips/mips64 kernel with different cpu types),
> > and new CPU leaf types show up on QOM tree as expected (QOMifycation is done as expected)
>
> you mean the "info qom-tree" output?
I've used scripts/qmp/qom-* scripts for testing which use QMP,
but QOM tree that both use is the same so there shouldn't be any difference.
>
> > and '-cpu help' also works as expected,
> > so with checkpatch issues fixed you may add to patches my
> >
> > Tested-by: Igor Mammedov <imammedo@redhat.com>
>
> ok thanks for the testing!
>
> I'll wait to see if there is some KVM feedback from imgtec folks before
> spaming a v2.
>
> >> Igor Mammedov (2):
> >> mips: MIPSCPU model subclasses
> >> mips: replace cpu_mips_init() with cpu_generic_init()
> >>
> >> Philippe Mathieu-Daudé (6):
> >> mips: move hw/mips/cputimer.c to target/mips/
> >> mips: introduce internal.h and cleanup cpu.h
> >> mips: split cpu_mips_realize_env() out of cpu_mips_init()
> >> mips: call cpu_mips_realize_env() from mips_cpu_realizefn()
> >> mips: now than MIPSCPU is QOMified, mark it abstract
> >> mips: update mips_cpu_list() to use object_class_get_list()
> >>
> >> target/mips/cpu-qom.h | 1 +
> >> target/mips/cpu.h | 357 +---------------------
> >> target/mips/internal.h | 422 ++++++++++++++++++++++++++
> >> hw/mips/cps.c | 2 +-
> >> hw/mips/mips_fulong2e.c | 2 +-
> >> hw/mips/mips_jazz.c | 2 +-
> >> hw/mips/mips_malta.c | 2 +-
> >> hw/mips/mips_mipssim.c | 2 +-
> >> hw/mips/mips_r4k.c | 2 +-
> >> hw/mips/cputimer.c => target/mips/cp0_timer.c | 2 +-
> >> target/mips/cpu.c | 57 +++-
> >> target/mips/gdbstub.c | 1 +
> >> target/mips/helper.c | 47 +++
> >> target/mips/kvm.c | 1 +
> >> target/mips/machine.c | 1 +
> >> target/mips/msa_helper.c | 1 +
> >> target/mips/op_helper.c | 1 +
> >> target/mips/translate.c | 23 +-
> >> target/mips/translate_init.c | 68 +----
> >> hw/mips/Makefile.objs | 2 +-
> >> target/mips/Makefile.objs | 2 +-
> >> 21 files changed, 549 insertions(+), 449 deletions(-)
> >> create mode 100644 target/mips/internal.h
> >> rename hw/mips/cputimer.c => target/mips/cp0_timer.c (99%)
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-18 20:08 ` Philippe Mathieu-Daudé
2017-08-21 9:02 ` Igor Mammedov
@ 2017-08-30 13:50 ` Igor Mammedov
2017-08-30 14:41 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 24+ messages in thread
From: Igor Mammedov @ 2017-08-30 13:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
On Fri, 18 Aug 2017 17:08:29 -0300
Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> On 08/17/2017 12:22 PM, Igor Mammedov wrote:
> > On Thu, 17 Aug 2017 01:30:54 -0300
> > Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> [...]
> >> Also I couldn't test it with KVM.
> > Tested in TCG mode (boots debian mips/mips64 kernel with different cpu types),
> > and new CPU leaf types show up on QOM tree as expected (QOMifycation is done as expected)
>
> you mean the "info qom-tree" output?
>
> > and '-cpu help' also works as expected,
> > so with checkpatch issues fixed you may add to patches my
> >
> > Tested-by: Igor Mammedov <imammedo@redhat.com>
>
> ok thanks for the testing!
>
> I'll wait to see if there is some KVM feedback from imgtec folks before
> spaming a v2.
Philippe,
Are you going to respin series soon?
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-30 13:50 ` Igor Mammedov
@ 2017-08-30 14:41 ` Philippe Mathieu-Daudé
2017-08-30 18:19 ` James Hogan
0 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-30 14:41 UTC (permalink / raw)
To: Igor Mammedov
Cc: Peter Maydell, Thomas Huth, James Hogan, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
Hi Igor,
On 08/30/2017 10:50 AM, Igor Mammedov wrote:
>> [...]
>>>> Also I couldn't test it with KVM.
[..]
>>
>> I'll wait to see if there is some KVM feedback from imgtec folks before
>> spaming a v2.
>
> Philippe,
>
> Are you going to respin series soon?
I'm waiting 2.11 officially announced open to send it which should be
tomorrow, in the meaning time it is available in my git repository at:
git://github.com/philmd/qemu.git tags/mips-qomify-20170830
Regards,
Phil.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-30 14:41 ` Philippe Mathieu-Daudé
@ 2017-08-30 18:19 ` James Hogan
2017-08-30 19:52 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 24+ messages in thread
From: James Hogan @ 2017-08-30 18:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Igor Mammedov, Peter Maydell, Thomas Huth, Eduardo Habkost,
qemu-devel, Hervé Poussineau, Yongbok Kim, Aurelien Jarno
[-- Attachment #1: Type: text/plain, Size: 774 bytes --]
Hi Philippe,
On Wed, Aug 30, 2017 at 11:41:38AM -0300, Philippe Mathieu-Daudé wrote:
> Hi Igor,
>
> On 08/30/2017 10:50 AM, Igor Mammedov wrote:
> >> [...]
> >>>> Also I couldn't test it with KVM.
> [..]
> >>
> >> I'll wait to see if there is some KVM feedback from imgtec folks before
> >> spaming a v2.
Sorry for the delay,
> >
> > Philippe,
> >
> > Are you going to respin series soon?
>
> I'm waiting 2.11 officially announced open to send it which should be
> tomorrow, in the meaning time it is available in my git repository at:
>
> git://github.com/philmd/qemu.git tags/mips-qomify-20170830
A sanity check of your branch doesn't reveal any obvious regressions
when booting a Malta KVM guest kernel with KVM.
Cheers
James
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-30 18:19 ` James Hogan
@ 2017-08-30 19:52 ` Philippe Mathieu-Daudé
2017-08-30 20:53 ` James Hogan
0 siblings, 1 reply; 24+ messages in thread
From: Philippe Mathieu-Daudé @ 2017-08-30 19:52 UTC (permalink / raw)
To: James Hogan
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, qemu-devel,
Hervé Poussineau, Yongbok Kim, Igor Mammedov, Aurelien Jarno
Hi James,
On 08/30/2017 03:19 PM, James Hogan wrote:
[...]
>> git://github.com/philmd/qemu.git tags/mips-qomify-20170830
>
> A sanity check of your branch doesn't reveal any obvious regressions
> when booting a Malta KVM guest kernel with KVM.
Thank you for your time to test this!
Does that mean I can add your Tested-by: to the series?
Regards,
Phil.
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [Qemu-devel] [PATCH 0/8] QOMify MIPS cpu
2017-08-30 19:52 ` Philippe Mathieu-Daudé
@ 2017-08-30 20:53 ` James Hogan
0 siblings, 0 replies; 24+ messages in thread
From: James Hogan @ 2017-08-30 20:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Thomas Huth, Eduardo Habkost, qemu-devel,
Hervé Poussineau, Yongbok Kim, Igor Mammedov, Aurelien Jarno
On Wed, Aug 30, 2017 at 04:52:04PM -0300, Philippe Mathieu-Daudé wrote:
> Hi James,
>
> On 08/30/2017 03:19 PM, James Hogan wrote:
> [...]
> >> git://github.com/philmd/qemu.git tags/mips-qomify-20170830
> >
> > A sanity check of your branch doesn't reveal any obvious regressions
> > when booting a Malta KVM guest kernel with KVM.
>
> Thank you for your time to test this!
>
> Does that mean I can add your Tested-by: to the series?
Sure,
Cheers
James
^ permalink raw reply [flat|nested] 24+ messages in thread