From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37495) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1diP9T-00043l-B1 for qemu-devel@nongnu.org; Thu, 17 Aug 2017 14:04:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1diP9S-0005LA-5O for qemu-devel@nongnu.org; Thu, 17 Aug 2017 14:04:15 -0400 Received: from mail-wr0-x230.google.com ([2a00:1450:400c:c0c::230]:34014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1diP9R-0005Je-UG for qemu-devel@nongnu.org; Thu, 17 Aug 2017 14:04:14 -0400 Received: by mail-wr0-x230.google.com with SMTP id y96so47730115wrc.1 for ; Thu, 17 Aug 2017 11:04:13 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 17 Aug 2017 19:04:00 +0100 Message-Id: <20170817180404.29334-6-alex.bennee@linaro.org> In-Reply-To: <20170817180404.29334-1-alex.bennee@linaro.org> References: <20170817180404.29334-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [RFC PATCH 5/9] arm/cpu.h: align VFP registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: rth@twiddle.net, cota@braap.org, batuzovk@ispras.ru Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Peter Maydell Signed-off-by: Alex Bennée --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b39d64aa0b..cdd47cb868 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -457,8 +457,8 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; - + float64 regs[64] __attribute__((aligned(16))); + /* VFP system registers */ uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len; -- 2.13.0