From: David Gibson <david@gibson.dropbear.id.au>
To: BALATON Zoltan <balaton@eik.bme.hu>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
Alexander Graf <agraf@suse.de>, Francois Revol <revol@free.fr>
Subject: Re: [Qemu-devel] [PATCH 02/15] ppc4xx: Make MAL emulation more generic
Date: Mon, 21 Aug 2017 20:40:07 +1000 [thread overview]
Message-ID: <20170821104006.GL12356@umbus.fritz.box> (raw)
In-Reply-To: <158c09e2f3e7930786edcc49bcd9b19b9f92bfa5.1503249785.git.balaton@eik.bme.hu>
[-- Attachment #1: Type: text/plain, Size: 9814 bytes --]
On Sun, Aug 20, 2017 at 07:23:05PM +0200, BALATON Zoltan wrote:
> Allow MAL with more RX and TX channels as found in newer versions.
>
> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
I've applied patches 1 & 2 to my ppc-for-2.11 tree.
> ---
> hw/ppc/ppc405_uc.c | 2 +-
> hw/ppc/ppc4xx_devs.c | 171 +++++++++++++++++++-----------------------------
> include/hw/ppc/ppc4xx.h | 3 +-
> 3 files changed, 70 insertions(+), 106 deletions(-)
>
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index 3c74402..03856d5 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -2281,7 +2281,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
> mal_irqs[1] = pic[12];
> mal_irqs[2] = pic[13];
> mal_irqs[3] = pic[14];
> - ppc405_mal_init(env, mal_irqs);
> + ppc4xx_mal_init(env, 4, 2, mal_irqs);
> /* Ethernet */
> /* Uses pic[9], pic[15], pic[17] */
> /* CPU control */
> diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c
> index 8e4f78e..6e1cc09 100644
> --- a/hw/ppc/ppc4xx_devs.c
> +++ b/hw/ppc/ppc4xx_devs.c
> @@ -737,6 +737,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
>
> /*****************************************************************************/
> /* MAL */
> +
> enum {
> MAL0_CFG = 0x180,
> MAL0_ESR = 0x181,
> @@ -750,17 +751,13 @@ enum {
> MAL0_RXEOBISR = 0x192,
> MAL0_RXDEIR = 0x193,
> MAL0_TXCTP0R = 0x1A0,
> - MAL0_TXCTP1R = 0x1A1,
> - MAL0_TXCTP2R = 0x1A2,
> - MAL0_TXCTP3R = 0x1A3,
> MAL0_RXCTP0R = 0x1C0,
> - MAL0_RXCTP1R = 0x1C1,
> MAL0_RCBS0 = 0x1E0,
> MAL0_RCBS1 = 0x1E1,
> };
>
> -typedef struct ppc40x_mal_t ppc40x_mal_t;
> -struct ppc40x_mal_t {
> +typedef struct ppc4xx_mal_t ppc4xx_mal_t;
> +struct ppc4xx_mal_t {
> qemu_irq irqs[4];
> uint32_t cfg;
> uint32_t esr;
> @@ -773,16 +770,32 @@ struct ppc40x_mal_t {
> uint32_t rxcarr;
> uint32_t rxeobisr;
> uint32_t rxdeir;
> - uint32_t txctpr[4];
> - uint32_t rxctpr[2];
> - uint32_t rcbs[2];
> + uint32_t *txctpr;
> + uint32_t *rxctpr;
> + uint32_t *rcbs;
> + uint8_t txcnum;
> + uint8_t rxcnum;
> };
>
> -static void ppc40x_mal_reset(void *opaque);
> +static void ppc4xx_mal_reset(void *opaque)
> +{
> + ppc4xx_mal_t *mal;
> +
> + mal = opaque;
> + mal->cfg = 0x0007C000;
> + mal->esr = 0x00000000;
> + mal->ier = 0x00000000;
> + mal->rxcasr = 0x00000000;
> + mal->rxdeir = 0x00000000;
> + mal->rxeobisr = 0x00000000;
> + mal->txcasr = 0x00000000;
> + mal->txdeir = 0x00000000;
> + mal->txeobisr = 0x00000000;
> +}
>
> static uint32_t dcr_read_mal(void *opaque, int dcrn)
> {
> - ppc40x_mal_t *mal;
> + ppc4xx_mal_t *mal;
> uint32_t ret;
>
> mal = opaque;
> @@ -820,48 +833,32 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn)
> case MAL0_RXDEIR:
> ret = mal->rxdeir;
> break;
> - case MAL0_TXCTP0R:
> - ret = mal->txctpr[0];
> - break;
> - case MAL0_TXCTP1R:
> - ret = mal->txctpr[1];
> - break;
> - case MAL0_TXCTP2R:
> - ret = mal->txctpr[2];
> - break;
> - case MAL0_TXCTP3R:
> - ret = mal->txctpr[3];
> - break;
> - case MAL0_RXCTP0R:
> - ret = mal->rxctpr[0];
> - break;
> - case MAL0_RXCTP1R:
> - ret = mal->rxctpr[1];
> - break;
> - case MAL0_RCBS0:
> - ret = mal->rcbs[0];
> - break;
> - case MAL0_RCBS1:
> - ret = mal->rcbs[1];
> - break;
> default:
> ret = 0;
> break;
> }
> + if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
> + ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
> + }
> + if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
> + ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
> + }
> + if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
> + ret = mal->rcbs[dcrn - MAL0_RCBS0];
> + }
>
> return ret;
> }
>
> static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
> {
> - ppc40x_mal_t *mal;
> - int idx;
> + ppc4xx_mal_t *mal;
>
> mal = opaque;
> switch (dcrn) {
> case MAL0_CFG:
> if (val & 0x80000000) {
> - ppc40x_mal_reset(mal);
> + ppc4xx_mal_reset(mal);
> }
> mal->cfg = val & 0x00FFC087;
> break;
> @@ -900,65 +897,35 @@ static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
> /* Read/clear */
> mal->rxdeir &= ~val;
> break;
> - case MAL0_TXCTP0R:
> - idx = 0;
> - goto update_tx_ptr;
> - case MAL0_TXCTP1R:
> - idx = 1;
> - goto update_tx_ptr;
> - case MAL0_TXCTP2R:
> - idx = 2;
> - goto update_tx_ptr;
> - case MAL0_TXCTP3R:
> - idx = 3;
> - update_tx_ptr:
> - mal->txctpr[idx] = val;
> - break;
> - case MAL0_RXCTP0R:
> - idx = 0;
> - goto update_rx_ptr;
> - case MAL0_RXCTP1R:
> - idx = 1;
> - update_rx_ptr:
> - mal->rxctpr[idx] = val;
> - break;
> - case MAL0_RCBS0:
> - idx = 0;
> - goto update_rx_size;
> - case MAL0_RCBS1:
> - idx = 1;
> - update_rx_size:
> - mal->rcbs[idx] = val & 0x000000FF;
> - break;
> + }
> + if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
> + mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
> + }
> + if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
> + mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
> + }
> + if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
> + mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
> }
> }
>
> -static void ppc40x_mal_reset(void *opaque)
> -{
> - ppc40x_mal_t *mal;
> -
> - mal = opaque;
> - mal->cfg = 0x0007C000;
> - mal->esr = 0x00000000;
> - mal->ier = 0x00000000;
> - mal->rxcasr = 0x00000000;
> - mal->rxdeir = 0x00000000;
> - mal->rxeobisr = 0x00000000;
> - mal->txcasr = 0x00000000;
> - mal->txdeir = 0x00000000;
> - mal->txeobisr = 0x00000000;
> -}
> -
> -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
> +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> + qemu_irq irqs[4])
> {
> - ppc40x_mal_t *mal;
> + ppc4xx_mal_t *mal;
> int i;
>
> - mal = g_malloc0(sizeof(ppc40x_mal_t));
> + assert(txcnum <= 32 && rxcnum <= 32);
> + mal = g_malloc0(sizeof(*mal));
> + mal->txcnum = txcnum;
> + mal->rxcnum = rxcnum;
> + mal->txctpr = g_new0(uint32_t, txcnum);
> + mal->rxctpr = g_new0(uint32_t, rxcnum);
> + mal->rcbs = g_new0(uint32_t, rxcnum);
> for (i = 0; i < 4; i++) {
> mal->irqs[i] = irqs[i];
> }
> - qemu_register_reset(&ppc40x_mal_reset, mal);
> + qemu_register_reset(&ppc4xx_mal_reset, mal);
> ppc_dcr_register(env, MAL0_CFG,
> mal, &dcr_read_mal, &dcr_write_mal);
> ppc_dcr_register(env, MAL0_ESR,
> @@ -981,20 +948,16 @@ void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
> mal, &dcr_read_mal, &dcr_write_mal);
> ppc_dcr_register(env, MAL0_RXDEIR,
> mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXCTP0R,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXCTP1R,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXCTP2R,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_TXCTP3R,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RXCTP0R,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RXCTP1R,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RCBS0,
> - mal, &dcr_read_mal, &dcr_write_mal);
> - ppc_dcr_register(env, MAL0_RCBS1,
> - mal, &dcr_read_mal, &dcr_write_mal);
> + for (i = 0; i < txcnum; i++) {
> + ppc_dcr_register(env, MAL0_TXCTP0R + i,
> + mal, &dcr_read_mal, &dcr_write_mal);
> + }
> + for (i = 0; i < rxcnum; i++) {
> + ppc_dcr_register(env, MAL0_RXCTP0R + i,
> + mal, &dcr_read_mal, &dcr_write_mal);
> + }
> + for (i = 0; i < rxcnum; i++) {
> + ppc_dcr_register(env, MAL0_RCBS0 + i,
> + mal, &dcr_read_mal, &dcr_write_mal);
> + }
> }
> diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h
> index db50cfa..cb0bb55 100644
> --- a/include/hw/ppc/ppc4xx.h
> +++ b/include/hw/ppc/ppc4xx.h
> @@ -53,7 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
> hwaddr *ram_sizes,
> int do_init);
>
> -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]);
> +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum,
> + qemu_irq irqs[4]);
>
> #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2017-08-21 10:40 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-20 17:23 [Qemu-devel] [PATCH 00/15] Sam460ex emulation BALATON Zoltan
2017-08-20 17:23 ` [Qemu-devel] [PATCH 11/15] ppc: Add 460EX embedded CPU BALATON Zoltan
2017-08-23 2:28 ` David Gibson
2017-08-23 9:08 ` BALATON Zoltan
2017-08-23 9:20 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 05/15] ppc4xx: Split off 4xx I2C emulation from ppc405_uc to its own file BALATON Zoltan
2017-08-20 17:23 ` [Qemu-devel] [PATCH 03/15] ohci: Allow sysbus version to be used as a companion BALATON Zoltan
2017-08-21 4:10 ` David Gibson
2017-08-23 13:58 ` Gerd Hoffmann
2017-08-20 17:23 ` [Qemu-devel] [PATCH 07/15] ppc4xx_i2c: Move to hw/i2c BALATON Zoltan
2017-08-21 10:54 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 04/15] ehci: Add ppc4xx-ehci for the USB 2.0 controller in embedded PPC SoCs BALATON Zoltan
2017-08-21 4:18 ` David Gibson
2017-08-23 13:57 ` Gerd Hoffmann
2017-08-20 17:23 ` [Qemu-devel] [PATCH 06/15] ppc4xx_i2c: QOMify BALATON Zoltan
2017-08-21 10:50 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 15/15] ppc: Add aCube Sam460ex board BALATON Zoltan
2017-08-20 22:10 ` Philippe Mathieu-Daudé
2017-08-23 4:16 ` David Gibson
2017-08-23 11:12 ` BALATON Zoltan
2017-08-23 11:43 ` François Revol
2017-08-23 12:47 ` BALATON Zoltan
2017-08-23 13:33 ` [Qemu-devel] [Qemu-ppc] " luigi burdo
2017-08-24 2:54 ` [Qemu-devel] " David Gibson
2017-08-24 2:51 ` David Gibson
2017-08-24 21:43 ` BALATON Zoltan
2017-08-24 23:55 ` David Gibson
2017-08-24 2:44 ` David Gibson
2017-08-24 21:37 ` BALATON Zoltan
2017-08-25 0:15 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 01/15] ppc4xx: Move MAL from ppc405_uc to ppc4xx_devs BALATON Zoltan
2017-08-20 17:23 ` [Qemu-devel] [PATCH 02/15] ppc4xx: Make MAL emulation more generic BALATON Zoltan
2017-08-21 10:40 ` David Gibson [this message]
2017-08-20 17:23 ` [Qemu-devel] [PATCH 14/15] ppc4xx: Add device models found in PPC440 core SoCs BALATON Zoltan
2017-08-23 2:49 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 12/15] ppc4xx: Export ECB and PLB emulation BALATON Zoltan
2017-08-23 2:30 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 10/15] ppc440: Add emulation of plb-pcix controller found in some 440 SoCs BALATON Zoltan
2017-08-20 22:20 ` Philippe Mathieu-Daudé
2017-08-24 22:12 ` BALATON Zoltan
2017-08-23 0:49 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 08/15] ppc4xx_i2c: Implement basic I2C functions BALATON Zoltan
2017-08-20 17:23 ` [Qemu-devel] [PATCH 13/15] ppc4xx: Add more PLB registers BALATON Zoltan
2017-08-20 21:58 ` Philippe Mathieu-Daudé
2017-08-20 22:12 ` BALATON Zoltan
2017-08-23 2:40 ` David Gibson
2017-08-23 2:39 ` David Gibson
2017-08-23 10:16 ` BALATON Zoltan
2017-08-24 2:35 ` David Gibson
2017-08-24 20:28 ` BALATON Zoltan
2017-08-25 5:05 ` David Gibson
2017-08-20 17:23 ` [Qemu-devel] [PATCH 09/15] hw/ide: Emulate SiI3112 SATA controller BALATON Zoltan
2017-08-21 21:14 ` John Snow
2017-08-22 11:08 ` BALATON Zoltan
2017-08-22 19:01 ` John Snow
2017-08-22 20:15 ` BALATON Zoltan
2017-08-22 20:21 ` John Snow
2017-08-22 21:54 ` BALATON Zoltan
2017-08-23 0:52 ` David Gibson
2017-08-23 16:16 ` John Snow
2017-08-27 12:34 ` [Qemu-devel] [Qemu-ppc] [PATCH 00/15] Sam460ex emulation BALATON Zoltan
2017-08-27 16:56 ` [Qemu-devel] Qemu 2.10 rc4 build issue on BE luigi burdo
2017-08-28 9:20 ` [Qemu-devel] [Qemu-ppc] " Thomas Huth
2017-08-28 11:13 ` luigi burdo
2017-08-28 15:56 ` [Qemu-devel] " Eric Blake
2017-08-29 7:34 ` [Qemu-devel] [Qemu-ppc] [PATCH 00/15] Sam460ex emulation David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170821104006.GL12356@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=agraf@suse.de \
--cc=balaton@eik.bme.hu \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=revol@free.fr \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).