From: Pranith Kumar <bobby.prani@gmail.com>
To: alex.bennee@linaro.org, Peter Maydell <peter.maydell@linaro.org>,
"open list:ARM" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: rth@twiddle.net, pbonzini@redhat.com
Subject: [Qemu-devel] [PATCH 1/3] target/arm: Remove stale comment
Date: Sun, 27 Aug 2017 23:53:24 -0400 [thread overview]
Message-ID: <20170828035327.17146-1-bobby.prani@gmail.com> (raw)
Update the comment which is not true since MTTCG.
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target/arm/translate-a64.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..f42b155d7d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2012,10 +2012,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
}
tcg_addr = read_cpu_reg_sp(s, rn, 1);
- /* Note that since TCG is single threaded load-acquire/store-release
- * semantics require no extra if (is_lasr) { ... } handling.
- */
-
if (is_excl) {
if (!is_store) {
s->is_ldex = true;
--
2.13.0
next reply other threads:[~2017-08-28 3:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-28 3:53 Pranith Kumar [this message]
2017-08-28 3:53 ` [Qemu-devel] [RFC PATCH 2/3] cpus-common: Cache allocated work items Pranith Kumar
2017-08-28 17:47 ` Richard Henderson
2017-08-28 21:43 ` Pranith Kumar
2017-08-29 20:38 ` Paolo Bonzini
2017-08-28 19:05 ` Emilio G. Cota
2017-08-28 21:51 ` Pranith Kumar
2017-08-28 3:53 ` [Qemu-devel] [RFC PATCH 3/3] mttcg: Implement implicit ordering semantics Pranith Kumar
2017-08-28 17:57 ` Richard Henderson
2017-08-28 21:41 ` Pranith Kumar
2017-08-28 22:39 ` Richard Henderson
2017-08-28 17:42 ` [Qemu-devel] [PATCH 1/3] target/arm: Remove stale comment Richard Henderson
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