* [Qemu-devel] [PATCH 1/4] tcg/arm: Fully convert tcg_target_op_def
2017-09-14 19:00 [Qemu-devel] [PATCH 0/4] tcg: Fully convert tcg_target_op_def Richard Henderson
@ 2017-09-14 19:00 ` Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 2/4] tcg/ppc: " Richard Henderson
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2017-09-14 19:00 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.inc.c | 186 +++++++++++++++++++++++++++--------------------
1 file changed, 107 insertions(+), 79 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 14599a8685..98a12535a5 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -2060,91 +2060,119 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef arm_op_defs[] = {
- { INDEX_op_exit_tb, { } },
- { INDEX_op_goto_tb, { } },
- { INDEX_op_br, { } },
- { INDEX_op_goto_ptr, { "r" } },
-
- { INDEX_op_ld8u_i32, { "r", "r" } },
- { INDEX_op_ld8s_i32, { "r", "r" } },
- { INDEX_op_ld16u_i32, { "r", "r" } },
- { INDEX_op_ld16s_i32, { "r", "r" } },
- { INDEX_op_ld_i32, { "r", "r" } },
- { INDEX_op_st8_i32, { "r", "r" } },
- { INDEX_op_st16_i32, { "r", "r" } },
- { INDEX_op_st_i32, { "r", "r" } },
-
- /* TODO: "r", "r", "ri" */
- { INDEX_op_add_i32, { "r", "r", "rIN" } },
- { INDEX_op_sub_i32, { "r", "rI", "rIN" } },
- { INDEX_op_mul_i32, { "r", "r", "r" } },
- { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
- { INDEX_op_muls2_i32, { "r", "r", "r", "r" } },
- { INDEX_op_and_i32, { "r", "r", "rIK" } },
- { INDEX_op_andc_i32, { "r", "r", "rIK" } },
- { INDEX_op_or_i32, { "r", "r", "rI" } },
- { INDEX_op_xor_i32, { "r", "r", "rI" } },
- { INDEX_op_neg_i32, { "r", "r" } },
- { INDEX_op_not_i32, { "r", "r" } },
-
- { INDEX_op_shl_i32, { "r", "r", "ri" } },
- { INDEX_op_shr_i32, { "r", "r", "ri" } },
- { INDEX_op_sar_i32, { "r", "r", "ri" } },
- { INDEX_op_rotl_i32, { "r", "r", "ri" } },
- { INDEX_op_rotr_i32, { "r", "r", "ri" } },
- { INDEX_op_clz_i32, { "r", "r", "rIK" } },
- { INDEX_op_ctz_i32, { "r", "r", "rIK" } },
-
- { INDEX_op_brcond_i32, { "r", "rIN" } },
- { INDEX_op_setcond_i32, { "r", "r", "rIN" } },
- { INDEX_op_movcond_i32, { "r", "r", "rIN", "rIK", "0" } },
-
- { INDEX_op_add2_i32, { "r", "r", "r", "r", "rIN", "rIK" } },
- { INDEX_op_sub2_i32, { "r", "r", "rI", "rI", "rIN", "rIK" } },
- { INDEX_op_brcond2_i32, { "r", "r", "rIN", "rIN" } },
- { INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } },
-
-#if TARGET_LONG_BITS == 32
- { INDEX_op_qemu_ld_i32, { "r", "l" } },
- { INDEX_op_qemu_ld_i64, { "r", "r", "l" } },
- { INDEX_op_qemu_st_i32, { "s", "s" } },
- { INDEX_op_qemu_st_i64, { "s", "s", "s" } },
-#else
- { INDEX_op_qemu_ld_i32, { "r", "l", "l" } },
- { INDEX_op_qemu_ld_i64, { "r", "r", "l", "l" } },
- { INDEX_op_qemu_st_i32, { "s", "s", "s" } },
- { INDEX_op_qemu_st_i64, { "s", "s", "s", "s" } },
-#endif
-
- { INDEX_op_bswap16_i32, { "r", "r" } },
- { INDEX_op_bswap32_i32, { "r", "r" } },
-
- { INDEX_op_ext8s_i32, { "r", "r" } },
- { INDEX_op_ext16s_i32, { "r", "r" } },
- { INDEX_op_ext16u_i32, { "r", "r" } },
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
+ static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
+ static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
+ static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
+ static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_r_rIN
+ = { .args_ct_str = { "r", "r", "rIN" } };
+ static const TCGTargetOpDef r_r_rIK
+ = { .args_ct_str = { "r", "r", "rIK" } };
+ static const TCGTargetOpDef r_r_r_r
+ = { .args_ct_str = { "r", "r", "r", "r" } };
+ static const TCGTargetOpDef r_r_l_l
+ = { .args_ct_str = { "r", "r", "l", "l" } };
+ static const TCGTargetOpDef s_s_s_s
+ = { .args_ct_str = { "s", "s", "s", "s" } };
+ static const TCGTargetOpDef br
+ = { .args_ct_str = { "r", "rIN" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
+ static const TCGTargetOpDef sub2
+ = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
+ static const TCGTargetOpDef br2
+ = { .args_ct_str = { "r", "r", "rIN", "rIN" } };
+ static const TCGTargetOpDef setc2
+ = { .args_ct_str = { "r", "r", "r", "rIN", "rIN" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
- { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
- { INDEX_op_extract_i32, { "r", "r" } },
- { INDEX_op_sextract_i32, { "r", "r" } },
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_sextract_i32:
+ return &r_r;
- { INDEX_op_div_i32, { "r", "r", "r" } },
- { INDEX_op_divu_i32, { "r", "r", "r" } },
+ case INDEX_op_add_i32:
+ case INDEX_op_sub_i32:
+ case INDEX_op_setcond_i32:
+ return &r_r_rIN;
+ case INDEX_op_and_i32:
+ case INDEX_op_andc_i32:
+ case INDEX_op_clz_i32:
+ case INDEX_op_ctz_i32:
+ return &r_r_rIK;
+ case INDEX_op_mul_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ return &r_r_r;
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_muls2_i32:
+ return &r_r_r_r;
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ return &r_r_rI;
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotr_i32:
+ return &r_r_ri;
- { INDEX_op_mb, { } },
- { -1 },
-};
+ case INDEX_op_brcond_i32:
+ return &br;
+ case INDEX_op_deposit_i32:
+ return &dep;
+ case INDEX_op_movcond_i32:
+ return &movc;
+ case INDEX_op_add2_i32:
+ return &add2;
+ case INDEX_op_sub2_i32:
+ return &sub2;
+ case INDEX_op_brcond2_i32:
+ return &br2;
+ case INDEX_op_setcond2_i32:
+ return &setc2;
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- int i, n = ARRAY_SIZE(arm_op_defs);
+ case INDEX_op_qemu_ld_i32:
+ return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
+ case INDEX_op_qemu_ld_i64:
+ return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
+ case INDEX_op_qemu_st_i32:
+ return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
+ case INDEX_op_qemu_st_i64:
+ return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
- for (i = 0; i < n; ++i) {
- if (arm_op_defs[i].op == op) {
- return &arm_op_defs[i];
- }
+ default:
+ return NULL;
}
- return NULL;
}
static void tcg_target_init(TCGContext *s)
--
2.13.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH 2/4] tcg/ppc: Fully convert tcg_target_op_def
2017-09-14 19:00 [Qemu-devel] [PATCH 0/4] tcg: Fully convert tcg_target_op_def Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 1/4] tcg/arm: " Richard Henderson
@ 2017-09-14 19:00 ` Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 3/4] tcg/sparc: " Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 4/4] tcg/mips: " Richard Henderson
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2017-09-14 19:00 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.inc.c | 321 +++++++++++++++++++++++++----------------------
1 file changed, 168 insertions(+), 153 deletions(-)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8ffc7a7205..879885b68b 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -2596,166 +2596,181 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
}
-static const TCGTargetOpDef ppc_op_defs[] = {
- { INDEX_op_exit_tb, { } },
- { INDEX_op_goto_tb, { } },
- { INDEX_op_br, { } },
- { INDEX_op_goto_ptr, { "r" } },
-
- { INDEX_op_ld8u_i32, { "r", "r" } },
- { INDEX_op_ld8s_i32, { "r", "r" } },
- { INDEX_op_ld16u_i32, { "r", "r" } },
- { INDEX_op_ld16s_i32, { "r", "r" } },
- { INDEX_op_ld_i32, { "r", "r" } },
-
- { INDEX_op_st8_i32, { "r", "r" } },
- { INDEX_op_st16_i32, { "r", "r" } },
- { INDEX_op_st_i32, { "r", "r" } },
-
- { INDEX_op_add_i32, { "r", "r", "ri" } },
- { INDEX_op_mul_i32, { "r", "r", "rI" } },
- { INDEX_op_div_i32, { "r", "r", "r" } },
- { INDEX_op_divu_i32, { "r", "r", "r" } },
- { INDEX_op_sub_i32, { "r", "rI", "ri" } },
- { INDEX_op_and_i32, { "r", "r", "ri" } },
- { INDEX_op_or_i32, { "r", "r", "ri" } },
- { INDEX_op_xor_i32, { "r", "r", "ri" } },
- { INDEX_op_andc_i32, { "r", "r", "ri" } },
- { INDEX_op_orc_i32, { "r", "r", "ri" } },
- { INDEX_op_eqv_i32, { "r", "r", "ri" } },
- { INDEX_op_nand_i32, { "r", "r", "r" } },
- { INDEX_op_nor_i32, { "r", "r", "r" } },
- { INDEX_op_clz_i32, { "r", "r", "rZW" } },
- { INDEX_op_ctz_i32, { "r", "r", "rZW" } },
- { INDEX_op_ctpop_i32, { "r", "r" } },
-
- { INDEX_op_shl_i32, { "r", "r", "ri" } },
- { INDEX_op_shr_i32, { "r", "r", "ri" } },
- { INDEX_op_sar_i32, { "r", "r", "ri" } },
- { INDEX_op_rotl_i32, { "r", "r", "ri" } },
- { INDEX_op_rotr_i32, { "r", "r", "ri" } },
-
- { INDEX_op_neg_i32, { "r", "r" } },
- { INDEX_op_not_i32, { "r", "r" } },
- { INDEX_op_ext8s_i32, { "r", "r" } },
- { INDEX_op_ext16s_i32, { "r", "r" } },
- { INDEX_op_bswap16_i32, { "r", "r" } },
- { INDEX_op_bswap32_i32, { "r", "r" } },
-
- { INDEX_op_brcond_i32, { "r", "ri" } },
- { INDEX_op_setcond_i32, { "r", "r", "ri" } },
- { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
-
- { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
- { INDEX_op_extract_i32, { "r", "r" } },
-
- { INDEX_op_muluh_i32, { "r", "r", "r" } },
- { INDEX_op_mulsh_i32, { "r", "r", "r" } },
-
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_ld8u_i64, { "r", "r" } },
- { INDEX_op_ld8s_i64, { "r", "r" } },
- { INDEX_op_ld16u_i64, { "r", "r" } },
- { INDEX_op_ld16s_i64, { "r", "r" } },
- { INDEX_op_ld32u_i64, { "r", "r" } },
- { INDEX_op_ld32s_i64, { "r", "r" } },
- { INDEX_op_ld_i64, { "r", "r" } },
-
- { INDEX_op_st8_i64, { "r", "r" } },
- { INDEX_op_st16_i64, { "r", "r" } },
- { INDEX_op_st32_i64, { "r", "r" } },
- { INDEX_op_st_i64, { "r", "r" } },
-
- { INDEX_op_add_i64, { "r", "r", "rT" } },
- { INDEX_op_sub_i64, { "r", "rI", "rT" } },
- { INDEX_op_and_i64, { "r", "r", "ri" } },
- { INDEX_op_or_i64, { "r", "r", "rU" } },
- { INDEX_op_xor_i64, { "r", "r", "rU" } },
- { INDEX_op_andc_i64, { "r", "r", "ri" } },
- { INDEX_op_orc_i64, { "r", "r", "r" } },
- { INDEX_op_eqv_i64, { "r", "r", "r" } },
- { INDEX_op_nand_i64, { "r", "r", "r" } },
- { INDEX_op_nor_i64, { "r", "r", "r" } },
- { INDEX_op_clz_i64, { "r", "r", "rZW" } },
- { INDEX_op_ctz_i64, { "r", "r", "rZW" } },
- { INDEX_op_ctpop_i64, { "r", "r" } },
-
- { INDEX_op_shl_i64, { "r", "r", "ri" } },
- { INDEX_op_shr_i64, { "r", "r", "ri" } },
- { INDEX_op_sar_i64, { "r", "r", "ri" } },
- { INDEX_op_rotl_i64, { "r", "r", "ri" } },
- { INDEX_op_rotr_i64, { "r", "r", "ri" } },
-
- { INDEX_op_mul_i64, { "r", "r", "rI" } },
- { INDEX_op_div_i64, { "r", "r", "r" } },
- { INDEX_op_divu_i64, { "r", "r", "r" } },
-
- { INDEX_op_neg_i64, { "r", "r" } },
- { INDEX_op_not_i64, { "r", "r" } },
- { INDEX_op_ext8s_i64, { "r", "r" } },
- { INDEX_op_ext16s_i64, { "r", "r" } },
- { INDEX_op_ext32s_i64, { "r", "r" } },
- { INDEX_op_ext_i32_i64, { "r", "r" } },
- { INDEX_op_extu_i32_i64, { "r", "r" } },
- { INDEX_op_bswap16_i64, { "r", "r" } },
- { INDEX_op_bswap32_i64, { "r", "r" } },
- { INDEX_op_bswap64_i64, { "r", "r" } },
-
- { INDEX_op_brcond_i64, { "r", "ri" } },
- { INDEX_op_setcond_i64, { "r", "r", "ri" } },
- { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
-
- { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
- { INDEX_op_extract_i64, { "r", "r" } },
-
- { INDEX_op_mulsh_i64, { "r", "r", "r" } },
- { INDEX_op_muluh_i64, { "r", "r", "r" } },
-#endif
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
+ static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
+ static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
+ static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
+ static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
+ static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
+ static const TCGTargetOpDef r_rI_ri
+ = { .args_ct_str = { "r", "rI", "ri" } };
+ static const TCGTargetOpDef r_rI_rT
+ = { .args_ct_str = { "r", "rI", "rT" } };
+ static const TCGTargetOpDef r_r_rZW
+ = { .args_ct_str = { "r", "r", "rZW" } };
+ static const TCGTargetOpDef L_L_L_L
+ = { .args_ct_str = { "L", "L", "L", "L" } };
+ static const TCGTargetOpDef S_S_S_S
+ = { .args_ct_str = { "S", "S", "S", "S" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef br2
+ = { .args_ct_str = { "r", "r", "ri", "ri" } };
+ static const TCGTargetOpDef setc2
+ = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
+ static const TCGTargetOpDef sub2
+ = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
-#if TCG_TARGET_REG_BITS == 32
- { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
- { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
-#endif
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_ctpop_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ case INDEX_op_ctpop_i64:
+ case INDEX_op_neg_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_extract_i64:
+ return &r_r;
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
- { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
-#else
- { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
- { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
-#endif
+ case INDEX_op_add_i32:
+ case INDEX_op_and_i32:
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_andc_i32:
+ case INDEX_op_orc_i32:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i64:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_setcond_i64:
+ return &r_r_ri;
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ return &r_r_rI;
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nor_i32:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i64:
+ return &r_r_r;
+ case INDEX_op_sub_i32:
+ return &r_rI_ri;
+ case INDEX_op_add_i64:
+ return &r_r_rT;
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i64:
+ return &r_r_rU;
+ case INDEX_op_sub_i64:
+ return &r_rI_rT;
+ case INDEX_op_clz_i32:
+ case INDEX_op_ctz_i32:
+ case INDEX_op_clz_i64:
+ case INDEX_op_ctz_i64:
+ return &r_r_rZW;
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_qemu_ld_i32, { "r", "L" } },
- { INDEX_op_qemu_st_i32, { "S", "S" } },
- { INDEX_op_qemu_ld_i64, { "r", "L" } },
- { INDEX_op_qemu_st_i64, { "S", "S" } },
-#elif TARGET_LONG_BITS == 32
- { INDEX_op_qemu_ld_i32, { "r", "L" } },
- { INDEX_op_qemu_st_i32, { "S", "S" } },
- { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
- { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
-#else
- { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
- { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
- { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
- { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
-#endif
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &r_ri;
- { INDEX_op_mb, { } },
- { -1 },
-};
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ return &movc;
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return &dep;
+ case INDEX_op_brcond2_i32:
+ return &br2;
+ case INDEX_op_setcond2_i32:
+ return &setc2;
+ case INDEX_op_add2_i64:
+ case INDEX_op_add2_i32:
+ return &add2;
+ case INDEX_op_sub2_i64:
+ case INDEX_op_sub2_i32:
+ return &sub2;
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- int i, n = ARRAY_SIZE(ppc_op_defs);
+ case INDEX_op_qemu_ld_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &r_L : &r_L_L);
+ case INDEX_op_qemu_st_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &S_S : &S_S_S);
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &r_L
+ : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &S_S
+ : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
- for (i = 0; i < n; ++i) {
- if (ppc_op_defs[i].op == op) {
- return &ppc_op_defs[i];
- }
+ default:
+ return NULL;
}
- return NULL;
}
static void tcg_target_init(TCGContext *s)
--
2.13.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH 3/4] tcg/sparc: Fully convert tcg_target_op_def
2017-09-14 19:00 [Qemu-devel] [PATCH 0/4] tcg: Fully convert tcg_target_op_def Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 1/4] tcg/arm: " Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 2/4] tcg/ppc: " Richard Henderson
@ 2017-09-14 19:00 ` Richard Henderson
2017-09-14 19:00 ` [Qemu-devel] [PATCH 4/4] tcg/mips: " Richard Henderson
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2017-09-14 19:00 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc/tcg-target.inc.c | 239 ++++++++++++++++++++++++++-------------------
1 file changed, 137 insertions(+), 102 deletions(-)
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
index 1da4debbaf..bc673bd8c6 100644
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.inc.c
@@ -1632,112 +1632,147 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef sparc_op_defs[] = {
- { INDEX_op_exit_tb, { } },
- { INDEX_op_goto_tb, { } },
- { INDEX_op_br, { } },
- { INDEX_op_goto_ptr, { "r" } },
-
- { INDEX_op_ld8u_i32, { "r", "r" } },
- { INDEX_op_ld8s_i32, { "r", "r" } },
- { INDEX_op_ld16u_i32, { "r", "r" } },
- { INDEX_op_ld16s_i32, { "r", "r" } },
- { INDEX_op_ld_i32, { "r", "r" } },
- { INDEX_op_st8_i32, { "rZ", "r" } },
- { INDEX_op_st16_i32, { "rZ", "r" } },
- { INDEX_op_st_i32, { "rZ", "r" } },
-
- { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_mul_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_div_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_divu_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_sub_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_and_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_andc_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_or_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_orc_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_xor_i32, { "r", "rZ", "rJ" } },
-
- { INDEX_op_shl_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_shr_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_sar_i32, { "r", "rZ", "rJ" } },
-
- { INDEX_op_neg_i32, { "r", "rJ" } },
- { INDEX_op_not_i32, { "r", "rJ" } },
-
- { INDEX_op_brcond_i32, { "rZ", "rJ" } },
- { INDEX_op_setcond_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_movcond_i32, { "r", "rZ", "rJ", "rI", "0" } },
-
- { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
- { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
- { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
- { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } },
-
- { INDEX_op_ld8u_i64, { "R", "r" } },
- { INDEX_op_ld8s_i64, { "R", "r" } },
- { INDEX_op_ld16u_i64, { "R", "r" } },
- { INDEX_op_ld16s_i64, { "R", "r" } },
- { INDEX_op_ld32u_i64, { "R", "r" } },
- { INDEX_op_ld32s_i64, { "R", "r" } },
- { INDEX_op_ld_i64, { "R", "r" } },
- { INDEX_op_st8_i64, { "RZ", "r" } },
- { INDEX_op_st16_i64, { "RZ", "r" } },
- { INDEX_op_st32_i64, { "RZ", "r" } },
- { INDEX_op_st_i64, { "RZ", "r" } },
-
- { INDEX_op_add_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_mul_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_div_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_divu_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_sub_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_and_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_andc_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_or_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_orc_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_xor_i64, { "R", "RZ", "RJ" } },
-
- { INDEX_op_shl_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_shr_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_sar_i64, { "R", "RZ", "RJ" } },
-
- { INDEX_op_neg_i64, { "R", "RJ" } },
- { INDEX_op_not_i64, { "R", "RJ" } },
-
- { INDEX_op_ext32s_i64, { "R", "R" } },
- { INDEX_op_ext32u_i64, { "R", "R" } },
- { INDEX_op_ext_i32_i64, { "R", "r" } },
- { INDEX_op_extu_i32_i64, { "R", "r" } },
- { INDEX_op_extrl_i64_i32, { "r", "R" } },
- { INDEX_op_extrh_i64_i32, { "r", "R" } },
-
- { INDEX_op_brcond_i64, { "RZ", "RJ" } },
- { INDEX_op_setcond_i64, { "R", "RZ", "RJ" } },
- { INDEX_op_movcond_i64, { "R", "RZ", "RJ", "RI", "0" } },
-
- { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
- { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } },
- { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } },
-
- { INDEX_op_qemu_ld_i32, { "r", "A" } },
- { INDEX_op_qemu_ld_i64, { "R", "A" } },
- { INDEX_op_qemu_st_i32, { "sZ", "A" } },
- { INDEX_op_qemu_st_i64, { "SZ", "A" } },
-
- { INDEX_op_mb, { } },
- { -1 },
-};
-
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- int i, n = ARRAY_SIZE(sparc_op_defs);
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
+ static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
+ static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
+ static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
+ static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
+ static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
+ static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
+ static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
+ static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
+ static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
+ static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
+ static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
+ static const TCGTargetOpDef r_rZ_rJ
+ = { .args_ct_str = { "r", "rZ", "rJ" } };
+ static const TCGTargetOpDef R_RZ_RJ
+ = { .args_ct_str = { "R", "RZ", "RJ" } };
+ static const TCGTargetOpDef r_r_rZ_rJ
+ = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
+ static const TCGTargetOpDef movc_32
+ = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
+ static const TCGTargetOpDef movc_64
+ = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
+ static const TCGTargetOpDef add2_32
+ = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
+ static const TCGTargetOpDef add2_64
+ = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
- for (i = 0; i < n; ++i) {
- if (sparc_op_defs[i].op == op) {
- return &sparc_op_defs[i];
- }
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_neg_i32:
+ case INDEX_op_not_i32:
+ return &r_r;
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ return &rZ_r;
+
+ case INDEX_op_add_i32:
+ case INDEX_op_mul_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_sub_i32:
+ case INDEX_op_and_i32:
+ case INDEX_op_andc_i32:
+ case INDEX_op_or_i32:
+ case INDEX_op_orc_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_setcond_i32:
+ return &r_rZ_rJ;
+
+ case INDEX_op_brcond_i32:
+ return &rZ_rJ;
+ case INDEX_op_movcond_i32:
+ return &movc_32;
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return &add2_32;
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_muls2_i32:
+ return &r_r_rZ_rJ;
+
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ return &R_r;
+
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &RZ_r;
+
+ case INDEX_op_add_i64:
+ case INDEX_op_mul_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_sub_i64:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i64:
+ case INDEX_op_or_i64:
+ case INDEX_op_orc_i64:
+ case INDEX_op_xor_i64:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_setcond_i64:
+ return &R_RZ_RJ;
+
+ case INDEX_op_neg_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ return &R_R;
+
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ return &r_R;
+
+ case INDEX_op_brcond_i64:
+ return &RZ_RJ;
+ case INDEX_op_movcond_i64:
+ return &movc_64;
+ case INDEX_op_add2_i64:
+ case INDEX_op_sub2_i64:
+ return &add2_64;
+ case INDEX_op_muluh_i64:
+ return &R_R_R;
+
+ case INDEX_op_qemu_ld_i32:
+ return &r_A;
+ case INDEX_op_qemu_ld_i64:
+ return &R_A;
+ case INDEX_op_qemu_st_i32:
+ return &sZ_A;
+ case INDEX_op_qemu_st_i64:
+ return &SZ_A;
+
+ default:
+ return NULL;
}
- return NULL;
}
static void tcg_target_init(TCGContext *s)
--
2.13.5
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Qemu-devel] [PATCH 4/4] tcg/mips: Fully convert tcg_target_op_def
2017-09-14 19:00 [Qemu-devel] [PATCH 0/4] tcg: Fully convert tcg_target_op_def Richard Henderson
` (2 preceding siblings ...)
2017-09-14 19:00 ` [Qemu-devel] [PATCH 3/4] tcg/sparc: " Richard Henderson
@ 2017-09-14 19:00 ` Richard Henderson
3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2017-09-14 19:00 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.inc.c | 324 ++++++++++++++++++++++++----------------------
1 file changed, 170 insertions(+), 154 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 1c09ec7d5b..ce4030602f 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -2163,166 +2163,182 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
-static const TCGTargetOpDef mips_op_defs[] = {
- { INDEX_op_exit_tb, { } },
- { INDEX_op_goto_tb, { } },
- { INDEX_op_br, { } },
- { INDEX_op_goto_ptr, { "r" } },
-
- { INDEX_op_ld8u_i32, { "r", "r" } },
- { INDEX_op_ld8s_i32, { "r", "r" } },
- { INDEX_op_ld16u_i32, { "r", "r" } },
- { INDEX_op_ld16s_i32, { "r", "r" } },
- { INDEX_op_ld_i32, { "r", "r" } },
- { INDEX_op_st8_i32, { "rZ", "r" } },
- { INDEX_op_st16_i32, { "rZ", "r" } },
- { INDEX_op_st_i32, { "rZ", "r" } },
-
- { INDEX_op_add_i32, { "r", "rZ", "rJ" } },
- { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
-#if !use_mips32r6_instructions
- { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } },
- { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } },
-#endif
- { INDEX_op_mulsh_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_muluh_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_div_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_divu_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_rem_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_remu_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_sub_i32, { "r", "rZ", "rN" } },
-
- { INDEX_op_and_i32, { "r", "rZ", "rIK" } },
- { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
- { INDEX_op_not_i32, { "r", "rZ" } },
- { INDEX_op_or_i32, { "r", "rZ", "rIZ" } },
- { INDEX_op_xor_i32, { "r", "rZ", "rIZ" } },
-
- { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
- { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
- { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
- { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
- { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
- { INDEX_op_clz_i32, { "r", "r", "rWZ" } },
-
- { INDEX_op_bswap16_i32, { "r", "r" } },
- { INDEX_op_bswap32_i32, { "r", "r" } },
-
- { INDEX_op_ext8s_i32, { "r", "rZ" } },
- { INDEX_op_ext16s_i32, { "r", "rZ" } },
-
- { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
- { INDEX_op_extract_i32, { "r", "r" } },
-
- { INDEX_op_brcond_i32, { "rZ", "rZ" } },
-#if use_mips32r6_instructions
- { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
-#else
- { INDEX_op_movcond_i32, { "r", "rZ", "rZ", "rZ", "0" } },
-#endif
- { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
+static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
+{
+ static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
+ static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
+ static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
+ static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
+ static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
+ static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
+ static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
+ static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
+ static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
+ static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
+ static const TCGTargetOpDef SZ_SZ_S
+ = { .args_ct_str = { "SZ", "SZ", "S" } };
+ static const TCGTargetOpDef SZ_SZ_S_S
+ = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
+ static const TCGTargetOpDef r_rZ_rN
+ = { .args_ct_str = { "r", "rZ", "rN" } };
+ static const TCGTargetOpDef r_rZ_rZ
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
+ static const TCGTargetOpDef r_r_rIK
+ = { .args_ct_str = { "r", "r", "rIK" } };
+ static const TCGTargetOpDef r_r_rWZ
+ = { .args_ct_str = { "r", "r", "rWZ" } };
+ static const TCGTargetOpDef r_r_r_r
+ = { .args_ct_str = { "r", "r", "r", "r" } };
+ static const TCGTargetOpDef r_r_L_L
+ = { .args_ct_str = { "r", "r", "L", "L" } };
+ static const TCGTargetOpDef dep
+ = { .args_ct_str = { "r", "0", "rZ" } };
+ static const TCGTargetOpDef movc
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
+ static const TCGTargetOpDef movc_r6
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
+ static const TCGTargetOpDef add2
+ = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
+ static const TCGTargetOpDef br2
+ = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
+ static const TCGTargetOpDef setc2
+ = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
+
+ switch (op) {
+ case INDEX_op_goto_ptr:
+ return &r;
-#if TCG_TARGET_REG_BITS == 32
- { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rN", "rN" } },
- { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rN", "rN" } },
- { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rZ", "rZ" } },
- { INDEX_op_brcond2_i32, { "rZ", "rZ", "rZ", "rZ" } },
-#endif
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_not_i32:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_extract_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_not_i64:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_extrl_i64_i32:
+ case INDEX_op_extrh_i64_i32:
+ case INDEX_op_extract_i64:
+ return &r_r;
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_ld8u_i64, { "r", "r" } },
- { INDEX_op_ld8s_i64, { "r", "r" } },
- { INDEX_op_ld16u_i64, { "r", "r" } },
- { INDEX_op_ld16s_i64, { "r", "r" } },
- { INDEX_op_ld32s_i64, { "r", "r" } },
- { INDEX_op_ld32u_i64, { "r", "r" } },
- { INDEX_op_ld_i64, { "r", "r" } },
- { INDEX_op_st8_i64, { "rZ", "r" } },
- { INDEX_op_st16_i64, { "rZ", "r" } },
- { INDEX_op_st32_i64, { "rZ", "r" } },
- { INDEX_op_st_i64, { "rZ", "r" } },
-
- { INDEX_op_add_i64, { "r", "rZ", "rJ" } },
- { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
-#if !use_mips32r6_instructions
- { INDEX_op_muls2_i64, { "r", "r", "rZ", "rZ" } },
- { INDEX_op_mulu2_i64, { "r", "r", "rZ", "rZ" } },
-#endif
- { INDEX_op_mulsh_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_muluh_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_div_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_divu_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_rem_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_remu_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_sub_i64, { "r", "rZ", "rN" } },
-
- { INDEX_op_and_i64, { "r", "rZ", "rIK" } },
- { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
- { INDEX_op_not_i64, { "r", "rZ" } },
- { INDEX_op_or_i64, { "r", "rZ", "rI" } },
- { INDEX_op_xor_i64, { "r", "rZ", "rI" } },
-
- { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
- { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
- { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
- { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
- { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
- { INDEX_op_clz_i64, { "r", "r", "rWZ" } },
-
- { INDEX_op_bswap16_i64, { "r", "r" } },
- { INDEX_op_bswap32_i64, { "r", "r" } },
- { INDEX_op_bswap64_i64, { "r", "r" } },
-
- { INDEX_op_ext8s_i64, { "r", "rZ" } },
- { INDEX_op_ext16s_i64, { "r", "rZ" } },
- { INDEX_op_ext32s_i64, { "r", "rZ" } },
- { INDEX_op_ext32u_i64, { "r", "rZ" } },
- { INDEX_op_ext_i32_i64, { "r", "rZ" } },
- { INDEX_op_extu_i32_i64, { "r", "rZ" } },
- { INDEX_op_extrl_i64_i32, { "r", "rZ" } },
- { INDEX_op_extrh_i64_i32, { "r", "rZ" } },
-
- { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
- { INDEX_op_extract_i64, { "r", "r" } },
-
- { INDEX_op_brcond_i64, { "rZ", "rZ" } },
-#if use_mips32r6_instructions
- { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rZ", "rZ" } },
-#else
- { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rZ", "0" } },
-#endif
- { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
-
- { INDEX_op_qemu_ld_i32, { "r", "LZ" } },
- { INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
- { INDEX_op_qemu_ld_i64, { "r", "LZ" } },
- { INDEX_op_qemu_st_i64, { "SZ", "SZ" } },
-#elif TARGET_LONG_BITS == 32
- { INDEX_op_qemu_ld_i32, { "r", "LZ" } },
- { INDEX_op_qemu_st_i32, { "SZ", "SZ" } },
- { INDEX_op_qemu_ld_i64, { "r", "r", "LZ" } },
- { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ" } },
-#else
- { INDEX_op_qemu_ld_i32, { "r", "LZ", "LZ" } },
- { INDEX_op_qemu_st_i32, { "SZ", "SZ", "SZ" } },
- { INDEX_op_qemu_ld_i64, { "r", "r", "LZ", "LZ" } },
- { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } },
-#endif
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return &rZ_r;
- { INDEX_op_mb, { } },
- { -1 },
-};
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ return &r_r_rJ;
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ return &r_rZ_rN;
+ case INDEX_op_mul_i32:
+ case INDEX_op_mulsh_i32:
+ case INDEX_op_muluh_i32:
+ case INDEX_op_div_i32:
+ case INDEX_op_divu_i32:
+ case INDEX_op_rem_i32:
+ case INDEX_op_remu_i32:
+ case INDEX_op_nor_i32:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_mulsh_i64:
+ case INDEX_op_muluh_i64:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i64:
+ case INDEX_op_nor_i64:
+ case INDEX_op_setcond_i64:
+ return &r_rZ_rZ;
+ case INDEX_op_muls2_i32:
+ case INDEX_op_mulu2_i32:
+ case INDEX_op_muls2_i64:
+ case INDEX_op_mulu2_i64:
+ return &r_r_r_r;
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ return &r_r_rIK;
+ case INDEX_op_or_i32:
+ case INDEX_op_xor_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_xor_i64:
+ return &r_r_rI;
+ case INDEX_op_shl_i32:
+ case INDEX_op_shr_i32:
+ case INDEX_op_sar_i32:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_rotl_i64:
+ return &r_r_ri;
+ case INDEX_op_clz_i32:
+ case INDEX_op_clz_i64:
+ return &r_r_rWZ;
-static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
-{
- int i, n = ARRAY_SIZE(mips_op_defs);
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return &dep;
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return &rZ_rZ;
+ case INDEX_op_movcond_i32:
+ case INDEX_op_movcond_i64:
+ return use_mips32r6_instructions ? &movc_r6 : &movc;
- for (i = 0; i < n; ++i) {
- if (mips_op_defs[i].op == op) {
- return &mips_op_defs[i];
- }
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return &add2;
+ case INDEX_op_setcond2_i32:
+ return &setc2;
+ case INDEX_op_brcond2_i32:
+ return &br2;
+
+ case INDEX_op_qemu_ld_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &r_L : &r_L_L);
+ case INDEX_op_qemu_st_i32:
+ return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
+ ? &SZ_S : &SZ_S_S);
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &r_L
+ : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
+ : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
+
+ default:
+ return NULL;
}
- return NULL;
}
static int tcg_target_callee_save_regs[] = {
--
2.13.5
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