qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: David Gibson <david@gibson.dropbear.id.au>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>,
	Alexey Kardashevskiy <aik@ozlabs.ru>,
	Alexander Graf <agraf@suse.de>
Subject: Re: [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in OS event queue
Date: Wed, 20 Sep 2017 16:34:16 +1000	[thread overview]
Message-ID: <20170920063416.GM5520@umbus.fritz.box> (raw)
In-Reply-To: <2d91c586-ff31-ceb8-bee6-6d4531d1b5c0@kaod.org>

[-- Attachment #1: Type: text/plain, Size: 4655 bytes --]

On Tue, Sep 19, 2017 at 09:36:08PM +0200, Cédric Le Goater wrote:
> On 09/19/2017 09:45 AM, David Gibson wrote:
> > On Mon, Sep 11, 2017 at 07:12:25PM +0200, Cédric Le Goater wrote:
> >> If a triggered event is let through, the Event Queue data defined in
> >> the associated IVE is pushed in the in-memory event queue. The latter
> >> is a circular buffer provided by the OS using the H_INT_SET_QUEUE_CONFIG
> >> hcall, one per target and priority couple. It is composed of Event
> >> Queue entries which are 4 bytes long, the first bit being a
> >> 'generation' bit and the 31 following bits the EQ Data field.
> >>
> >> The EQ Data field provides a way to set an invariant logical event
> >> source number for an IRQ. It is set with the H_INT_SET_SOURCE_CONFIG
> >> hcall.
> >>
> >> Notification of the CPU will be done in the following patch.
> >>
> >> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> >> ---
> >>  hw/intc/spapr_xive.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++
> >>  1 file changed, 67 insertions(+)
> >>
> >> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
> >> index 557a7e2535b5..4bc61cfda67a 100644
> >> --- a/hw/intc/spapr_xive.c
> >> +++ b/hw/intc/spapr_xive.c
> >> @@ -175,9 +175,76 @@ static const MemoryRegionOps spapr_xive_tm_ops = {
> >>      },
> >>  };
> >>  
> >> +static void spapr_xive_eq_push(XiveEQ *eq, uint32_t data)
> >> +{
> >> +    uint64_t qaddr_base = (((uint64_t)(eq->w2 & 0x0fffffff)) << 32) | eq->w3;
> >> +    uint32_t qsize = GETFIELD(EQ_W0_QSIZE, eq->w0);
> >> +    uint32_t qindex = GETFIELD(EQ_W1_PAGE_OFF, eq->w1);
> >> +    uint32_t qgen = GETFIELD(EQ_W1_GENERATION, eq->w1);
> >> +
> >> +    uint64_t qaddr = qaddr_base + (qindex << 2);
> >> +    uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));
> >> +    uint32_t qentries = 1 << (qsize + 10);
> >> +
> >> +    if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata))) {
> >> +        qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write EQ data @0x%"
> >> +                      HWADDR_PRIx "\n", __func__, qaddr);
> >> +        return;
> >> +    }
> >> +
> >> +    qindex = (qindex + 1) % qentries;
> >> +    if (qindex == 0) {
> >> +        qgen ^= 1;
> >> +        eq->w1 = SETFIELD(EQ_W1_GENERATION, eq->w1, qgen);
> >> +    }
> >> +    eq->w1 = SETFIELD(EQ_W1_PAGE_OFF, eq->w1, qindex);
> >> +}
> >> +
> >>  static void spapr_xive_irq(sPAPRXive *xive, int srcno)
> >>  {
> >> +    XiveIVE *ive;
> >> +    XiveEQ *eq;
> >> +    uint32_t eq_idx;
> >> +    uint32_t priority;
> >> +
> >> +    ive = spapr_xive_get_ive(xive, srcno);
> >> +    if (!ive || !(ive->w & IVE_VALID)) {
> >> +        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %d\n", srcno);
> >> +        return;
> >> +    }
> >> +
> >> +    if (ive->w & IVE_MASKED) {
> >> +        return;
> >> +    }
> >> +
> >> +    /* Find our XiveEQ */
> >> +    eq_idx = GETFIELD(IVE_EQ_INDEX, ive->w);
> >> +    eq = spapr_xive_get_eq(xive, eq_idx);
> >> +    if (!eq) {
> >> +        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No EQ for LISN %d\n", srcno);
> >> +        return;
> >> +    }
> >> +
> >> +    if (eq->w0 & EQ_W0_ENQUEUE) {
> >> +        spapr_xive_eq_push(eq, GETFIELD(IVE_EQ_DATA, ive->w));
> >> +    } else {
> >> +        qemu_log_mask(LOG_UNIMP, "XIVE: !ENQUEUE not implemented\n");
> >> +    }
> >> +
> >> +    if (!(eq->w0 & EQ_W0_UCOND_NOTIFY)) {
> >> +        qemu_log_mask(LOG_UNIMP, "XIVE: !UCOND_NOTIFY not implemented\n");
> >> +    }
> >> +
> >> +    if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {
> >> +        priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);
> >>  
> >> +        /* The EQ is masked. Can this happen ?  */
> >> +        if (priority == 0xff) {
> >> +            return;
> > 
> > How does the 8-bit priority field here interact with the 3-bit
> > priority which selects which EQ to use?
> 
> priority OxFF is a special case kept for masking, see the hcall 
> h_int_set_source_config. It should never reach the EQ lookup 
> routines. So may be an assert would be better here.

Ok, if this situation can't be guest triggered, only by a bug in the
rest of the XIVE code, then an assert() is better.

> 
> C. 
> 
> > 
> >> +        }
> >> +    } else {
> >> +        qemu_log_mask(LOG_UNIMP, "XIVE: w7 format1 not implemented\n");
> >> +    }
> >>  }
> >>  
> >>  /*
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

  reply	other threads:[~2017-09-20  6:56 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-11 17:12 [Qemu-devel] [RFC PATCH v2 00/21] Guest exploitation of the XIVE interrupt controller (POWER9) Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 01/21] ppc/xive: introduce a skeleton for the sPAPR XIVE interrupt controller Cédric Le Goater
2017-09-19  2:27   ` David Gibson
2017-09-19 13:15     ` Cédric Le Goater
2017-09-22 11:00       ` David Gibson
2017-09-22 12:42         ` Cédric Le Goater
2017-09-26  3:54           ` David Gibson
2017-09-26  9:45             ` Benjamin Herrenschmidt
2017-11-16 16:48               ` Cédric Le Goater
2017-11-16 15:58             ` Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 02/21] migration: add VMSTATE_STRUCT_VARRAY_UINT32_ALLOC Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 03/21] ppc/xive: define the XIVE internal tables Cédric Le Goater
2017-09-19  2:39   ` David Gibson
2017-09-19 13:46     ` Cédric Le Goater
2017-09-20  4:33       ` David Gibson
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 04/21] ppc/xive: provide a link to the sPAPR ICS object under XIVE Cédric Le Goater
2017-09-11 22:04   ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2017-09-12  5:47     ` Cédric Le Goater
2017-09-19  2:44   ` [Qemu-devel] " David Gibson
2017-09-19 14:46     ` Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 05/21] ppc/xive: allocate IRQ numbers for the IPIs Cédric Le Goater
2017-09-19  2:45   ` David Gibson
2017-09-19 14:52     ` Cédric Le Goater
2017-09-20  4:35       ` David Gibson
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 06/21] ppc/xive: introduce handlers for interrupt sources Cédric Le Goater
2017-09-19  2:48   ` David Gibson
2017-09-19 15:08     ` Cédric Le Goater
2017-09-20  4:38       ` David Gibson
2017-09-21 14:11         ` Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 07/21] ppc/xive: add MMIO handlers for the XIVE " Cédric Le Goater
2017-09-19  2:57   ` David Gibson
2017-09-20 12:54     ` Cédric Le Goater
2017-09-22 10:58       ` David Gibson
2017-09-22 12:26         ` Cédric Le Goater
2017-09-28  8:27       ` Benjamin Herrenschmidt
2017-09-20 13:05     ` Cédric Le Goater
2017-09-28  8:29       ` Benjamin Herrenschmidt
2017-09-28 13:20         ` David Gibson
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 08/21] ppc/xive: describe the XIVE interrupt source flags Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 09/21] ppc/xive: extend the interrupt presenter model for XIVE Cédric Le Goater
2017-09-19  7:36   ` David Gibson
2017-09-19 19:28     ` Cédric Le Goater
2017-09-22 10:58       ` David Gibson
2017-09-22 12:27         ` Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 10/21] ppc/xive: add MMIO handlers for the XIVE TIMA Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in OS event queue Cédric Le Goater
2017-09-19  7:45   ` David Gibson
2017-09-19 19:36     ` Cédric Le Goater
2017-09-20  6:34       ` David Gibson [this message]
2017-09-28  8:12         ` Benjamin Herrenschmidt
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 12/21] ppc/xive: notify the CPU when interrupt priority is more privileged Cédric Le Goater
2017-09-19  7:50   ` David Gibson
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 13/21] ppc/xive: handle interrupt acknowledgment by the O/S Cédric Le Goater
2017-09-19  7:53   ` David Gibson
2017-09-20  9:40     ` Cédric Le Goater
2017-09-28  8:14       ` Benjamin Herrenschmidt
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 14/21] ppc/xive: add support for the SET_OS_PENDING command Cédric Le Goater
2017-09-19  7:55   ` David Gibson
2017-09-20  9:47     ` Cédric Le Goater
2017-09-28  8:18       ` Benjamin Herrenschmidt
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 15/21] spapr: modify spapr_populate_pci_dt() to use a 'nr_irqs' argument Cédric Le Goater
2017-09-19  7:56   ` David Gibson
2017-09-20  9:49     ` Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 16/21] spapr: add a XIVE object to the sPAPR machine Cédric Le Goater
2017-09-19  8:38   ` David Gibson
2017-09-20  9:51     ` Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 17/21] ppc/xive: add hcalls support Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 18/21] ppc/xive: add device tree support Cédric Le Goater
2017-09-19  8:44   ` David Gibson
2017-09-20 12:26     ` Cédric Le Goater
2017-09-21  1:35       ` David Gibson
2017-09-21 11:21         ` Cédric Le Goater
2017-09-22 10:54           ` David Gibson
2017-09-28  8:43           ` Benjamin Herrenschmidt
2017-09-28  8:51             ` Cédric Le Goater
2017-09-28 10:03               ` Benjamin Herrenschmidt
2017-09-28 12:50                 ` Cédric Le Goater
2017-09-28  8:31         ` Benjamin Herrenschmidt
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 19/21] ppc/xive: introduce a helper to map the XIVE memory regions Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 20/21] ppc/xics: introduce a qirq_get() helper in the XICSFabric Cédric Le Goater
2017-09-11 17:12 ` [Qemu-devel] [RFC PATCH v2 21/21] spapr: activate XIVE exploitation mode Cédric Le Goater
2017-09-19  8:20 ` [Qemu-devel] [RFC PATCH v2 00/21] Guest exploitation of the XIVE interrupt controller (POWER9) David Gibson
2017-09-19  8:46   ` David Gibson
2017-09-20 12:33     ` Cédric Le Goater
2017-09-21  1:25       ` David Gibson
2017-09-21 14:18         ` Cédric Le Goater
2017-09-22 10:33           ` David Gibson
2017-09-22 12:32             ` Cédric Le Goater
2017-09-28  8:23       ` Benjamin Herrenschmidt
2017-09-28 13:17         ` David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170920063416.GM5520@umbus.fritz.box \
    --to=david@gibson.dropbear.id.au \
    --cc=agraf@suse.de \
    --cc=aik@ozlabs.ru \
    --cc=benh@kernel.crashing.org \
    --cc=clg@kaod.org \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).