From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37797) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dul0R-0004GB-NE for qemu-devel@nongnu.org; Wed, 20 Sep 2017 15:50:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dul0M-0007xO-RA for qemu-devel@nongnu.org; Wed, 20 Sep 2017 15:49:59 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:33867) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dul0M-0007xA-Mq for qemu-devel@nongnu.org; Wed, 20 Sep 2017 15:49:54 -0400 Received: by mail-qk0-x243.google.com with SMTP id d70so2332488qkc.1 for ; Wed, 20 Sep 2017 12:49:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 20 Sep 2017 16:49:31 -0300 Message-Id: <20170920194934.23071-4-f4bug@amsat.org> In-Reply-To: <20170920194934.23071-1-f4bug@amsat.org> References: <20170920194934.23071-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 3/6] mips: split cpu_mips_realize_env() out of cpu_mips_init() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Igor Mammedov , Eduardo Habkost , Aurelien Jarno , Yongbok Kim , Marcel Apfelbaum Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , James Hogan , Thomas Huth so it can be used in mips_cpu_realizefn() in the next commit Signed-off-by: Philippe Mathieu-Daudé Tested-by: Igor Mammedov Tested-by: James Hogan Reviewed-by: Eduardo Habkost --- target/mips/internal.h | 1 + target/mips/translate.c | 19 ++++++++++++------- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 91c2df4537..cf4c9db427 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -132,6 +132,7 @@ void mips_tcg_init(void); /* TODO QOM'ify CPU reset and remove */ void cpu_state_reset(CPUMIPSState *s); +void cpu_mips_realize_env(CPUMIPSState *env); /* cp0_timer.c */ uint32_t cpu_mips_get_random(CPUMIPSState *env); diff --git a/target/mips/translate.c b/target/mips/translate.c index f0febaf1b2..5fc7979ac5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20512,6 +20512,17 @@ void mips_tcg_init(void) #include "translate_init.c" +void cpu_mips_realize_env(CPUMIPSState *env) +{ + env->exception_base = (int32_t)0xBFC00000; + +#ifndef CONFIG_USER_ONLY + mmu_init(env, env->cpu_model); +#endif + fpu_init(env, env->cpu_model); + mvp_init(env, env->cpu_model); +} + MIPSCPU *cpu_mips_init(const char *cpu_model) { MIPSCPU *cpu; @@ -20524,13 +20535,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model) cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU)); env = &cpu->env; env->cpu_model = def; - env->exception_base = (int32_t)0xBFC00000; - -#ifndef CONFIG_USER_ONLY - mmu_init(env, def); -#endif - fpu_init(env, def); - mvp_init(env, def); + cpu_mips_realize_env(env); object_property_set_bool(OBJECT(cpu), true, "realized", NULL); -- 2.14.1