From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Peter Maydell <peter.maydell@linaro.org>,
Grant Likely <grant.likely@arm.com>,
Jason Wang <jasowang@redhat.com>
Cc: qemu-devel@nongnu.org, "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [Qemu-devel] [PATCH v5 4/7] hw/mdio: Mask out read-only bits.
Date: Fri, 22 Sep 2017 14:13:20 -0300 [thread overview]
Message-ID: <20170922171323.10348-5-f4bug@amsat.org> (raw)
In-Reply-To: <20170922171323.10348-1-f4bug@amsat.org>
From: Grant Likely <grant.likely@arm.com>
The RST and ANEG_RST bits are commands, not settings. An operating
system will get confused (or at least u-boot does) if those bits remain
set after writing to them. Therefore, mask them out on write.
Similarly, no bits in the ID1, ID2, and remote capability registers are
writeable; so mask them out also.
Signed-off-by: Grant Likely <grant.likely@arm.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[PMD: just rebased]
---
include/hw/net/mdio.h | 1 +
hw/net/mdio.c | 16 ++++++++++++----
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h
index b3b4f497c0..ed1879a728 100644
--- a/include/hw/net/mdio.h
+++ b/include/hw/net/mdio.h
@@ -53,6 +53,7 @@
struct qemu_phy {
uint32_t regs[NUM_PHY_REGS];
+ const uint16_t *regs_readonly_mask; /* 0=writable, 1=read-only */
int link;
diff --git a/hw/net/mdio.c b/hw/net/mdio.c
index 33bfbb4623..89a6a3a590 100644
--- a/hw/net/mdio.c
+++ b/hw/net/mdio.c
@@ -109,17 +109,24 @@ static unsigned int mdio_phy_read(struct qemu_phy *phy, unsigned int req)
static void mdio_phy_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
{
- int regnum;
+ int regnum = req & 0x1f;
+ uint16_t mask = phy->regs_readonly_mask[regnum];
- regnum = req & 0x1f;
- D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
+ D(printf("%s reg[%d] = %x; mask=%x\n", __func__, regnum, data, mask));
switch (regnum) {
default:
- phy->regs[regnum] = data;
+ phy->regs[regnum] = (phy->regs[regnum] & mask) | (data & ~mask);
break;
}
}
+static const uint16_t default_readonly_mask[32] = {
+ [PHY_CTRL] = PHY_CTRL_RST | PHY_CTRL_ANEG_RST,
+ [PHY_ID1] = 0xffff,
+ [PHY_ID2] = 0xffff,
+ [PHY_LP_ABILITY] = 0xffff,
+};
+
void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)
{
phy->regs[PHY_CTRL] = 0x3100;
@@ -128,6 +135,7 @@ void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)
phy->regs[PHY_ID2] = id2;
/* Autonegotiation advertisement reg. */
phy->regs[PHY_AUTONEG_ADV] = 0x01e1;
+ phy->regs_readonly_mask = default_readonly_mask;
phy->link = 1;
phy->read = mdio_phy_read;
--
2.14.1
next prev parent reply other threads:[~2017-09-22 17:13 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-22 17:13 [Qemu-devel] [PATCH v5 0/7] Generalize MDIO framework Philippe Mathieu-Daudé
2017-09-22 17:13 ` [Qemu-devel] [PATCH v5 1/7] hw/mdio: Generalize etraxfs MDIO bitbanging emulation Philippe Mathieu-Daudé
2018-02-27 22:30 ` Alistair Francis
2017-09-22 17:13 ` [Qemu-devel] [PATCH v5 2/7] hw/mdio: Add PHY register definition Philippe Mathieu-Daudé
2018-02-27 22:31 ` Alistair Francis
2017-09-22 17:13 ` [Qemu-devel] [PATCH v5 3/7] hw/mdio: Generalize phy initialization routine Philippe Mathieu-Daudé
2018-02-27 22:33 ` Alistair Francis
2018-05-28 3:09 ` Philippe Mathieu-Daudé
2017-09-22 17:13 ` Philippe Mathieu-Daudé [this message]
2018-02-27 22:37 ` [Qemu-devel] [PATCH v5 4/7] hw/mdio: Mask out read-only bits Alistair Francis
2017-09-22 17:13 ` [Qemu-devel] [PATCH v5 5/7] hw/mdio: Refactor bitbanging state machine Philippe Mathieu-Daudé
2018-02-27 22:40 ` Alistair Francis
2017-09-22 17:13 ` [Qemu-devel] [PATCH v5 6/7] hw/mdio: Add VMState support Philippe Mathieu-Daudé
2018-02-27 22:42 ` Alistair Francis
2017-09-22 17:13 ` [Qemu-devel] [PATCH v5 7/7] hw/mdio: Use bitbang core for smc91c111 network device Philippe Mathieu-Daudé
2017-09-22 17:19 ` [Qemu-devel] [PATCH v5 0/7] Generalize MDIO framework Alistair Francis
2017-10-09 13:21 ` Edgar E. Iglesias
2018-02-27 23:18 ` Philippe Mathieu-Daudé
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