From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dxc4y-0004ns-C1 for qemu-devel@nongnu.org; Thu, 28 Sep 2017 12:54:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dxc4x-0004Ma-JD for qemu-devel@nongnu.org; Thu, 28 Sep 2017 12:54:28 -0400 Received: from mail-pf0-x22f.google.com ([2607:f8b0:400e:c00::22f]:54707) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dxc4x-0004M0-D1 for qemu-devel@nongnu.org; Thu, 28 Sep 2017 12:54:27 -0400 Received: by mail-pf0-x22f.google.com with SMTP id d187so1138635pfg.11 for ; Thu, 28 Sep 2017 09:54:27 -0700 (PDT) Received: from bigtime.twiddle.net ([70.35.39.2]) by smtp.gmail.com with ESMTPSA id e133sm3062332pfh.177.2017.09.28.09.54.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Sep 2017 09:54:25 -0700 (PDT) From: Richard Henderson Date: Thu, 28 Sep 2017 09:54:11 -0700 Message-Id: <20170928165414.7339-7-richard.henderson@linaro.org> In-Reply-To: <20170928165414.7339-1-richard.henderson@linaro.org> References: <20170928165414.7339-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 6/9] arm: Support Capstone in disas_set_info List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- disas.c | 3 +++ target/arm/cpu.c | 21 ++++++++++++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/disas.c b/disas.c index 1c44514254..23c4742f8d 100644 --- a/disas.c +++ b/disas.c @@ -451,6 +451,7 @@ void disas(FILE *out, void *code, unsigned long size) print_insn = print_insn_ppc; #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS) print_insn = print_insn_arm_a64; + s.info.cap_arch = CS_ARCH_ARM64; #elif defined(__alpha__) print_insn = print_insn_alpha; #elif defined(__sparc__) @@ -458,6 +459,8 @@ void disas(FILE *out, void *code, unsigned long size) s.info.mach = bfd_mach_sparc_v9b; #elif defined(__arm__) print_insn = print_insn_arm; + s.info.cap_arch = CS_ARCH_ARM; + /* TCG only generates code for arm mode. */ #elif defined(__MIPSEB__) print_insn = print_insn_big_mips; #elif defined(__MIPSEL__) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4300de66e2..e5f84066b4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -33,6 +33,7 @@ #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" +#include "disas/capstone.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { @@ -489,10 +490,24 @@ static void arm_disas_set_info(CPUState *cpu, disassemble_info *info) #if defined(CONFIG_ARM_A64_DIS) info->print_insn = print_insn_arm_a64; #endif - } else if (env->thumb) { - info->print_insn = print_insn_thumb1; + info->cap_arch = CS_ARCH_ARM64; } else { - info->print_insn = print_insn_arm; + int cap_mode; + if (env->thumb) { + info->print_insn = print_insn_thumb1; + cap_mode = CS_MODE_THUMB; + } else { + info->print_insn = print_insn_arm; + cap_mode = CS_MODE_ARM; + } + if (arm_feature(env, ARM_FEATURE_V8)) { + cap_mode |= CS_MODE_V8; + } + if (arm_feature(env, ARM_FEATURE_M)) { + cap_mode |= CS_MODE_MCLASS; + } + info->cap_arch = CS_ARCH_ARM; + info->cap_mode = cap_mode; } if (bswap_code(arm_sctlr_b(env))) { #ifdef TARGET_WORDS_BIGENDIAN -- 2.13.5