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From: David Gibson <david@gibson.dropbear.id.au>
To: Igor Mammedov <imammedo@redhat.com>
Cc: qemu-devel@nongnu.org, "Alexander Graf" <agraf@suse.de>,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"open list:ppce500" <qemu-ppc@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 22/23] ppc: pnv: drop PnvChipClass::cpu_model field
Date: Fri, 6 Oct 2017 19:46:34 +1100	[thread overview]
Message-ID: <20171006084634.GA10961@umbus.fritz.box> (raw)
In-Reply-To: <1507220690-265042-23-git-send-email-imammedo@redhat.com>

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On Thu, Oct 05, 2017 at 06:24:49PM +0200, Igor Mammedov wrote:
> deduce core type directly from chip type instead of
> maintaining type mapping in PnvChipClass::cpu_model.
> 
> Signed-off-by: Igor Mammedov <imammedo@redhat.com>
> ---
>  include/hw/ppc/pnv.h      |  1 -
>  include/hw/ppc/pnv_core.h |  1 -
>  hw/ppc/pnv.c              | 25 +++++++++++++------------
>  hw/ppc/pnv_core.c         |  5 -----
>  4 files changed, 13 insertions(+), 19 deletions(-)
> 
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index d82eee1..20244da 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -69,7 +69,6 @@ typedef struct PnvChipClass {
>      SysBusDeviceClass parent_class;
>  
>      /*< public >*/
> -    const char *cpu_model;
>      PnvChipType  chip_type;
>      uint64_t     chip_cfam_id;
>      uint64_t     cores_mask;
> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> index a336a1f..e337af7 100644
> --- a/include/hw/ppc/pnv_core.h
> +++ b/include/hw/ppc/pnv_core.h
> @@ -46,6 +46,5 @@ typedef struct PnvCoreClass {
>  
>  #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
>  #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
> -extern char *pnv_core_typename(const char *model);
>  
>  #endif /* _PPC_PNV_CORE_H */
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 9c5eb7c..ab7083b 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -55,6 +55,16 @@
>  #define KERNEL_LOAD_ADDR        0x20000000
>  #define INITRD_LOAD_ADDR        0x40000000
>  
> +static const char *pvn_chip_core_typename(const PnvChip *o)

s/pvn/pnv/ again.

> +{
> +    const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
> +    int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
> +    char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
> +    const char *core_type = object_class_get_name(object_class_by_name(s));
> +    g_free(s);
> +    return core_type;
> +}
> +
>  /*
>   * On Power Systems E880 (POWER8), the max cpus (threads) should be :
>   *     4 * 4 sockets * 12 cores * 8 threads = 1536
> @@ -270,8 +280,7 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
>  
>  static void powernv_populate_chip(PnvChip *chip, void *fdt)
>  {
> -    PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> -    char *typename = pnv_core_typename(pcc->cpu_model);
> +    const char *typename = pvn_chip_core_typename(chip);
>      size_t typesize = object_type_get_instance_size(typename);
>      int i;
>  
> @@ -301,7 +310,6 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
>          powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
>                                       chip->ram_size);
>      }
> -    g_free(typename);
>  }
>  
>  static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
> @@ -713,7 +721,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
>      DeviceClass *dc = DEVICE_CLASS(klass);
>      PnvChipClass *k = PNV_CHIP_CLASS(klass);
>  
> -    k->cpu_model = "power8e_v2.1";
>      k->chip_type = PNV_CHIP_POWER8E;
>      k->chip_cfam_id = 0x221ef04980000000ull;  /* P8 Murano DD2.1 */
>      k->cores_mask = POWER8E_CORE_MASK;
> @@ -735,7 +742,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
>      DeviceClass *dc = DEVICE_CLASS(klass);
>      PnvChipClass *k = PNV_CHIP_CLASS(klass);
>  
> -    k->cpu_model = "power8_v2.0";
>      k->chip_type = PNV_CHIP_POWER8;
>      k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
>      k->cores_mask = POWER8_CORE_MASK;
> @@ -757,7 +763,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
>      DeviceClass *dc = DEVICE_CLASS(klass);
>      PnvChipClass *k = PNV_CHIP_CLASS(klass);
>  
> -    k->cpu_model = "power8nvl_v1.0";
>      k->chip_type = PNV_CHIP_POWER8NVL;
>      k->chip_cfam_id = 0x120d304980000000ull;  /* P8 Naples DD1.0 */
>      k->cores_mask = POWER8_CORE_MASK;
> @@ -779,7 +784,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
>      DeviceClass *dc = DEVICE_CLASS(klass);
>      PnvChipClass *k = PNV_CHIP_CLASS(klass);
>  
> -    k->cpu_model = "power9_v1.0";
>      k->chip_type = PNV_CHIP_POWER9;
>      k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
>      k->cores_mask = POWER9_CORE_MASK;
> @@ -854,7 +858,7 @@ static void pnv_chip_init(Object *obj)
>  static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
>  {
>      PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> -    char *typename = pnv_core_typename(pcc->cpu_model);
> +    const char *typename = pvn_chip_core_typename(chip);
>      size_t typesize = object_type_get_instance_size(typename);
>      int i, j;
>      char *name;
> @@ -879,8 +883,6 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
>              memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
>          }
>      }
> -
> -    g_free(typename);
>  }
>  
>  static void pnv_chip_realize(DeviceState *dev, Error **errp)
> @@ -888,7 +890,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
>      PnvChip *chip = PNV_CHIP(dev);
>      Error *error = NULL;
>      PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
> -    char *typename = pnv_core_typename(pcc->cpu_model);
> +    const char *typename = pvn_chip_core_typename(chip);
>      size_t typesize = object_type_get_instance_size(typename);
>      int i, core_hwid;
>  
> @@ -947,7 +949,6 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
>                                  &PNV_CORE(pnv_core)->xscom_regs);
>          i++;
>      }
> -    g_free(typename);
>  
>      /* Create LPC controller */
>      object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 000c87e..621b69e 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -246,9 +246,4 @@ static const TypeInfo pnv_core_infos[] = {
>      DEFINE_PNV_CORE_TYPE("power9_v1.0"),
>  };
>  
> -char *pnv_core_typename(const char *model)
> -{
> -    return g_strdup_printf(PNV_CORE_TYPE_NAME("%s"), model);
> -}
> -
>  DEFINE_TYPES(pnv_core_infos)

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  parent reply	other threads:[~2017-10-06  8:55 UTC|newest]

Thread overview: 81+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-05 16:24 [Qemu-devel] [PATCH 00/23] generalize parsing of cpu_model (part 3/PPC) Igor Mammedov
2017-10-05 16:24 ` [Qemu-devel] [PATCH 01/23] qom: update doc comment for type_register[_static]() Igor Mammedov
2017-10-06  2:57   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 02/23] qom: introduce type_register_static_array() Igor Mammedov
2017-10-06  2:58   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 03/23] qom: add helper macro DEFINE_TYPES() Igor Mammedov
2017-10-06  3:06   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 04/23] ppc: mpc8544ds/e500plat: use generic cpu_model parsing Igor Mammedov
2017-10-06  3:02   ` David Gibson
2017-10-06  8:27     ` Igor Mammedov
2017-10-06  9:12       ` David Gibson
2017-10-06  9:37         ` Igor Mammedov
2017-10-05 16:24 ` [Qemu-devel] [PATCH 05/23] ppc: mac_newworld: " Igor Mammedov
2017-10-06  3:08   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 06/23] ppc: mac_oldworld: " Igor Mammedov
2017-10-06  3:09   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 07/23] ppc: bamboo: " Igor Mammedov
2017-10-06  3:11   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 08/23] ppc: replace cpu_model with cpu_type on ref405ep, taihu boards Igor Mammedov
2017-10-06  3:12   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 09/23] ppc: virtex-ml507: replace cpu_model with cpu_type Igor Mammedov
2017-10-06  3:13   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 10/23] ppc: 40p/prep: " Igor Mammedov
2017-10-06  3:14   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 11/23] ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model() Igor Mammedov
2017-10-05 18:35   ` Greg Kurz
2017-10-06  3:16   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 12/23] ppc: move '-cpu foo, compat=xxx' parsing into ppc_cpu_parse_featurestr() Igor Mammedov
2017-10-05 19:05   ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2017-10-06  8:40     ` Igor Mammedov
2017-10-06  3:54   ` [Qemu-devel] " David Gibson
2017-10-06  9:03     ` Igor Mammedov
2017-10-06  9:17       ` David Gibson
2017-10-06  9:52         ` Igor Mammedov
2017-10-06 10:14           ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 13/23] ppc: spapr: define core types statically Igor Mammedov
2017-10-05 20:31   ` Greg Kurz
2017-10-06  3:58   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 14/23] ppc: spapr: use cpu type name directly Igor Mammedov
2017-10-05 20:47   ` Greg Kurz
2017-10-06  4:01   ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 15/23] ppc: spapr: register 'host' core type along with the rest of core types Igor Mammedov
2017-10-05 21:55   ` Greg Kurz
2017-10-06  4:41   ` David Gibson
2017-10-06  9:07     ` Igor Mammedov
2017-10-06  9:13       ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 16/23] ppc: spapr: use cpu model names as tcg defaults instead of aliases Igor Mammedov
2017-10-06  4:43   ` David Gibson
2017-10-06  7:39   ` Greg Kurz
2017-10-06  9:27     ` Igor Mammedov
2017-10-06 10:12       ` Greg Kurz
2017-10-05 16:24 ` [Qemu-devel] [PATCH 17/23] ppc: spapr: use generic cpu_model parsing Igor Mammedov
2017-10-06  5:04   ` David Gibson
2017-10-06  9:20     ` Igor Mammedov
2017-10-06  9:35       ` David Gibson
2017-10-06  9:56         ` Igor Mammedov
2017-10-05 16:24 ` [Qemu-devel] [PATCH 18/23] ppc: pnv: " Igor Mammedov
2017-10-06  6:21   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-10-06  8:34   ` [Qemu-devel] " David Gibson
2017-10-06  9:30     ` Igor Mammedov
2017-10-06 11:25       ` David Gibson
2017-10-09  5:44         ` Igor Mammedov
2017-10-09  6:59           ` David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 19/23] ppc: pnv: normalize core/chip type names Igor Mammedov
2017-10-06  6:22   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-10-06  8:37   ` [Qemu-devel] " David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 20/23] ppc: pnv: drop PnvCoreClass::cpu_oc field Igor Mammedov
2017-10-06  6:27   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-10-06  8:41   ` [Qemu-devel] " David Gibson
2017-10-06  9:31     ` Igor Mammedov
2017-10-05 16:24 ` [Qemu-devel] [PATCH 21/23] ppc: pnv: define core types statically Igor Mammedov
2017-10-06  6:24   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-10-06  8:42   ` [Qemu-devel] " David Gibson
2017-10-05 16:24 ` [Qemu-devel] [PATCH 22/23] ppc: pnv: drop PnvChipClass::cpu_model field Igor Mammedov
2017-10-06  6:27   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-10-06  8:46   ` David Gibson [this message]
2017-10-06  9:32     ` [Qemu-devel] " Igor Mammedov
2017-10-05 16:24 ` [Qemu-devel] [PATCH 23/23] ppc: pnv: consolidate type definitions and batch register them Igor Mammedov
2017-10-06  6:27   ` [Qemu-devel] [Qemu-ppc] " Cédric Le Goater
2017-10-06  8:47   ` [Qemu-devel] " David Gibson
2017-10-05 17:31 ` [Qemu-devel] [PATCH 00/23] generalize parsing of cpu_model (part 3/PPC) no-reply

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