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From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: "Cédric Le Goater" <clg@kaod.org>,
	qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	"Benjamin Herrenschmidt" <benh@kernel.crashing.org>,
	"Alexey Kardashevskiy" <aik@ozlabs.ru>
Subject: Re: [Qemu-devel] [PATCH 0/2] disable the decrementer interrupt when a CPU is unplugged
Date: Fri, 6 Oct 2017 20:09:26 +1100	[thread overview]
Message-ID: <20171006090926.GF10961@umbus.fritz.box> (raw)
In-Reply-To: <87poa0g62t.fsf@localhost.localdomain.i-did-not-set--mail-host-address--so-tickle-me>

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On Fri, Oct 06, 2017 at 11:40:02AM +0530, Nikunj A Dadhania wrote:
> Cédric Le Goater <clg@kaod.org> writes:
> 
> > Hello,
> >
> > When a CPU is stopped with the 'stop-self' RTAS call, its state
> > 'halted' is switched to 1 and, in this case, the MSR is not taken into
> > account anymore in the cpu_has_work() routine. Only the pending
> > hardware interrupts are checked with their LPCR:PECE* enablement bit.
> >
> > If the DECR timer fires after 'stop-self' is called and before the CPU
> > 'stop' state is reached, the nearly-dead CPU will have some work to do
> > and the guest will crash. This case happens very frequently with the
> > not yet upstream P9 XIVE exploitation mode. In XICS mode, the DECR is
> > occasionally fired but after 'stop' state, so no work is to be done
> > and the guest survives.
> >
> > I suspect there is a race between the QEMU mainloop triggering the
> > timers and the TCG CPU thread but I could not quite identify the root
> > cause. To be safe, let's disable the decrementer interrupt in the LPCR
> > when the CPU is halted and reenable it when the CPU is restarted.
> 
> Moreover, disabling the DECR in the reset path solves the TCG multi cpu
> reboot case, as reboot path does not call stop-cpu rtas call.
> 
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index 3e20b1d886..c5150ee590 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -86,6 +86,15 @@ static void spapr_cpu_reset(void *opaque)
>      cs->halted = 1;
>  
>      env->spr[SPR_HIOR] = 0;
> +    /* Disable DECR for secondary cpus */
> +    if (cs != first_cpu) {
> +        if (env->mmu_model == POWERPC_MMU_3_00) {
> +            env->spr[SPR_LPCR] &= ~LPCR_DEE;
> +        } else {
> +            /* P7 and P8 both have same bit for DECR */
> +            env->spr[SPR_LPCR] &= ~LPCR_P8_PECE3;
> +        }
> +    }
>  }

This seems reasonable.

>  
>  static void spapr_cpu_destroy(PowerPCCPU *cpu)
> 
> 
> Regards
> Nikunj
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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      parent reply	other threads:[~2017-10-06  9:10 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-05 16:49 [Qemu-devel] [PATCH 0/2] disable the decrementer interrupt when a CPU is unplugged Cédric Le Goater
2017-10-05 16:49 ` [Qemu-devel] [PATCH 1/2] spapr/rtas: " Cédric Le Goater
2017-10-06  9:07   ` David Gibson
2017-10-06  9:53     ` Benjamin Herrenschmidt
2017-10-06 10:10       ` David Gibson
2017-10-09 14:28         ` Cédric Le Goater
2017-10-06 21:15     ` Cédric Le Goater
2017-10-07  5:16       ` David Gibson
2017-10-05 16:49 ` [Qemu-devel] [PATCH 2/2] spapr/rtas: do not reset the MSR in stop-self command Cédric Le Goater
2017-10-06  9:08   ` David Gibson
2017-10-06  6:10 ` [Qemu-devel] [PATCH 0/2] disable the decrementer interrupt when a CPU is unplugged Nikunj A Dadhania
2017-10-06  6:14   ` Cédric Le Goater
2017-10-06  7:46   ` Benjamin Herrenschmidt
2017-10-06  7:53     ` Cédric Le Goater
2017-10-06  8:11     ` Nikunj A Dadhania
2017-10-06  9:09   ` David Gibson [this message]

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