From: Aaron Lindsay <alindsay@codeaurora.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
mspradli@codeaurora.org
Subject: Re: [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0]
Date: Mon, 9 Oct 2017 16:40:50 -0400 [thread overview]
Message-ID: <20171009204050.GC3676@codeaurora.org> (raw)
In-Reply-To: <CAFEAcA-18f=10NENHVpqmhobf2camcqxVaq8KzquCSkJGknoZQ@mail.gmail.com>
On Oct 09 19:19, Peter Maydell wrote:
> On 19 April 2017 at 18:41, Aaron Lindsay <alindsay@codeaurora.org> wrote:
> > A53 advertises ARM_FEATURE_PMU, but wasn't initializing pmceid[01]
> >
> > Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
> > ---
> > target/arm/cpu.c | 2 +-
> > target/arm/cpu64.c | 2 ++
> > 2 files changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> > index 04b062c..921b028 100644
> > --- a/target/arm/cpu.c
> > +++ b/target/arm/cpu.c
> > @@ -1342,7 +1342,7 @@ static void cortex_a15_initfn(Object *obj)
> > cpu->id_pfr0 = 0x00001131;
> > cpu->id_pfr1 = 0x00011011;
> > cpu->id_dfr0 = 0x02010555;
> > - cpu->pmceid0 = 0x0000000;
> > + cpu->pmceid0 = 0x00000000;
> > cpu->pmceid1 = 0x00000000;
> > cpu->id_afr0 = 0x00000000;
> > cpu->id_mmfr0 = 0x10201105;
>
> This is A15 code, which the commit message doesn't say anything about.
> Fixing this code style nit should probably be a separate patch.
I'll split this off for the next version.
> > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> > index 670c07a..7b1642e 100644
> > --- a/target/arm/cpu64.c
> > +++ b/target/arm/cpu64.c
> > @@ -198,6 +198,8 @@ static void aarch64_a53_initfn(Object *obj)
> > cpu->id_isar5 = 0x00011121;
> > cpu->id_aa64pfr0 = 0x00002222;
> > cpu->id_aa64dfr0 = 0x10305106;
> > + cpu->pmceid0 = 0x00000000;
> > + cpu->pmceid1 = 0x00000000;
> > cpu->id_aa64isar0 = 0x00011120;
> > cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
> > cpu->dbgdidr = 0x3516d000;
>
> Does this actually make a difference? The field values should be 0
> anyway if the CPU-specific initfn doesn't set them to anything.
Perhaps not. I thought the omission was accidental since A15 and A57
both initialize them to zero (added in
4054bfa9e7986c9b7d2bf70f9e10af9647e376fc: "target-arm: Add the pmceid0
and pmceid1 registers")
-Aaron
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
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next prev parent reply other threads:[~2017-10-09 20:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-19 17:41 [Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3 Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0] Aaron Lindsay
2017-10-09 18:19 ` Peter Maydell
2017-10-09 20:40 ` Aaron Lindsay [this message]
2017-04-19 17:41 ` [Qemu-devel] [PATCH 02/13] target/arm: Check PMCNTEN for whether PMCCNTR is enabled Aaron Lindsay
2017-10-17 12:48 ` Peter Maydell
2017-04-19 17:41 ` [Qemu-devel] [PATCH 03/13] target/arm: Reorganize PMCCNTR read, write, sync Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 04/13] target/arm: Mask PMU register writes based on PMCR_EL0.N Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 05/13] target/arm: Allow AArch32 access for PMCCFILTR Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 06/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0 Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 07/13] target/arm: Implement PMOVSSET Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 08/13] target/arm: Split arm_ccnt_enabled into generic pmu_counter_enabled Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 09/13] target/arm: Add array for supported PMU events, generate PMCEID[01] Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 10/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 11/13] target/arm: PMU: Add instruction and cycle events Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 12/13] target/arm: PMU: Set PMCR.N to 4 Aaron Lindsay
2017-04-19 17:41 ` [Qemu-devel] [PATCH 13/13] target/arm: Implement PMSWINC Aaron Lindsay
2017-04-19 18:22 ` [Qemu-devel] [PATCH 00/13] More fully implement ARM PMUv3 no-reply
-- strict thread matches above, loose matches on Subject: below --
2017-09-30 2:08 [Qemu-devel] [PATCH v2 " Aaron Lindsay
2017-09-30 2:08 ` [Qemu-devel] [PATCH 01/13] target/arm: A53: Initialize PMCEID[0] Aaron Lindsay
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