From: "Alex Bennée" <alex.bennee@linaro.org>
To: richard.henderson@linaro.org
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org,
qemu-arm@nongnu.org, "Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework
Date: Fri, 13 Oct 2017 17:24:34 +0100 [thread overview]
Message-ID: <20171013162438.32458-27-alex.bennee@linaro.org> (raw)
In-Reply-To: <20171013162438.32458-1-alex.bennee@linaro.org>
This is a simple pattern based framework for testing our softfloat
implementation. It is easier to use while debugging softfloat itself
than indirectly with a tool like risu.
As the softfloat library is built against given targets we need a
version per target architecture we build.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
tests/Makefile.include | 8 ++++++-
tests/test-softfloat.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 tests/test-softfloat.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 4ca15e6817..8bf1dfd19a 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -156,6 +156,10 @@ check-unit-y += tests/ptimer-test$(EXESUF)
gcov-files-ptimer-test-y = hw/core/ptimer.c
check-unit-y += tests/test-qapi-util$(EXESUF)
gcov-files-test-qapi-util-y = qapi/qapi-util.c
+check-unit-y += tests/test-softfloat$(EXESUF)
+gcov-files-test-softfloat-y = fpu/softfloat.c
+check-unit-y += tests/test-softfloat-aarch64$(EXESUF)
+gcov-files-test-softfloat-aarch64-y = fpu/softfloat.c
check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh
@@ -555,7 +559,7 @@ test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \
tests/rcutorture.o tests/test-rcu-list.o \
tests/test-qdist.o tests/test-shift128.o \
tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \
- tests/atomic_add-bench.o
+ tests/atomic_add-bench.o tests/test-softfloat.o
$(test-obj-y): QEMU_INCLUDES += -Itests
QEMU_CFLAGS += -I$(SRC_PATH)/tests
@@ -604,6 +608,8 @@ tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(tes
tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y)
tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y)
tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y)
+tests/test-softfloat$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o
+tests/test-softfloat-aarch64$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o
tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c
new file mode 100644
index 0000000000..d7b740e1cb
--- /dev/null
+++ b/tests/test-softfloat.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2017, Linaro
+ * Author: Alex Bennée <alex.bennee@linaro.org>
+ *
+ * License: GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "fpu/softfloat.h"
+
+typedef struct {
+ float_status initial_status;
+ float16 in;
+ float16 out;
+ uint8_t final_exception_flags;
+} f16_test_data;
+
+static void test_f16_round_to_int(void)
+{
+ int i;
+ float16 out;
+ float_status flags, *fp = &flags;
+ f16_test_data test_data[] = {
+ { { /* defaults */ }, 0x87FF, 0x8000 },
+ { { /* defaults */ }, 0xE850, 0xE850 },
+ { { /* defaults */ }, 0x0000, 0x0000 },
+ { { /* defaults */ }, 0x857F, 0x8000 },
+ { { /* defaults */ }, 0x74FB, 0x74FB },
+ /* from risu 3b4: 4ef98945 frintp v5.8h, v10.8h */
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x06b1, 0x3c00, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x6966, 0x6966, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x83c0, 0x8000, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xa619, 0x8000, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x9cf4, 0x8000, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee11, 0xee11, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee5c, 0xee5c, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x8004, 0x8000, 0 }
+ };
+
+ for (i = 0; i < ARRAY_SIZE(test_data); ++i) {
+ flags = test_data[i].initial_status;
+ out = float16_round_to_int(test_data[i].in, fp);
+
+ if (!(test_data[i].out == out)) {
+ fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n",
+ __func__, i, test_data[i].out, out);
+ g_test_fail();
+ }
+ }
+}
+
+int main(int argc, char *argv[])
+{
+ g_test_init(&argc, &argv, NULL);
+ g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int);
+ return g_test_run();
+}
--
2.14.1
next prev parent reply other threads:[~2017-10-13 16:32 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
2017-10-13 20:36 ` Richard Henderson
2017-10-14 9:58 ` Laurent Vivier
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN Alex Bennée
2017-10-13 20:49 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns Alex Bennée
2017-10-13 20:52 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX Alex Bennée
2017-10-15 16:13 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
2017-10-15 16:14 ` Richard Henderson
2017-10-15 16:54 ` Peter Maydell
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
2017-10-16 20:10 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix Alex Bennée
2017-10-15 16:28 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode Alex Bennée
2017-10-16 20:16 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing Alex Bennée
2017-10-15 18:02 ` Richard Henderson
2017-10-16 8:20 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support Alex Bennée
2017-10-16 22:01 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) Alex Bennée
2017-10-16 22:08 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX Alex Bennée
2017-10-16 22:24 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc Alex Bennée
2017-10-16 23:47 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions Alex Bennée
2017-10-17 0:06 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) Alex Bennée
2017-10-17 0:36 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same Alex Bennée
2017-10-17 0:39 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) Alex Bennée
2017-10-17 2:17 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int Alex Bennée
2017-10-13 16:24 ` Alex Bennée [this message]
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc Alex Bennée
2017-10-13 16:58 ` [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) no-reply
2017-10-13 16:59 ` no-reply
2017-10-17 2:34 ` Richard Henderson
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