* [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:36 ` Richard Henderson
2017-10-14 9:58 ` Laurent Vivier
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit Alex Bennée
` (31 subsequent siblings)
32 siblings, 2 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Riku Voipio, Laurent Vivier
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
linux-user/main.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 829f974662..5072aa855b 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3854,6 +3854,11 @@ static void handle_arg_log(const char *arg)
qemu_set_log(mask);
}
+static void handle_arg_dfilter(const char *arg)
+{
+ qemu_set_dfilter_ranges(arg, NULL);
+}
+
static void handle_arg_log_filename(const char *arg)
{
qemu_set_log_filename(arg, &error_fatal);
@@ -4054,6 +4059,8 @@ static const struct qemu_argument arg_table[] = {
{"d", "QEMU_LOG", true, handle_arg_log,
"item[,...]", "enable logging of specified items "
"(use '-d help' for a list of items)"},
+ {"dfilter", "QEMU_DFILTER", true, handle_arg_dfilter,
+ "range[,...]","filter logging based on address range"},
{"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
"logfile", "write logs to 'logfile' (default stderr)"},
{"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
@ 2017-10-13 20:36 ` Richard Henderson
2017-10-14 9:58 ` Laurent Vivier
1 sibling, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-13 20:36 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, qemu-devel, qemu-arm, Riku Voipio, Laurent Vivier
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> linux-user/main.c | 7 +++++++
> 1 file changed, 7 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
2017-10-13 20:36 ` Richard Henderson
@ 2017-10-14 9:58 ` Laurent Vivier
1 sibling, 0 replies; 59+ messages in thread
From: Laurent Vivier @ 2017-10-14 9:58 UTC (permalink / raw)
To: Alex Bennée, richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Riku Voipio
Le 13/10/2017 à 18:24, Alex Bennée a écrit :
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> linux-user/main.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 829f974662..5072aa855b 100644
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
` (30 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
---
target/arm/cpu.h | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 89d49cdcb2..3a0f27c782 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1340,6 +1340,7 @@ enum arm_features {
ARM_FEATURE_VBAR, /* has cp15 VBAR */
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
+ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
};
static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 670c07ab6e..973614dfc6 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
}
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit Alex Bennée
@ 2017-10-13 20:44 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-13 20:44 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> ---
> target/arm/cpu.h | 1 +
> target/arm/cpu64.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 89d49cdcb2..3a0f27c782 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1340,6 +1340,7 @@ enum arm_features {
> ARM_FEATURE_VBAR, /* has cp15 VBAR */
> ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
> ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */
> + ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */
> };
>
> static inline int arm_feature(CPUARMState *env, int feature)
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 670c07ab6e..973614dfc6 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -226,6 +226,7 @@ static void aarch64_any_initfn(Object *obj)
> set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
> set_feature(&cpu->env, ARM_FEATURE_CRC);
> + set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
> cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
> cpu->dcz_blocksize = 7; /* 512 bytes */
> }
>
Need to update linux-user/elfload.c, get_elf_hwcap as well (HWCAP_ASIMDHP).
I suppose that will be a separate patch, since we're missing 8 bits from
current linux/arch/arm64/include/uapi/asm/hwcap.h.
... and we probably need to report a kernel arm32 bug that there is no
equivalent bit defined there.
Anyway, as far as this goes,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 01/30] linux-user/main: support dfilter Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 02/30] arm: introduce ARM_V8_FP16 feature bit Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values Alex Bennée
` (29 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Paolo Bonzini, Peter Crosthwaite, Richard Henderson
This allows us to explicitly pass float16 to helpers rather than
assuming uint32_t and dealing with the result. Of course they will be
passed in i32 sized registers by default.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/exec/helper-head.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 1cfc43b9ff..fdb82151d3 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -30,6 +30,7 @@
#define dh_alias_int i32
#define dh_alias_i64 i64
#define dh_alias_s64 i64
+#define dh_alias_f16 i32
#define dh_alias_f32 i32
#define dh_alias_f64 i64
#define dh_alias_ptr ptr
@@ -42,6 +43,7 @@
#define dh_ctype_int int
#define dh_ctype_i64 uint64_t
#define dh_ctype_s64 int64_t
+#define dh_ctype_f16 float16
#define dh_ctype_f32 float32
#define dh_ctype_f64 float64
#define dh_ctype_ptr void *
@@ -98,6 +100,7 @@
#define dh_is_signed_s32 1
#define dh_is_signed_i64 0
#define dh_is_signed_s64 1
+#define dh_is_signed_f16 0
#define dh_is_signed_f32 0
#define dh_is_signed_f64 0
#define dh_is_signed_tl 0
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (2 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 03/30] include/exec/helper-head.h: support f16 in helper calls Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:44 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN Alex Bennée
` (28 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3a0f27c782..521b82d46e 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -488,6 +488,7 @@ typedef struct CPUARMState {
* Qn = regs[2n+1]:regs[2n]
* Dn = regs[2n]
* Sn = regs[2n] bits 31..0
+ * Hn = regs[2n] bits 15..0 for even n, and bits 31..16 for odd n
* This corresponds to the architecturally defined mapping between
* the two execution states, and means we do not need to explicitly
* map these registers when changing states.
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (3 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 04/30] target/arm/cpu.h: update comment for half-precision values Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:49 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal Alex Bennée
` (27 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat-specialize.h | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index de2c5d5702..c8282b8bf7 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -685,6 +685,49 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
}
#endif
+/*----------------------------------------------------------------------------
+| Takes two half-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status)
+{
+ flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN;
+ flag aIsLargerSignificand;
+ uint16_t av, bv;
+
+ aIsQuietNaN = float16_is_quiet_nan(a, status);
+ aIsSignalingNaN = float16_is_signaling_nan(a, status);
+ bIsQuietNaN = float16_is_quiet_nan(b, status);
+ bIsSignalingNaN = float16_is_signaling_nan(b, status);
+ av = float16_val(a);
+ bv = float16_val(b);
+
+ if (aIsSignalingNaN | bIsSignalingNaN) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ if (status->default_nan_mode) {
+ return float16_default_nan(status);
+ }
+
+ if ((uint16_t)(av << 1) < (uint16_t)(bv << 1)) {
+ aIsLargerSignificand = 0;
+ } else if ((uint16_t)(bv << 1) < (uint16_t)(av << 1)) {
+ aIsLargerSignificand = 1;
+ } else {
+ aIsLargerSignificand = (av < bv) ? 1 : 0;
+ }
+
+ if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
+ aIsLargerSignificand)) {
+ return float16_maybe_silence_nan(b, status);
+ } else {
+ return float16_maybe_silence_nan(a, status);
+ }
+}
+
/*----------------------------------------------------------------------------
| Takes two single-precision floating-point values `a' and `b', one of which
| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (4 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 05/30] softfloat: implement propagateFloat16NaN Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper Alex Bennée
` (26 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 15 +++++++++++++++
include/fpu/softfloat.h | 1 +
2 files changed, 16 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 433c5dad2d..3a4ab1355f 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3488,6 +3488,21 @@ static float16 roundAndPackFloat16(flag zSign, int zExp,
return packFloat16(zSign, zExp, zSig >> 13);
}
+/*----------------------------------------------------------------------------
+| If `a' is denormal and we are in flush-to-zero mode then set the
+| input-denormal exception and return zero. Otherwise just return the value.
+*----------------------------------------------------------------------------*/
+float16 float16_squash_input_denormal(float16 a, float_status *status)
+{
+ if (status->flush_inputs_to_zero) {
+ if (extractFloat16Exp(a) == 0 && extractFloat16Frac(a) != 0) {
+ float_raise(float_flag_input_denormal, status);
+ return make_float16(float16_val(a) & 0x8000);
+ }
+ }
+ return a;
+}
+
static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr,
uint32_t *zSigPtr)
{
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 0f96a0edd1..d5e99667b6 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -277,6 +277,7 @@ void float_raise(uint8_t flags, float_status *status);
| If `a' is denormal and we are in flush-to-zero mode then set the
| input-denormal exception and return zero. Otherwise just return the value.
*----------------------------------------------------------------------------*/
+float16 float16_squash_input_denormal(float16 a, float_status *status);
float32 float32_squash_input_denormal(float32 a, float_status *status);
float64 float64_squash_input_denormal(float64 a, float_status *status);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (5 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 06/30] fpu/softfloat: implement float16_squash_input_denormal Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:51 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns Alex Bennée
` (25 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
This will be required when expanding the MINMAX() macro for 16
bit/half-precision operations.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
include/fpu/softfloat.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index d5e99667b6..edf402d422 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -374,6 +374,13 @@ static inline int float16_is_zero_or_denormal(float16 a)
return (float16_val(a) & 0x7c00) == 0;
}
+static inline float16 float16_abs(float16 a)
+{
+ /* Note that abs does *not* handle NaN specially, nor does
+ * it flush denormal inputs to zero.
+ */
+ return make_float16(float16_val(a) & 0x7fff);
+}
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (6 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 07/30] fpu/softfloat: implement float16_abs helper Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 20:52 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX Alex Bennée
` (24 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
Expand the current helpers to include half-precision functions. The
includes having f16 version of the compare functions.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 2 ++
include/fpu/softfloat.h | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 3a4ab1355f..013b223947 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -7579,6 +7579,7 @@ int float ## s ## _compare_quiet(float ## s a, float ## s b, \
return float ## s ## _compare_internal(a, b, 1, status); \
}
+COMPARE(16, 0x1f)
COMPARE(32, 0xff)
COMPARE(64, 0x7ff)
@@ -7779,6 +7780,7 @@ float ## s float ## s ## _maxnummag(float ## s a, float ## s b, \
return float ## s ## _minmax(a, b, 0, 1, 1, status); \
}
+MINMAX(16)
MINMAX(32)
MINMAX(64)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index edf402d422..d89fdf7675 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -381,6 +381,17 @@ static inline float16 float16_abs(float16 a)
*/
return make_float16(float16_val(a) & 0x7fff);
}
+
+/* Expanded by the MINMAX macro in softfloat.c */
+int float16_compare(float16, float16, float_status *status);
+int float16_compare_quiet(float16, float16, float_status *status);
+float16 float16_min(float16, float16, float_status *status);
+float16 float16_max(float16, float16, float_status *status);
+float16 float16_minnum(float16, float16, float_status *status);
+float16 float16_maxnum(float16, float16, float_status *status);
+float16 float16_minnummag(float16, float16, float_status *status);
+float16 float16_maxnummag(float16, float16, float_status *status);
+
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (7 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 08/30] softfloat: add half-precision expansions for MINMAX fns Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-15 16:13 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
` (23 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
While a comparison between a QNaN and a number will return the number
it is not the same with a signaling NaN. In this case the SNaN will
"win" and after potentially raising an exception it will be quietened.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 013b223947..6ab4b39c09 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -7684,6 +7684,7 @@ int float128_compare_quiet(float128 a, float128 b, float_status *status)
* minnum() and maxnum() functions. These are similar to the min()
* and max() functions but if one of the arguments is a QNaN and
* the other is numerical then the numerical argument is returned.
+ * SNaNs will get quietened before being returned.
* minnum() and maxnum correspond to the IEEE 754-2008 minNum()
* and maxNum() operations. min() and max() are the typical min/max
* semantics provided by many CPUs which predate that specification.
@@ -7704,11 +7705,14 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \
if (float ## s ## _is_any_nan(a) || \
float ## s ## _is_any_nan(b)) { \
if (isieee) { \
- if (float ## s ## _is_quiet_nan(a, status) && \
+ if (float ## s ## _is_signaling_nan(a, status) || \
+ float ## s ## _is_signaling_nan(b, status)) { \
+ propagateFloat ## s ## NaN(a, b, status); \
+ } else if (float ## s ## _is_quiet_nan(a, status) && \
!float ## s ##_is_any_nan(b)) { \
return b; \
} else if (float ## s ## _is_quiet_nan(b, status) && \
- !float ## s ## _is_any_nan(a)) { \
+ !float ## s ## _is_any_nan(a)) { \
return a; \
} \
} \
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX Alex Bennée
@ 2017-10-15 16:13 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-15 16:13 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> - if (float ## s ## _is_quiet_nan(a, status) && \
> + if (float ## s ## _is_signaling_nan(a, status) || \
> + float ## s ## _is_signaling_nan(b, status)) { \
> + propagateFloat ## s ## NaN(a, b, status); \
Missing a return here?
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (8 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 09/30] softfloat: propagate signalling NaNs in MINMAX Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-15 16:14 ` Richard Henderson
2017-10-15 16:54 ` Peter Maydell
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
` (22 subsequent siblings)
32 siblings, 2 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
Mention the pseudo-code fragment from which this is based and correct
the spelling of signalling.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat-specialize.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index c8282b8bf7..2ccd4abe11 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -445,14 +445,14 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status)
#if defined(TARGET_ARM)
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
- flag aIsLargerSignificand)
+ flag aIsLargerSignificand)
{
- /* ARM mandated NaN propagation rules: take the first of:
- * 1. A if it is signaling
- * 2. B if it is signaling
+ /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take the first of:
+ * 1. A if it is signalling
+ * 2. B if it is signalling
* 3. A (quiet)
* 4. B (quiet)
- * A signaling NaN is always quietened before returning it.
+ * A signalling NaN is always quietened before returning it.
*/
if (aIsSNaN) {
return 0;
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
@ 2017-10-15 16:14 ` Richard Henderson
2017-10-15 16:54 ` Peter Maydell
1 sibling, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-15 16:14 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> Mention the pseudo-code fragment from which this is based and correct
> the spelling of signalling.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> fpu/softfloat-specialize.h | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
2017-10-15 16:14 ` Richard Henderson
@ 2017-10-15 16:54 ` Peter Maydell
1 sibling, 0 replies; 59+ messages in thread
From: Peter Maydell @ 2017-10-15 16:54 UTC (permalink / raw)
To: Alex Bennée
Cc: Richard Henderson, QEMU Developers, qemu-arm, Aurelien Jarno
On 13 October 2017 at 17:24, Alex Bennée <alex.bennee@linaro.org> wrote:
> Mention the pseudo-code fragment from which this is based and correct
> the spelling of signalling.
We are following the IEEE spec here, which spells it "signaling"
with one 'l', being American. (The ARM ARM also uses the one-l
spelling.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (9 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 10/30] softfloat: improve comments on ARM NaN propagation Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-16 20:10 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix Alex Bennée
` (21 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
--
v1
- dropped the advsimd_2a stuff
---
target/arm/helper-a64.c | 18 ++++++
target/arm/helper-a64.h | 4 ++
target/arm/translate-a64.c | 147 ++++++++++++++++++++++++++++-----------------
3 files changed, 115 insertions(+), 54 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index d9df82cff5..a0c20faabc 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -537,3 +537,21 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr,
return !success;
}
+
+/*
+ * AdvSIMD half-precision
+ */
+
+#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
+
+#define ADVSIMD_HALFOP(name) \
+float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return float16_ ## name(a, b, fpst); \
+}
+
+ADVSIMD_HALFOP(min)
+ADVSIMD_HALFOP(max)
+ADVSIMD_HALFOP(minnum)
+ADVSIMD_HALFOP(maxnum)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 6f9eaba533..b774431f1f 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -44,3 +44,7 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
+DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index a39b9d3633..1282d14c58 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5602,26 +5602,80 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resh);
}
-static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
- int opc, bool is_min, TCGv_ptr fpst)
-{
- /* Helper function for disas_simd_across_lanes: do a single precision
- * min/max operation on the specified two inputs,
- * and return the result in tcg_elt1.
- */
- if (opc == 0xc) {
- if (is_min) {
- gen_helper_vfp_minnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
- } else {
- gen_helper_vfp_maxnums(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
- }
+/*
+ * do_reduction_op helper
+ *
+ * This mirrors the Reduce() pseudocode in the ARM ARM. It is
+ * important for correct NaN propagation that we do these
+ * operations in exactly the order specified by the pseudocode.
+ *
+ * This is a recursive function, TCG temps should be freed by the
+ * calling function once it is done with the values.
+ */
+static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
+ int esize, int size, int vmap, TCGv_ptr fpst)
+{
+ if (esize == size) {
+ int element;
+ TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
+ TCGv_i32 tcg_elem;
+
+ /* We should have one register left here */
+ assert(ctpop8(vmap) == 1);
+ element = ctz32(vmap);
+ assert(element < 8);
+
+ tcg_elem = tcg_temp_new_i32();
+ read_vec_element_i32(s, tcg_elem, rn, element, msize);
+ return tcg_elem;
} else {
- assert(opc == 0xf);
- if (is_min) {
- gen_helper_vfp_mins(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
- } else {
- gen_helper_vfp_maxs(tcg_elt1, tcg_elt1, tcg_elt2, fpst);
+ int bits = size / 2;
+ int shift = ctpop8(vmap) / 2;
+ int vmap_lo = (vmap >> shift) & vmap;
+ int vmap_hi = (vmap & ~vmap_lo);
+ TCGv_i32 tcg_hi, tcg_lo, tcg_res;
+
+ tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
+ tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
+ tcg_res = tcg_temp_new_i32();
+
+ /* base fpopcode = 0x0c NMV, 0x0f V
+ 0x10 MIN, 0x00 MAX
+ 0x20 F32, 0x00 FP16
+ */
+ switch(fpopcode) {
+ case 0x0c: /* fmaxnmv half-precision */
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x0f: /* fmaxv half-precision */
+ gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x1c: /* fminnmv half-precision */
+ gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x1f: /* fminv half-precision */
+ gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x2c: /* fmaxnmv */
+ gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x2f: /* fmaxv */
+ gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x3c: /* fminnmv */
+ gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ case 0x3f: /* fminv */
+ gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
+ break;
+ default:
+ fprintf(stderr, "%s: fpopcode %x not handled\n", __func__, fpopcode);
+ break;
}
+
+ tcg_temp_free_i32(tcg_hi);
+ tcg_temp_free_i32(tcg_lo);
+ return tcg_res;
}
}
@@ -5663,16 +5717,21 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
break;
case 0xc: /* FMAXNMV, FMINNMV */
case 0xf: /* FMAXV, FMINV */
- if (!is_u || !is_q || extract32(size, 0, 1)) {
- unallocated_encoding(s);
- return;
- }
- /* Bit 1 of size field encodes min vs max, and actual size is always
- * 32 bits: adjust the size variable so following code can rely on it
+ /* Bit 1 of size field encodes min vs max and the actual size
+ * depends on the encoding of the U bit. If not set (and FP16
+ * enabled) then we do half-precision float instead of single
+ * precision.
*/
is_min = extract32(size, 1, 1);
is_fp = true;
- size = 2;
+ if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ size = 1;
+ } else if (!is_u || !is_q || extract32(size, 0, 1)) {
+ unallocated_encoding(s);
+ return;
+ } else {
+ size = 2;
+ }
break;
default:
unallocated_encoding(s);
@@ -5729,38 +5788,18 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
}
} else {
- /* Floating point ops which work on 32 bit (single) intermediates.
+ /* Floating point vector reduction ops which work across 32
+ * bit (single) or 16 bit (half-precision) intermediates.
* Note that correct NaN propagation requires that we do these
* operations in exactly the order specified by the pseudocode.
*/
- TCGv_i32 tcg_elt1 = tcg_temp_new_i32();
- TCGv_i32 tcg_elt2 = tcg_temp_new_i32();
- TCGv_i32 tcg_elt3 = tcg_temp_new_i32();
TCGv_ptr fpst = get_fpstatus_ptr();
-
- assert(esize == 32);
- assert(elements == 4);
-
- read_vec_element(s, tcg_elt, rn, 0, MO_32);
- tcg_gen_extrl_i64_i32(tcg_elt1, tcg_elt);
- read_vec_element(s, tcg_elt, rn, 1, MO_32);
- tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
-
- do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
-
- read_vec_element(s, tcg_elt, rn, 2, MO_32);
- tcg_gen_extrl_i64_i32(tcg_elt2, tcg_elt);
- read_vec_element(s, tcg_elt, rn, 3, MO_32);
- tcg_gen_extrl_i64_i32(tcg_elt3, tcg_elt);
-
- do_minmaxop(s, tcg_elt2, tcg_elt3, opcode, is_min, fpst);
-
- do_minmaxop(s, tcg_elt1, tcg_elt2, opcode, is_min, fpst);
-
- tcg_gen_extu_i32_i64(tcg_res, tcg_elt1);
- tcg_temp_free_i32(tcg_elt1);
- tcg_temp_free_i32(tcg_elt2);
- tcg_temp_free_i32(tcg_elt3);
+ int fpopcode = opcode | is_min << 4 | is_u << 5;
+ int vmap = (1 << elements) - 1;
+ TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
+ (is_q ? 128 : 64), vmap, fpst);
+ tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
+ tcg_temp_free_i32(tcg_res32);
tcg_temp_free_ptr(fpst);
}
@@ -5882,7 +5921,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
{
int size = ctz32(imm5);
int esize = 8 << size;
- int elements = (is_q ? 128 : 64)/esize;
+ int elements = (is_q ? 128 : 64) / esize;
int i = 0;
if (size > 3 || ((size == 3) && !is_q)) {
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
@ 2017-10-16 20:10 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-16 20:10 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +/*
> + * do_reduction_op helper
> + *
> + * This mirrors the Reduce() pseudocode in the ARM ARM. It is
> + * important for correct NaN propagation that we do these
> + * operations in exactly the order specified by the pseudocode.
> + *
> + * This is a recursive function, TCG temps should be freed by the
> + * calling function once it is done with the values.
> + */
> +static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
> + int esize, int size, int vmap, TCGv_ptr fpst)
> +{
> + if (esize == size) {
> + int element;
> + TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
> + TCGv_i32 tcg_elem;
> +
> + /* We should have one register left here */
> + assert(ctpop8(vmap) == 1);
I think you should match the ctpop to the size of vmap. It's true you only
need uint8_t at present, so maybe use that? At least it's self-consistent.
> + tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
> + tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
> + tcg_res = tcg_temp_new_i32();
You can re-use one of the two inputs for the output, fwiw.
> + /* Bit 1 of size field encodes min vs max and the actual size
> + * depends on the encoding of the U bit. If not set (and FP16
> + * enabled) then we do half-precision float instead of single
> + * precision.
> */
> is_min = extract32(size, 1, 1);
> is_fp = true;
> - size = 2;
> + if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> + size = 1;
You do still need to check size[0] == 0.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (10 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 11/30] target/arm: implement half-precision F(MIN|MAX)(V|NMV) Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-15 16:28 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode Alex Bennée
` (20 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
We do implement all the opcodes.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/translate-a64.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1282d14c58..50e53bf8b0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7177,8 +7177,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
/* Handle 64x64->64 opcodes which are shared between the scalar
* and vector 3-same groups. We cover every opcode where size == 3
* is valid in either the three-reg-same (integer, not pairwise)
- * or scalar-three-reg-same groups. (Some opcodes are not yet
- * implemented.)
+ * or scalar-three-reg-same groups.
*/
TCGCond cond;
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (11 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 12/30] target/arm/translate-a64.c: handle_3same_64 comment fix Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-16 20:16 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing Alex Bennée
` (19 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
This is the initial decode skeleton for the Advanced SIMD scalar
three same instruction group. The fprintf is purely to aid debugging
as the additional instructions are added. It will be removed once the
group is complete.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/translate-a64.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 50e53bf8b0..5e531b3ae4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9751,6 +9751,81 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
}
}
+/*
+ * Advanced SIMD three same (ARMv8.2 FP16 variants)
+ *
+ * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
+ * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
+ * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
+ *
+ * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
+ * (register), FACGE, FABD, FCMGT (register) and FACGT.
+ *
+ */
+static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
+{
+ int opcode, fpopcode;
+ int is_q, u, a, rm, rn, rd;
+ int datasize, elements;
+ int pass;
+ TCGv_ptr fpst;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (!fp_access_check(s)) {
+ return;
+ }
+
+ /* For these floating point ops, the U, a and opcode bits
+ * together indicate the operation.
+ */
+ opcode = extract32(insn, 11, 3);
+ u = extract32(insn, 29, 1);
+ a = extract32(insn, 23, 1);
+ is_q = extract32(insn, 30, 1);
+ rm = extract32(insn, 16, 5);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+
+ fpopcode = opcode | (a << 4) | (u << 5);
+ datasize = is_q ? 128 : 64;
+ elements = datasize / 16;
+
+ fpst = get_fpstatus_ptr();
+
+ for (pass = 0; pass < elements; pass++) {
+ TCGv_i32 tcg_op1 = tcg_temp_new_i32();
+ TCGv_i32 tcg_op2 = tcg_temp_new_i32();
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
+ read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
+
+ switch (fpopcode) {
+ default:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode);
+ g_assert_not_reached();
+ }
+
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+ tcg_temp_free_i32(tcg_res);
+ tcg_temp_free_i32(tcg_op1);
+ tcg_temp_free_i32(tcg_op2);
+ }
+
+ tcg_temp_free_ptr(fpst);
+
+ if (!is_q) {
+ /* non-quad vector op */
+ clear_vec_high(s, rd);
+ }
+
+}
+
static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
int size, int rn, int rd)
{
@@ -11159,6 +11234,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x4e280800, 0xff3e0c00, disas_crypto_aes },
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
+ { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (12 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 13/30] target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-15 18:02 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support Alex Bennée
` (18 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
Half-precision helpers for float16 maths. I didn't bother hand-coding
the count leading zeros as we could always fall-back to host-utils if
we needed to.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat-macros.h | 39 +++++++++++++++++++++++++++++++++++++++
fpu/softfloat.c | 21 +++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h
index 9cc6158cb4..73091a88a8 100644
--- a/fpu/softfloat-macros.h
+++ b/fpu/softfloat-macros.h
@@ -89,6 +89,31 @@ this code that are retained.
# define SOFTFLOAT_GNUC_PREREQ(maj, min) 0
#endif
+/*----------------------------------------------------------------------------
+| Shifts `a' right by the number of bits given in `count'. If any nonzero
+| bits are shifted off, they are ``jammed'' into the least significant bit of
+| the result by setting the least significant bit to 1. The value of `count'
+| can be arbitrarily large; in particular, if `count' is greater than 16, the
+| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
+| The result is stored in the location pointed to by `zPtr'.
+*----------------------------------------------------------------------------*/
+
+static inline void shift16RightJamming(uint16_t a, int count, uint16_t *zPtr)
+{
+ uint16_t z;
+
+ if ( count == 0 ) {
+ z = a;
+ }
+ else if ( count < 16 ) {
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
+ }
+ else {
+ z = ( a != 0 );
+ }
+ *zPtr = z;
+
+}
/*----------------------------------------------------------------------------
| Shifts `a' right by the number of bits given in `count'. If any nonzero
@@ -664,6 +689,20 @@ static uint32_t estimateSqrt32(int aExp, uint32_t a)
}
+/*----------------------------------------------------------------------------
+| Returns the number of leading 0 bits before the most-significant 1 bit of
+| `a'. If `a' is zero, 16 is returned.
+*----------------------------------------------------------------------------*/
+
+static int8_t countLeadingZeros16( uint16_t a )
+{
+ if (a) {
+ return __builtin_clz(a);
+ } else {
+ return 16;
+ }
+}
+
/*----------------------------------------------------------------------------
| Returns the number of leading 0 bits before the most-significant 1 bit of
| `a'. If `a' is zero, 32 is returned.
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 6ab4b39c09..cf7bf6d4f4 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3488,6 +3488,27 @@ static float16 roundAndPackFloat16(flag zSign, int zExp,
return packFloat16(zSign, zExp, zSig >> 13);
}
+/*----------------------------------------------------------------------------
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
+| and significand `zSig', and returns the proper single-precision floating-
+| point value corresponding to the abstract input. This routine is just like
+| `roundAndPackFloat32' except that `zSig' does not have to be normalized.
+| Bit 15 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''
+| floating-point exponent.
+*----------------------------------------------------------------------------*/
+
+static float16
+ normalizeRoundAndPackFloat16(flag zSign, int zExp, uint16_t zSig,
+ float_status *status)
+{
+ int8_t shiftCount;
+
+ shiftCount = countLeadingZeros16( zSig ) - 1;
+ return roundAndPackFloat16(zSign, zExp - shiftCount, zSig<<shiftCount,
+ true, status);
+
+}
+
/*----------------------------------------------------------------------------
| If `a' is denormal and we are in flush-to-zero mode then set the
| input-denormal exception and return zero. Otherwise just return the value.
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing Alex Bennée
@ 2017-10-15 18:02 ` Richard Henderson
2017-10-16 8:20 ` Alex Bennée
0 siblings, 1 reply; 59+ messages in thread
From: Richard Henderson @ 2017-10-15 18:02 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> Half-precision helpers for float16 maths. I didn't bother hand-coding
> the count leading zeros as we could always fall-back to host-utils if
> we needed to.
>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> fpu/softfloat-macros.h | 39 +++++++++++++++++++++++++++++++++++++++
> fpu/softfloat.c | 21 +++++++++++++++++++++
> 2 files changed, 60 insertions(+)
>
> diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h
> index 9cc6158cb4..73091a88a8 100644
> --- a/fpu/softfloat-macros.h
> +++ b/fpu/softfloat-macros.h
> @@ -89,6 +89,31 @@ this code that are retained.
> # define SOFTFLOAT_GNUC_PREREQ(maj, min) 0
> #endif
>
> +/*----------------------------------------------------------------------------
> +| Shifts `a' right by the number of bits given in `count'. If any nonzero
> +| bits are shifted off, they are ``jammed'' into the least significant bit of
> +| the result by setting the least significant bit to 1. The value of `count'
> +| can be arbitrarily large; in particular, if `count' is greater than 16, the
> +| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
> +| The result is stored in the location pointed to by `zPtr'.
> +*----------------------------------------------------------------------------*/
> +
> +static inline void shift16RightJamming(uint16_t a, int count, uint16_t *zPtr)
> +{
> + uint16_t z;
> +
> + if ( count == 0 ) {
> + z = a;
> + }
> + else if ( count < 16 ) {
> + z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
> + }
> + else {
> + z = ( a != 0 );
> + }
> + *zPtr = z;
> +
> +}
When are you going to use a SRJ of a uint16_t? Isn't most of your actual
arithmetic actually done on uint32_t?
> +/*----------------------------------------------------------------------------
> +| Returns the number of leading 0 bits before the most-significant 1 bit of
> +| `a'. If `a' is zero, 16 is returned.
> +*----------------------------------------------------------------------------*/
> +
> +static int8_t countLeadingZeros16( uint16_t a )
> +{
> + if (a) {
> + return __builtin_clz(a);
> + } else {
> + return 16;
> + }
> +}
__builtin_clz works on "int". You need to use clz32(a) - 16.
> +/*----------------------------------------------------------------------------
> +| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
> +| and significand `zSig', and returns the proper single-precision floating-
s/single/half/
> +| point value corresponding to the abstract input. This routine is just like
> +| `roundAndPackFloat32' except that `zSig' does not have to be normalized.
> +| Bit 15 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''
> +| floating-point exponent.
> +*----------------------------------------------------------------------------*/
> +
> +static float16
> + normalizeRoundAndPackFloat16(flag zSign, int zExp, uint16_t zSig,
> + float_status *status)
> +{
> + int8_t shiftCount;
> +
> + shiftCount = countLeadingZeros16( zSig ) - 1;
> + return roundAndPackFloat16(zSign, zExp - shiftCount, zSig<<shiftCount,
> + true, status);
Do I recall correctly that your lsb is between bits 7:6, like
roundAndPackFloat32? You've got 11 bits of sig. Plus 7 bits of extra equals
18 bits. Which doesn't fit in uint16_t.
So, the reason that roundAndPackFloat32 uses 7 bits is that 7 + 24 == 31.
We can either use a split at (15 - 11 =) 4 bits, and still fit in a uint16_t,
or we can drop uint16_t and admit that the compiler is going to promote to int,
or uint32_t, anyway. If we do that, we have options of a split between 4 and
(31 - 11 =) 20 bits.
We talked this week re fp->int conversion, it did seem Really Useful when we
noted that sig << exp is representable in a uint32_t. Which does suggest a
choice at or below (32 - 11 - 14 =) 7.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing
2017-10-15 18:02 ` Richard Henderson
@ 2017-10-16 8:20 ` Alex Bennée
0 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-16 8:20 UTC (permalink / raw)
To: Richard Henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
Richard Henderson <richard.henderson@linaro.org> writes:
> On 10/13/2017 09:24 AM, Alex Bennée wrote:
>> Half-precision helpers for float16 maths. I didn't bother hand-coding
>> the count leading zeros as we could always fall-back to host-utils if
>> we needed to.
>>
>> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> fpu/softfloat-macros.h | 39 +++++++++++++++++++++++++++++++++++++++
>> fpu/softfloat.c | 21 +++++++++++++++++++++
>> 2 files changed, 60 insertions(+)
>>
>> diff --git a/fpu/softfloat-macros.h b/fpu/softfloat-macros.h
>> index 9cc6158cb4..73091a88a8 100644
>> --- a/fpu/softfloat-macros.h
>> +++ b/fpu/softfloat-macros.h
>> @@ -89,6 +89,31 @@ this code that are retained.
>> # define SOFTFLOAT_GNUC_PREREQ(maj, min) 0
>> #endif
>>
>> +/*----------------------------------------------------------------------------
>> +| Shifts `a' right by the number of bits given in `count'. If any nonzero
>> +| bits are shifted off, they are ``jammed'' into the least significant bit of
>> +| the result by setting the least significant bit to 1. The value of `count'
>> +| can be arbitrarily large; in particular, if `count' is greater than 16, the
>> +| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
>> +| The result is stored in the location pointed to by `zPtr'.
>> +*----------------------------------------------------------------------------*/
>> +
>> +static inline void shift16RightJamming(uint16_t a, int count, uint16_t *zPtr)
>> +{
>> + uint16_t z;
>> +
>> + if ( count == 0 ) {
>> + z = a;
>> + }
>> + else if ( count < 16 ) {
>> + z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
>> + }
>> + else {
>> + z = ( a != 0 );
>> + }
>> + *zPtr = z;
>> +
>> +}
>
> When are you going to use a SRJ of a uint16_t? Isn't most of your actual
> arithmetic actually done on uint32_t?
The add/sub stuff currently uses it. Arguably it could do what it needs
with 32 bit as well but the spare exponent bits are enough for operating
on the significand. That said I'm fairly sure it all ends up 32 bit in
the generated code.
>
>> +/*----------------------------------------------------------------------------
>> +| Returns the number of leading 0 bits before the most-significant 1 bit of
>> +| `a'. If `a' is zero, 16 is returned.
>> +*----------------------------------------------------------------------------*/
>> +
>> +static int8_t countLeadingZeros16( uint16_t a )
>> +{
>> + if (a) {
>> + return __builtin_clz(a);
>> + } else {
>> + return 16;
>> + }
>> +}
>
> __builtin_clz works on "int". You need to use clz32(a) - 16.
Ahh my mistake - I'd assumed it had the same smarts as the gcc atomics.
Maybe I should just use our utils functions afterall.
>
>> +/*----------------------------------------------------------------------------
>> +| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
>> +| and significand `zSig', and returns the proper single-precision floating-
>
> s/single/half/
>
>> +| point value corresponding to the abstract input. This routine is just like
>> +| `roundAndPackFloat32' except that `zSig' does not have to be normalized.
>> +| Bit 15 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''
>> +| floating-point exponent.
>> +*----------------------------------------------------------------------------*/
>> +
>> +static float16
>> + normalizeRoundAndPackFloat16(flag zSign, int zExp, uint16_t zSig,
>> + float_status *status)
>> +{
>> + int8_t shiftCount;
>> +
>> + shiftCount = countLeadingZeros16( zSig ) - 1;
>> + return roundAndPackFloat16(zSign, zExp - shiftCount, zSig<<shiftCount,
>> + true, status);
>
> Do I recall correctly that your lsb is between bits 7:6, like
> roundAndPackFloat32? You've got 11 bits of sig. Plus 7 bits of extra equals
> 18 bits. Which doesn't fit in uint16_t.
No it takes a 32 bit sig in and deals with it internally.
>
> So, the reason that roundAndPackFloat32 uses 7 bits is that 7 + 24 == 31.
>
> We can either use a split at (15 - 11 =) 4 bits, and still fit in a uint16_t,
> or we can drop uint16_t and admit that the compiler is going to promote to int,
> or uint32_t, anyway. If we do that, we have options of a split between 4 and
> (31 - 11 =) 20 bits.
>
> We talked this week re fp->int conversion, it did seem Really Useful when we
> noted that sig << exp is representable in a uint32_t. Which does suggest a
> choice at or below (32 - 11 - 14 =) 7.
>
>
> r~
--
Alex Bennée
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (13 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 14/30] softfloat: 16 bit helpers for shr, clz and rounding and packing Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-16 22:01 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) Alex Bennée
` (17 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
Rather than following the SoftFloat3 implementation I've used the same
basic template as the rest of our softfloat code. One minor difference
is the 32bit intermediates end up with the binary point in the same
place as the 32 bit version so the change isn't totally mechanical.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 352 ++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 6 +
2 files changed, 358 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index cf7bf6d4f4..ff967f5525 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3532,6 +3532,358 @@ static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr,
*zExpPtr = 1 - shiftCount;
}
+/*----------------------------------------------------------------------------
+| Returns the result of adding the absolute values of the half-precision
+| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated
+| before being returned. `zSign' is ignored if the result is a NaN.
+| The addition is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+static float16 addFloat16Sigs(float16 a, float16 b, flag zSign,
+ float_status *status)
+{
+ int aExp, bExp, zExp;
+ uint16_t aSig, bSig, zSig;
+ int expDiff;
+
+ aSig = extractFloat16Frac( a );
+ aExp = extractFloat16Exp( a );
+ bSig = extractFloat16Frac( b );
+ bExp = extractFloat16Exp( b );
+ expDiff = aExp - bExp;
+ aSig <<= 3;
+ bSig <<= 3;
+ if ( 0 < expDiff ) {
+ if ( aExp == 0x1F ) {
+ if (aSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ return a;
+ }
+ if ( bExp == 0 ) {
+ --expDiff;
+ }
+ else {
+ bSig |= 0x20000000;
+ }
+ shift16RightJamming( bSig, expDiff, &bSig );
+ zExp = aExp;
+ }
+ else if ( expDiff < 0 ) {
+ if ( bExp == 0x1F ) {
+ if (bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ return packFloat16( zSign, 0x1F, 0 );
+ }
+ if ( aExp == 0 ) {
+ ++expDiff;
+ }
+ else {
+ aSig |= 0x0400;
+ }
+ shift16RightJamming( aSig, - expDiff, &aSig );
+ zExp = bExp;
+ }
+ else {
+ if ( aExp == 0x1F ) {
+ if (aSig | bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ return a;
+ }
+ if ( aExp == 0 ) {
+ if (status->flush_to_zero) {
+ if (aSig | bSig) {
+ float_raise(float_flag_output_denormal, status);
+ }
+ return packFloat16(zSign, 0, 0);
+ }
+ return packFloat16( zSign, 0, ( aSig + bSig )>>3 );
+ }
+ zSig = 0x0400 + aSig + bSig;
+ zExp = aExp;
+ goto roundAndPack;
+ }
+ aSig |= 0x0400;
+ zSig = ( aSig + bSig )<<1;
+ --zExp;
+ if ( (int16_t) zSig < 0 ) {
+ zSig = aSig + bSig;
+ ++zExp;
+ }
+ roundAndPack:
+ return roundAndPackFloat16(zSign, zExp, zSig, true, status);
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of subtracting the absolute values of the half-
+| precision floating-point values `a' and `b'. If `zSign' is 1, the
+| difference is negated before being returned. `zSign' is ignored if the
+| result is a NaN. The subtraction is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+static float16 subFloat16Sigs(float16 a, float16 b, flag zSign,
+ float_status *status)
+{
+ int aExp, bExp, zExp;
+ uint16_t aSig, bSig, zSig;
+ int expDiff;
+
+ aSig = extractFloat16Frac( a );
+ aExp = extractFloat16Exp( a );
+ bSig = extractFloat16Frac( b );
+ bExp = extractFloat16Exp( b );
+ expDiff = aExp - bExp;
+ aSig <<= 7;
+ bSig <<= 7;
+ if ( 0 < expDiff ) goto aExpBigger;
+ if ( expDiff < 0 ) goto bExpBigger;
+ if ( aExp == 0xFF ) {
+ if (aSig | bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ if ( aExp == 0 ) {
+ aExp = 1;
+ bExp = 1;
+ }
+ if ( bSig < aSig ) goto aBigger;
+ if ( aSig < bSig ) goto bBigger;
+ return packFloat16(status->float_rounding_mode == float_round_down, 0, 0);
+ bExpBigger:
+ if ( bExp == 0xFF ) {
+ if (bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ return packFloat16( zSign ^ 1, 0xFF, 0 );
+ }
+ if ( aExp == 0 ) {
+ ++expDiff;
+ }
+ else {
+ aSig |= 0x40000000;
+ }
+ shift16RightJamming( aSig, - expDiff, &aSig );
+ bSig |= 0x40000000;
+ bBigger:
+ zSig = bSig - aSig;
+ zExp = bExp;
+ zSign ^= 1;
+ goto normalizeRoundAndPack;
+ aExpBigger:
+ if ( aExp == 0xFF ) {
+ if (aSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ return a;
+ }
+ if ( bExp == 0 ) {
+ --expDiff;
+ }
+ else {
+ bSig |= 0x40000000;
+ }
+ shift16RightJamming( bSig, expDiff, &bSig );
+ aSig |= 0x40000000;
+ aBigger:
+ zSig = aSig - bSig;
+ zExp = aExp;
+ normalizeRoundAndPack:
+ --zExp;
+ return normalizeRoundAndPackFloat16(zSign, zExp, zSig, status);
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of adding the half-precision floating-point values `a'
+| and `b'. The operation is performed according to the IEC/IEEE Standard for
+| Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+float16 float16_add(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ if ( aSign == bSign ) {
+ return addFloat16Sigs(a, b, aSign, status);
+ }
+ else {
+ return subFloat16Sigs(a, b, aSign, status);
+ }
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of subtracting the half-precision floating-point values
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+float16 float16_sub(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ if ( aSign == bSign ) {
+ return subFloat16Sigs(a, b, aSign, status);
+ }
+ else {
+ return addFloat16Sigs(a, b, aSign, status);
+ }
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of multiplying the half-precision floating-point values
+| `a' and `b'. The operation is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+float16 float16_mul(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign, zSign;
+ int aExp, bExp, zExp;
+ uint32_t aSig, bSig;
+ uint32_t zSig32; /* no zSig as zSig32 passed into rp&f */
+
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ aSig = extractFloat16Frac( a );
+ aExp = extractFloat16Exp( a );
+ aSign = extractFloat16Sign( a );
+ bSig = extractFloat16Frac( b );
+ bExp = extractFloat16Exp( b );
+ bSign = extractFloat16Sign( b );
+ zSign = aSign ^ bSign;
+ if ( aExp == 0x1F ) {
+ if ( aSig || ( ( bExp == 0x1F ) && bSig ) ) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ if ( ( bExp | bSig ) == 0 ) {
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ return packFloat16( zSign, 0x1F, 0 );
+ }
+ if ( bExp == 0x1F ) {
+ if (bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ if ( ( aExp | aSig ) == 0 ) {
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ return packFloat16( zSign, 0x1F, 0 );
+ }
+ if ( aExp == 0 ) {
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
+ normalizeFloat16Subnormal( aSig, &aExp, &aSig );
+ }
+ if ( bExp == 0 ) {
+ if ( bSig == 0 ) return packFloat16( zSign, 0, 0 );
+ normalizeFloat16Subnormal( bSig, &bExp, &bSig );
+ }
+ zExp = aExp + bExp - 0xF;
+ /* Add implicit bit */
+ aSig = ( aSig | 0x0400 )<<4;
+ bSig = ( bSig | 0x0400 )<<5;
+ /* Max (format " => 0x%x" (* (lsh #x400 4) (lsh #x400 5))) => 0x20000000
+ * So shift so binary point from 30/29 to 23/22
+ */
+ shift32RightJamming( ( (uint32_t) aSig ) * bSig, 7, &zSig32 );
+ /* At this point the significand is at the same point as
+ * float32_mul, so we can do the same test */
+ if ( 0 <= (int32_t) ( zSig32<<1 ) ) {
+ zSig32 <<= 1;
+ --zExp;
+ }
+ return roundAndPackFloat16(zSign, zExp, zSig32, true, status);
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of dividing the half-precision floating-point value `a'
+| by the corresponding value `b'. The operation is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+float16 float16_div(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign, zSign;
+ int aExp, bExp, zExp;
+ uint32_t aSig, bSig, zSig;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ aSig = extractFloat16Frac( a );
+ aExp = extractFloat16Exp( a );
+ aSign = extractFloat16Sign( a );
+ bSig = extractFloat16Frac( b );
+ bExp = extractFloat16Exp( b );
+ bSign = extractFloat16Sign( b );
+ zSign = aSign ^ bSign;
+ if ( aExp == 0xFF ) {
+ if (aSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ if ( bExp == 0xFF ) {
+ if (bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ return packFloat16( zSign, 0xFF, 0 );
+ }
+ if ( bExp == 0xFF ) {
+ if (bSig) {
+ return propagateFloat16NaN(a, b, status);
+ }
+ return packFloat16( zSign, 0, 0 );
+ }
+ if ( bExp == 0 ) {
+ if ( bSig == 0 ) {
+ if ( ( aExp | aSig ) == 0 ) {
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ float_raise(float_flag_divbyzero, status);
+ return packFloat16( zSign, 0xFF, 0 );
+ }
+ normalizeFloat16Subnormal( bSig, &bExp, &bSig );
+ }
+ if ( aExp == 0 ) {
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
+ normalizeFloat16Subnormal( aSig, &aExp, &aSig );
+ }
+ zExp = aExp - bExp + 0x7D;
+ aSig = ( aSig | 0x00800000 )<<7;
+ bSig = ( bSig | 0x00800000 )<<8;
+ if ( bSig <= ( aSig + aSig ) ) {
+ aSig >>= 1;
+ ++zExp;
+ }
+ zSig = ( ( (uint64_t) aSig )<<16 ) / bSig;
+ if ( ( zSig & 0x3F ) == 0 ) {
+ zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 );
+ }
+ return roundAndPackFloat16(zSign, zExp, zSig, true, status);
+
+}
+
/* Half precision floats come in two formats: standard IEEE and "ARM" format.
The latter gains extra exponent range by omitting the NaN/Inf encodings. */
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index d89fdf7675..f1d79b6d03 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -345,6 +345,12 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
/*----------------------------------------------------------------------------
| Software half-precision operations.
*----------------------------------------------------------------------------*/
+
+float16 float16_add(float16, float16, float_status *status);
+float16 float16_sub(float16, float16, float_status *status);
+float16 float16_mul(float16, float16, float_status *status);
+float16 float16_div(float16, float16, float_status *status);
+
int float16_is_quiet_nan(float16, float_status *status);
int float16_is_signaling_nan(float16, float_status *status);
float16 float16_maybe_silence_nan(float16, float_status *status);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support Alex Bennée
@ 2017-10-16 22:01 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-16 22:01 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +static float16 addFloat16Sigs(float16 a, float16 b, flag zSign,
> + float_status *status)
> +{
> + int aExp, bExp, zExp;
> + uint16_t aSig, bSig, zSig;
> + int expDiff;
> +
> + aSig = extractFloat16Frac( a );
> + aExp = extractFloat16Exp( a );
> + bSig = extractFloat16Frac( b );
> + bExp = extractFloat16Exp( b );
> + expDiff = aExp - bExp;
> + aSig <<= 3;
> + bSig <<= 3;
> + if ( 0 < expDiff ) {
> + if ( aExp == 0x1F ) {
> + if (aSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + return a;
> + }
> + if ( bExp == 0 ) {
> + --expDiff;
> + }
> + else {
> + bSig |= 0x20000000;
> + }
This number is wrong. The 32-bit number is the implicit bit (0x800000) << 6
(which is the shift applied there). Here it should be 0x400 << 3. And it
probably should be written that way for clarity.
> + else if ( expDiff < 0 ) {
> + if ( bExp == 0x1F ) {
> + if (bSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + return packFloat16( zSign, 0x1F, 0 );
> + }
> + if ( aExp == 0 ) {
> + ++expDiff;
> + }
> + else {
> + aSig |= 0x0400;
This number is wrong because you didn't apply the << 3.
> + if ( aExp == 0 ) {
> + if (status->flush_to_zero) {
> + if (aSig | bSig) {
> + float_raise(float_flag_output_denormal, status);
> + }
> + return packFloat16(zSign, 0, 0);
> + }
> + return packFloat16( zSign, 0, ( aSig + bSig )>>3 );
> + }
> + zSig = 0x0400 + aSig + bSig;
> + zExp = aExp;
> + goto roundAndPack;
> + }
> + aSig |= 0x0400;
Needs << 3.
> + zSig = ( aSig + bSig )<<1;
> + --zExp;
> + if ( (int16_t) zSig < 0 ) {
> + zSig = aSig + bSig;
> + ++zExp;
> + }
As a side-note, I really wish the existing code didn't try to half-optimize
this. Both aSig and bSig really should have their implicit bits added. Of
course, that affects this weird zExp dance as well.
> + int aExp, bExp, zExp;
> + uint16_t aSig, bSig, zSig;
> + int expDiff;
> +
> + aSig = extractFloat16Frac( a );
> + aExp = extractFloat16Exp( a );
> + bSig = extractFloat16Frac( b );
> + bExp = extractFloat16Exp( b );
> + expDiff = aExp - bExp;
> + aSig <<= 7;
> + bSig <<= 7;
You've just lost one frac bit off the left of the uint16_t.
You cannot add that many bias bits and still use that as an intermediate data
type. You can only shift by 3, as you did for add. Or, widen to uint32_t.
> + if ( 0 < expDiff ) goto aExpBigger;
> + if ( expDiff < 0 ) goto bExpBigger;
> + if ( aExp == 0xFF ) {
> + if (aSig | bSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + if ( aExp == 0 ) {
> + aExp = 1;
> + bExp = 1;
> + }
> + if ( bSig < aSig ) goto aBigger;
> + if ( aSig < bSig ) goto bBigger;
> + return packFloat16(status->float_rounding_mode == float_round_down, 0, 0);
> + bExpBigger:
> + if ( bExp == 0xFF ) {
> + if (bSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + return packFloat16( zSign ^ 1, 0xFF, 0 );
> + }
> + if ( aExp == 0 ) {
> + ++expDiff;
> + }
> + else {
> + aSig |= 0x40000000;
> + }
> + shift16RightJamming( aSig, - expDiff, &aSig );
> + bSig |= 0x40000000;
These should be 0x400 << shl. It should be obvious that 0x40000000 doesn't fit
in uint16_t.
> + bBigger:
> + zSig = bSig - aSig;
> + zExp = bExp;
> + zSign ^= 1;
> + goto normalizeRoundAndPack;
> + aExpBigger:
> + if ( aExp == 0xFF ) {
> + if (aSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + return a;
> + }
> + if ( bExp == 0 ) {
> + --expDiff;
> + }
> + else {
> + bSig |= 0x40000000;
> + }
> + shift16RightJamming( bSig, expDiff, &bSig );
> + aSig |= 0x40000000;
Likewise.
> + aBigger:
> + zSig = aSig - bSig;
> + zExp = aExp;
> + normalizeRoundAndPack:
> + --zExp;
> + return normalizeRoundAndPackFloat16(zSign, zExp, zSig, status);
This reinforces my point about not using uint16_t
> +float16 float16_mul(float16 a, float16 b, float_status *status)
...
> + if ( aExp == 0 ) {
> + if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
> + normalizeFloat16Subnormal( aSig, &aExp, &aSig );
> + }
> + if ( bExp == 0 ) {
> + if ( bSig == 0 ) return packFloat16( zSign, 0, 0 );
> + normalizeFloat16Subnormal( bSig, &bExp, &bSig );
> + }
> + zExp = aExp + bExp - 0xF;
> + /* Add implicit bit */
> + aSig = ( aSig | 0x0400 )<<4;
> + bSig = ( bSig | 0x0400 )<<5;
The implicit bit shouldn't be added for denormals. It *probably* doesn't
matter since the normalization step should be setting the same bit, but it's
certainly less than clear.
Is there a particular reason to add the 9 bits of shifting? I thought we
demonstrated to your satisfaction that it wasn't required.
> + /* Max (format " => 0x%x" (* (lsh #x400 4) (lsh #x400 5))) => 0x20000000
> + * So shift so binary point from 30/29 to 23/22
> + */
That's the minimum, not maximum. Maximum would be
0x7ff<<4 * 0x7ff<<5 => 0x7fe00200
I am totally unclear why the binary point should be at 23/22. That doesn't
seem to match up with the shifts you've used for either addition or
subtraction. Both of which were different, btw...
> + shift32RightJamming( ( (uint32_t) aSig ) * bSig, 7, &zSig32 );
> + /* At this point the significand is at the same point as
> + * float32_mul, so we can do the same test */
> + if ( 0 <= (int32_t) ( zSig32<<1 ) ) {
> + zSig32 <<= 1;
> + --zExp;
> + }
These two are definitely in the wrong order. You can certainly normalize
0x20000000 to 0x40000000 via that IF, but not if you've already right-shifted
by 7 bits.
> +/*----------------------------------------------------------------------------
> +| Returns the result of dividing the half-precision floating-point value `a'
> +| by the corresponding value `b'. The operation is performed according to the
> +| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
> +*----------------------------------------------------------------------------*/
> +
> +float16 float16_div(float16 a, float16 b, float_status *status)
> +{
> + flag aSign, bSign, zSign;
> + int aExp, bExp, zExp;
> + uint32_t aSig, bSig, zSig;
> + a = float16_squash_input_denormal(a, status);
> + b = float16_squash_input_denormal(b, status);
> +
> + aSig = extractFloat16Frac( a );
> + aExp = extractFloat16Exp( a );
> + aSign = extractFloat16Sign( a );
> + bSig = extractFloat16Frac( b );
> + bExp = extractFloat16Exp( b );
> + bSign = extractFloat16Sign( b );
> + zSign = aSign ^ bSign;
> + if ( aExp == 0xFF ) {
> + if (aSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + if ( bExp == 0xFF ) {
> + if (bSig) {
> + return propagateFloat16NaN(a, b, status);
> + }
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + return packFloat16( zSign, 0xFF, 0 );
All these 0xff should be 0x1f for float16.
> + if ( bExp == 0 ) {
> + if ( bSig == 0 ) {
> + if ( ( aExp | aSig ) == 0 ) {
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + float_raise(float_flag_divbyzero, status);
> + return packFloat16( zSign, 0xFF, 0 );
> + }
> + normalizeFloat16Subnormal( bSig, &bExp, &bSig );
> + }
> + if ( aExp == 0 ) {
> + if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
> + normalizeFloat16Subnormal( aSig, &aExp, &aSig );
> + }
> + zExp = aExp - bExp + 0x7D;
The exponent bias correction is wrong.
> + aSig = ( aSig | 0x00800000 )<<7;
> + bSig = ( bSig | 0x00800000 )<<8;
Again, the implicit bit isn't correct, and probably should be explicitly set
for subnormals.
> + if ( bSig <= ( aSig + aSig ) ) {
> + aSig >>= 1;
> + ++zExp;
> + }
> + zSig = ( ( (uint64_t) aSig )<<16 ) / bSig;
If you hadn't already shifted by 7 & 8, you wouldn't need to make this a
uint64_t for division. Indeed, those shift were chosen for float32 so that the
float32 fraction was at the top of the uint32_t. We then normalize the
operands such that result must be fractional.
> + if ( ( zSig & 0x3F ) == 0 ) {
> + zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 );
> + }
Well, the 0x3f isn't right. I think ideally we'd use div and mod
unconditionally and let the compiler dtrt, e.g.
aSig <<= 16;
q = aSig / bSig;
r = aSig % bSig;
zSig = q | (r != 0);
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (14 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 15/30] softfloat: half-precision add/sub/mul/div support Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-16 22:08 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX Alex Bennée
` (16 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 4 ++++
target/arm/helper-a64.h | 4 ++++
target/arm/translate-a64.c | 12 +++++++++++-
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index a0c20faabc..8ef15c4c45 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -551,6 +551,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
return float16_ ## name(a, b, fpst); \
}
+ADVSIMD_HALFOP(add)
+ADVSIMD_HALFOP(sub)
+ADVSIMD_HALFOP(mul)
+ADVSIMD_HALFOP(div)
ADVSIMD_HALFOP(min)
ADVSIMD_HALFOP(max)
ADVSIMD_HALFOP(minnum)
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index b774431f1f..a4ce87970e 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -44,6 +44,10 @@ DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32)
DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64)
+DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 5e531b3ae4..f687bab214 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9806,8 +9806,18 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
switch (fpopcode) {
+ case 0x2: /* FADD */
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x23: /* FMUL */
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x27: /* FDIV */
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
default:
- fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode);
+ fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
+ __func__, insn, fpopcode, s->pc);
g_assert_not_reached();
}
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) Alex Bennée
@ 2017-10-16 22:08 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-16 22:08 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
> +DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
> +DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
> +DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)
...
> switch (fpopcode) {
> + case 0x2: /* FADD */
> + gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
> + break;
Forgot FSUB with case 0x12?
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (15 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 16/30] target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub) Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-16 22:24 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton Alex Bennée
` (15 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 18 ++++++++++++++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 45 +++++++++++++++++++++++++++++++++++----------
3 files changed, 54 insertions(+), 10 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 8ef15c4c45..dd26675d5c 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -559,3 +559,21 @@ ADVSIMD_HALFOP(min)
ADVSIMD_HALFOP(max)
ADVSIMD_HALFOP(minnum)
ADVSIMD_HALFOP(maxnum)
+
+/* Data processing - scalar floating-point and advanced SIMD */
+
+float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+
+ a = float16_squash_input_denormal(a, fpst);
+ b = float16_squash_input_denormal(b, fpst);
+
+ if ((float16_is_zero(a) && float16_is_infinity(b)) ||
+ (float16_is_infinity(a) && float16_is_zero(b))) {
+ /* 2.0 with the sign bit set to sign(A) XOR sign(B) */
+ return make_float16((1U << 14) |
+ ((float16_val(a) ^ float16_val(b)) & (1U << 15)));
+ }
+ return float16_mul(a, b, fpst);
+}
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index a4ce87970e..0f97eb607f 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -52,3 +52,4 @@ DEF_HELPER_3(advsimd_maxh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
+DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f687bab214..d12106695f 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10648,7 +10648,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
/* fall through */
case 0x9: /* FMUL, FMULX */
- if (!extract32(size, 1, 1)) {
+ if (!extract32(size, 1, 1) && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
}
@@ -10660,18 +10660,30 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
if (is_fp) {
- /* low bit of size indicates single/double */
- size = extract32(size, 0, 1) ? 3 : 2;
- if (size == 2) {
+ /* convert insn encoded size to TCGMemOp size */
+ switch (size) {
+ case 0: /* half-precision */
+ size = MO_16;
+ index = h << 2 | l << 1 | m;
+ break;
+ case 2: /* single precision */
+ size = MO_32;
index = h << 1 | l;
- } else {
+ rm |= (m << 4);
+ break;
+ case 3: /* double precision */
+ size = MO_64;
if (l || !is_q) {
unallocated_encoding(s);
return;
}
index = h;
+ rm |= (m << 4);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
}
- rm |= (m << 4);
} else {
switch (size) {
case 1:
@@ -10805,10 +10817,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
break;
case 0x9: /* FMUL, FMULX */
- if (u) {
- gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
- } else {
- gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
+ switch (size) {
+ case 1:
+ if (u) {
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, fpst);
+ } else {
+ g_assert_not_reached();
+ }
+ break;
+ case 2:
+ if (u) {
+ gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
+ } else {
+ gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
+ }
+ break;
+ default:
+ g_assert_not_reached();
}
break;
case 0xc: /* SQDMULH */
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX Alex Bennée
@ 2017-10-16 22:24 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-16 22:24 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -10648,7 +10648,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
> }
> /* fall through */
> case 0x9: /* FMUL, FMULX */
> - if (!extract32(size, 1, 1)) {
> + if (!extract32(size, 1, 1) && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
> unallocated_encoding(s);
> return;
> }
This isn't quite right --
00 = fp16
10 = fp32
11 = fp64
You still need to diagnose 01.
> @@ -10805,10 +10817,23 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
> gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
> break;
> case 0x9: /* FMUL, FMULX */
> - if (u) {
> - gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
> - } else {
> - gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
> + switch (size) {
> + case 1:
MO_* here, since you converted to them above.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (16 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 17/30] target/arm/translate-a64.c: add FP16 FMULX Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc Alex Bennée
` (14 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
This is just the decode skeleton which will be filled out by later
patches.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/translate-a64.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d12106695f..11990daff4 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10568,6 +10568,40 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
}
}
+/* AdvSIMD two reg misc FP16
+ * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
+ * +---+---+---+-----------+---+-------------+--------+-----+------+------+
+ * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
+ * +---+---+---+-----------+---+-------------+--------+-----+------+------+
+ * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00
+ * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800
+ * Half-precision variants of two-reg misc.
+ */
+static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
+{
+ int fpop, opcode, a;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ if (!fp_access_check(s)) {
+ return;
+ }
+
+ opcode = extract32(insn, 12, 4);
+ a = extract32(insn, 23, 1);
+ fpop = deposit32(opcode, 5, 1, a);
+
+ switch (fpop) {
+ default:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
+ g_assert_not_reached();
+ }
+
+}
+
/* AdvSIMD scalar x indexed element
* 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
* +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
@@ -11270,6 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
+ { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (17 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 18/30] target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-16 23:47 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions Alex Bennée
` (13 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
While the group encoding declares bit 28 a zero it is set for
FCMGT (zero)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/translate-a64.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 11990daff4..7792cea9f5 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10571,10 +10571,10 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
/* AdvSIMD two reg misc FP16
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+---+-------------+--------+-----+------+------+
- * | 0 | 1 | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
+ * | 0 | Q | U | 1 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
* +---+---+---+-----------+---+-------------+--------+-----+------+------+
- * mask: 1101 1111 0111 1110 0000 1100 0000 0000 0xdf7e 0c00
- * val: 0101 1110 0111 1000 0000 1000 0000 0000 0x5e78 0800
+ * mask: 1001 1111 0111 1110 0000 1100 0000 0000 0x9f7e 0c00
+ * val: 0001 1110 0111 1000 0000 1000 0000 0000 0x1e78 0800
* Half-precision variants of two-reg misc.
*/
static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
@@ -11304,7 +11304,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
{ 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
{ 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
- { 0x5e780800, 0xdf7e0c00, disas_simd_two_reg_misc_fp16 },
+ { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
{ 0x00000000, 0x00000000, NULL }
};
@@ -11318,6 +11318,8 @@ static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
if (fn) {
fn(s, insn);
} else {
+ fprintf(stderr, "%s: failed to find %#4x @ %#" PRIx64 "\n",
+ __func__, insn, s->pc);
unallocated_encoding(s);
}
}
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (18 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 19/30] Fix mask for AdvancedSIMD 2 reg misc Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-17 0:06 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) Alex Bennée
` (12 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
This is mostly a mechanical conversion of the float32 variants of the
same name with some judicious search/replace and some constants
changed.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 216 ++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 8 ++
2 files changed, 224 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index ff967f5525..fdb2999c41 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3884,6 +3884,222 @@ float16 float16_div(float16 a, float16 b, float_status *status)
}
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. Otherwise, the comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq(float16 a, float16 b, float_status *status)
+{
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ av = float16_val(a);
+ bv = float16_val(b);
+ return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| or equal to the corresponding value `b', and 0 otherwise. The invalid
+| exception is raised if either operand is a NaN. The comparison is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. The invalid exception is
+| raised if either operand is a NaN. The comparison is performed according
+| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. The invalid exception is raised if either
+| operand is a NaN. The comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ float_raise(float_flag_invalid, status);
+ return 1;
+ }
+ return 0;
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is equal to
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. The comparison is performed according to the IEC/IEEE Standard
+| for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_eq_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ return ( float16_val(a) == float16_val(b) ) ||
+ ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 );
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than or
+| equal to the corresponding value `b', and 0 otherwise. Quiet NaNs do not
+| cause an exception. Otherwise, the comparison is performed according to the
+| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_le_quiet(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point value `a' is less than
+| the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
+| exception. Otherwise, the comparison is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_lt_quiet(float16 a, float16 b, float_status *status)
+{
+ flag aSign, bSign;
+ uint32_t av, bv;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 0;
+ }
+ aSign = extractFloat16Sign( a );
+ bSign = extractFloat16Sign( b );
+ av = float16_val(a);
+ bv = float16_val(b);
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
+
+}
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the half-precision floating-point values `a' and `b' cannot
+| be compared, and 0 otherwise. Quiet NaNs do not cause an exception. The
+| comparison is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+int float16_unordered_quiet(float16 a, float16 b, float_status *status)
+{
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
+ ) {
+ if (float16_is_signaling_nan(a, status)
+ || float16_is_signaling_nan(b, status)) {
+ float_raise(float_flag_invalid, status);
+ }
+ return 1;
+ }
+ return 0;
+}
+
/* Half precision floats come in two formats: standard IEEE and "ARM" format.
The latter gains extra exponent range by omitting the NaN/Inf encodings. */
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index f1d79b6d03..76a8310780 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -350,6 +350,14 @@ float16 float16_add(float16, float16, float_status *status);
float16 float16_sub(float16, float16, float_status *status);
float16 float16_mul(float16, float16, float_status *status);
float16 float16_div(float16, float16, float_status *status);
+int float16_eq(float16, float16, float_status *status);
+int float16_le(float16, float16, float_status *status);
+int float16_lt(float16, float16, float_status *status);
+int float16_unordered(float16, float16, float_status *status);
+int float16_eq_quiet(float16, float16, float_status *status);
+int float16_le_quiet(float16, float16, float_status *status);
+int float16_lt_quiet(float16, float16, float_status *status);
+int float16_unordered_quiet(float16, float16, float_status *status);
int float16_is_quiet_nan(float16, float_status *status);
int float16_is_signaling_nan(float16, float_status *status);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions Alex Bennée
@ 2017-10-17 0:06 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-17 0:06 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +int float16_eq(float16 a, float16 b, float_status *status)
> +{
> + uint32_t av, bv;
> + a = float16_squash_input_denormal(a, status);
> + b = float16_squash_input_denormal(b, status);
> +
> + if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
> + || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
float16_is_any_nan
> + ) {
> + float_raise(float_flag_invalid, status);
> + return 0;
> + }
> + av = float16_val(a);
> + bv = float16_val(b);
> + return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
For this trick to work you have to truncate to uint16_t not uint32_t.
It might be easier to read as
a == b || float16_is_zero(a | b)
That said, I wonder if it wouldn't be better to implement all of these in terms
of float16_compare, rather than duplicating all of this code.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (19 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 20/30] softfloat: half-precision compare functions Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-17 0:36 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same Alex Bennée
` (11 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
I re-use the existing handle_2misc_fcmp_zero handler and tweak it
slightly to deal with the half-precision case.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 39 +++++++++++++++++++++++++++++++++++++++
target/arm/helper-a64.h | 6 ++++++
target/arm/translate-a64.c | 25 ++++++++++++++++++-------
3 files changed, 63 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index dd26675d5c..b62d77aec4 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -577,3 +577,42 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
}
return float16_mul(a, b, fpst);
}
+
+
+/*
+ * Floating point comparisons produce an integer result.
+ * Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires.
+ */
+uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return -float16_eq_quiet(a, b, fpst);
+}
+
+uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return -float16_le(b, a, fpst);
+}
+
+uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return -float16_lt(b, a, fpst);
+}
+
+uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ float16 f0 = float16_abs(a);
+ float16 f1 = float16_abs(b);
+ return -float16_le(f1, f0, fpst);
+}
+
+/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */
+/* { */
+/* float_status *fpst = fpstp; */
+/* float16 f0 = float16_abs(a); */
+/* float16 f1 = float16_abs(b); */
+/* return -float16_lt(f1, f0, fpst); */
+/* } */
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 0f97eb607f..952869f43e 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -53,3 +53,9 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
+
+DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
+DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7792cea9f5..623b0b3fab 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7785,6 +7785,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
TCGv_i32 tcg_res = tcg_temp_new_i32();
NeonGenTwoSingleOPFn *genfn;
bool swap = false;
+ bool hp = (size == 1 ? true : false);
int pass, maxpasses;
switch (opcode) {
@@ -7792,7 +7793,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
swap = true;
/* fall through */
case 0x2c: /* FCMGT (zero) */
- genfn = gen_helper_neon_cgt_f32;
+ genfn = hp ? gen_helper_advsimd_cgt_f16 : gen_helper_neon_cgt_f32;
break;
case 0x2d: /* FCMEQ (zero) */
genfn = gen_helper_neon_ceq_f32;
@@ -7814,7 +7815,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
}
for (pass = 0; pass < maxpasses; pass++) {
- read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
+ read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32);
if (swap) {
genfn(tcg_res, tcg_zero, tcg_op, fpst);
} else {
@@ -7823,7 +7824,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
if (is_scalar) {
write_fp_sreg(s, rd, tcg_res);
} else {
- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
+ write_vec_element_i32(s, tcg_res, rd, pass, hp ? MO_16 : MO_32);
}
}
tcg_temp_free_i32(tcg_res);
@@ -9809,6 +9810,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
case 0x2: /* FADD */
gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
break;
+ case 0x6: /* FMAX */
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
case 0x23: /* FMUL */
gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
break;
@@ -10580,21 +10584,28 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
{
int fpop, opcode, a;
+ int rn, rd;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
}
- if (!fp_access_check(s)) {
- return;
- }
-
opcode = extract32(insn, 12, 4);
a = extract32(insn, 23, 1);
fpop = deposit32(opcode, 5, 1, a);
+ rn = extract32(insn, 5, 5);
+ rd = extract32(insn, 0, 5);
+
switch (fpop) {
+ case 0x2c: /* FCMGT (zero) */
+ case 0x2d: /* FCMEQ (zero) */
+ case 0x2e: /* FCMLT (zero) */
+ case 0x6c: /* FCMGE (zero) */
+ case 0x6d: /* FCMLE (zero) */
+ handle_2misc_fcmp_zero(s, fpop, true, 0, false, 1, rn, rd);
+ break;
default:
fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) Alex Bennée
@ 2017-10-17 0:36 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-17 0:36 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> @@ -7792,7 +7793,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
> swap = true;
> /* fall through */
> case 0x2c: /* FCMGT (zero) */
> - genfn = gen_helper_neon_cgt_f32;
> + genfn = hp ? gen_helper_advsimd_cgt_f16 : gen_helper_neon_cgt_f32;
> break;
> case 0x2d: /* FCMEQ (zero) */
> genfn = gen_helper_neon_ceq_f32;
> @@ -7814,7 +7815,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
> }
>
> for (pass = 0; pass < maxpasses; pass++) {
> - read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
> + read_vec_element_i32(s, tcg_op, rn, pass, hp ? MO_16 : MO_32);
> if (swap) {
> genfn(tcg_res, tcg_zero, tcg_op, fpst);
> } else {
I don't see a change to maxpasses here.
> case 0x2: /* FADD */
> gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
> break;
> + case 0x6: /* FMAX */
> + gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
> + break;
> case 0x23: /* FMUL */
> gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
> break;
Belongs in another patch?
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (20 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 21/30] target/arm/translate-a64: add FP16 2-reg misc compare (zero) Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-17 0:39 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) Alex Bennée
` (10 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 14 +++++++-------
target/arm/helper-a64.h | 1 -
target/arm/translate-a64.c | 3 +++
3 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index b62d77aec4..137866732d 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -609,10 +609,10 @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
return -float16_le(f1, f0, fpst);
}
-/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */
-/* { */
-/* float_status *fpst = fpstp; */
-/* float16 f0 = float16_abs(a); */
-/* float16 f1 = float16_abs(b); */
-/* return -float16_lt(f1, f0, fpst); */
-/* } */
+uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ float16 f0 = float16_abs(a);
+ float16 f1 = float16_abs(b);
+ return -float16_lt(f1, f0, fpst);
+}
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 952869f43e..66c4062ea5 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -53,7 +53,6 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
-
DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 623b0b3fab..4ad470d9e8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9819,6 +9819,9 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
case 0x27: /* FDIV */
gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
break;
+ case 0x35: /* FACGT */
+ gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
default:
fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
__func__, insn, fpopcode, s->pc);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same Alex Bennée
@ 2017-10-17 0:39 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-17 0:39 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> -/* uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp) */
> -/* { */
> -/* float_status *fpst = fpstp; */
> -/* float16 f0 = float16_abs(a); */
> -/* float16 f1 = float16_abs(b); */
> -/* return -float16_lt(f1, f0, fpst); */
> -/* } */
> +uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
> +{
> + float_status *fpst = fpstp;
> + float16 f0 = float16_abs(a);
> + float16 f1 = float16_abs(b);
> + return -float16_lt(f1, f0, fpst);
> +}
Should be folded into previous. But otherwise ok.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (21 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 22/30] target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-17 2:17 ` Richard Henderson
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations Alex Bennée
` (9 subsequent siblings)
32 siblings, 1 reply; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat-specialize.h | 52 +++++++
fpu/softfloat.c | 327 +++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 2 +
3 files changed, 381 insertions(+)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 2ccd4abe11..33c4be1757 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -728,6 +728,58 @@ static float16 propagateFloat16NaN(float16 a, float16 b, float_status *status)
}
}
+/*----------------------------------------------------------------------------
+| Takes three half-precision floating-point values `a', `b' and `c', one of
+| which is a NaN, and returns the appropriate NaN result. If any of `a',
+| `b' or `c' is a signaling NaN, the invalid exception is raised.
+| The input infzero indicates whether a*b was 0*inf or inf*0 (in which case
+| obviously c is a NaN, and whether to propagate c or some other NaN is
+| implementation defined).
+*----------------------------------------------------------------------------*/
+
+static float16 propagateFloat16MulAddNaN(float16 a, float16 b,
+ float16 c, flag infzero,
+ float_status *status)
+{
+ flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
+ cIsQuietNaN, cIsSignalingNaN;
+ int which;
+
+ aIsQuietNaN = float16_is_quiet_nan(a, status);
+ aIsSignalingNaN = float16_is_signaling_nan(a, status);
+ bIsQuietNaN = float16_is_quiet_nan(b, status);
+ bIsSignalingNaN = float16_is_signaling_nan(b, status);
+ cIsQuietNaN = float16_is_quiet_nan(c, status);
+ cIsSignalingNaN = float16_is_signaling_nan(c, status);
+
+ if (aIsSignalingNaN | bIsSignalingNaN | cIsSignalingNaN) {
+ float_raise(float_flag_invalid, status);
+ }
+
+ which = pickNaNMulAdd(aIsQuietNaN, aIsSignalingNaN,
+ bIsQuietNaN, bIsSignalingNaN,
+ cIsQuietNaN, cIsSignalingNaN, infzero, status);
+
+ if (status->default_nan_mode) {
+ /* Note that this check is after pickNaNMulAdd so that function
+ * has an opportunity to set the Invalid flag.
+ */
+ return float16_default_nan(status);
+ }
+
+ switch (which) {
+ case 0:
+ return float16_maybe_silence_nan(a, status);
+ case 1:
+ return float16_maybe_silence_nan(b, status);
+ case 2:
+ return float16_maybe_silence_nan(c, status);
+ case 3:
+ default:
+ return float16_default_nan(status);
+ }
+}
+
/*----------------------------------------------------------------------------
| Takes two single-precision floating-point values `a' and `b', one of which
| is a NaN, and returns the appropriate NaN result. If either `a' or `b' is a
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index fdb2999c41..f7473f97e3 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3884,6 +3884,333 @@ float16 float16_div(float16 a, float16 b, float_status *status)
}
+/*----------------------------------------------------------------------------
+| Returns the remainder of the half-precision floating-point value `a'
+| with respect to the corresponding value `b'. The operation is performed
+| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+float16 float16_rem(float16 a, float16 b, float_status *status)
+{
+ flag aSign, zSign;
+ int aExp, bExp, expDiff;
+ uint32_t aSig, bSig;
+ uint32_t q;
+ uint64_t aSig64, bSig64, q64;
+ uint32_t alternateASig;
+ int32_t sigMean;
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+
+ aSig = extractFloat32Frac( a );
+ aExp = extractFloat32Exp( a );
+ aSign = extractFloat32Sign( a );
+ bSig = extractFloat32Frac( b );
+ bExp = extractFloat32Exp( b );
+ if ( aExp == 0xFF ) {
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
+ return propagateFloat32NaN(a, b, status);
+ }
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ if ( bExp == 0xFF ) {
+ if (bSig) {
+ return propagateFloat32NaN(a, b, status);
+ }
+ return a;
+ }
+ if ( bExp == 0 ) {
+ if ( bSig == 0 ) {
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );
+ }
+ if ( aExp == 0 ) {
+ if ( aSig == 0 ) return a;
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );
+ }
+ expDiff = aExp - bExp;
+ aSig |= 0x00800000;
+ bSig |= 0x00800000;
+ if ( expDiff < 32 ) {
+ aSig <<= 8;
+ bSig <<= 8;
+ if ( expDiff < 0 ) {
+ if ( expDiff < -1 ) return a;
+ aSig >>= 1;
+ }
+ q = ( bSig <= aSig );
+ if ( q ) aSig -= bSig;
+ if ( 0 < expDiff ) {
+ q = ( ( (uint64_t) aSig )<<32 ) / bSig;
+ q >>= 32 - expDiff;
+ bSig >>= 2;
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
+ }
+ else {
+ aSig >>= 2;
+ bSig >>= 2;
+ }
+ }
+ else {
+ if ( bSig <= aSig ) aSig -= bSig;
+ aSig64 = ( (uint64_t) aSig )<<40;
+ bSig64 = ( (uint64_t) bSig )<<40;
+ expDiff -= 64;
+ while ( 0 < expDiff ) {
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;
+ aSig64 = - ( ( bSig * q64 )<<38 );
+ expDiff -= 62;
+ }
+ expDiff += 64;
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;
+ q = q64>>( 64 - expDiff );
+ bSig <<= 6;
+ aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
+ }
+ do {
+ alternateASig = aSig;
+ ++q;
+ aSig -= bSig;
+ } while ( 0 <= (int32_t) aSig );
+ sigMean = aSig + alternateASig;
+ if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
+ aSig = alternateASig;
+ }
+ zSign = ( (int32_t) aSig < 0 );
+ if ( zSign ) aSig = - aSig;
+ return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status);
+}
+
+/*----------------------------------------------------------------------------
+| Returns the result of multiplying the half-precision floating-point values
+| `a' and `b' then adding 'c', with no intermediate rounding step after the
+| multiplication. The operation is performed according to the IEC/IEEE
+| Standard for Binary Floating-Point Arithmetic 754-2008.
+| The flags argument allows the caller to select negation of the
+| addend, the intermediate product, or the final result. (The difference
+| between this and having the caller do a separate negation is that negating
+| externally will flip the sign bit on NaNs.)
+*----------------------------------------------------------------------------*/
+
+float16 float16_muladd(float16 a, float16 b, float16 c, int flags,
+ float_status *status)
+{
+ flag aSign, bSign, cSign, zSign;
+ int aExp, bExp, cExp, pExp, zExp, expDiff;
+ uint32_t aSig, bSig, cSig;
+ flag pInf, pZero, pSign;
+ uint64_t pSig64, cSig64, zSig64;
+ uint32_t pSig;
+ int shiftcount;
+ flag signflip, infzero;
+
+ a = float16_squash_input_denormal(a, status);
+ b = float16_squash_input_denormal(b, status);
+ c = float16_squash_input_denormal(c, status);
+ aSig = extractFloat16Frac(a);
+ aExp = extractFloat16Exp(a);
+ aSign = extractFloat16Sign(a);
+ bSig = extractFloat16Frac(b);
+ bExp = extractFloat16Exp(b);
+ bSign = extractFloat16Sign(b);
+ cSig = extractFloat16Frac(c);
+ cExp = extractFloat16Exp(c);
+ cSign = extractFloat16Sign(c);
+
+ infzero = ((aExp == 0 && aSig == 0 && bExp == 0x1f && bSig == 0) ||
+ (aExp == 0x1f && aSig == 0 && bExp == 0 && bSig == 0));
+
+ /* It is implementation-defined whether the cases of (0,inf,qnan)
+ * and (inf,0,qnan) raise InvalidOperation or not (and what QNaN
+ * they return if they do), so we have to hand this information
+ * off to the target-specific pick-a-NaN routine.
+ */
+ if (((aExp == 0xff) && aSig) ||
+ ((bExp == 0xff) && bSig) ||
+ ((cExp == 0xff) && cSig)) {
+ return propagateFloat16MulAddNaN(a, b, c, infzero, status);
+ }
+
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+
+ if (flags & float_muladd_negate_c) {
+ cSign ^= 1;
+ }
+
+ signflip = (flags & float_muladd_negate_result) ? 1 : 0;
+
+ /* Work out the sign and type of the product */
+ pSign = aSign ^ bSign;
+ if (flags & float_muladd_negate_product) {
+ pSign ^= 1;
+ }
+ pInf = (aExp == 0xff) || (bExp == 0xff);
+ pZero = ((aExp | aSig) == 0) || ((bExp | bSig) == 0);
+
+ if (cExp == 0xff) {
+ if (pInf && (pSign ^ cSign)) {
+ /* addition of opposite-signed infinities => InvalidOperation */
+ float_raise(float_flag_invalid, status);
+ return float16_default_nan(status);
+ }
+ /* Otherwise generate an infinity of the same sign */
+ return packFloat16(cSign ^ signflip, 0xff, 0);
+ }
+
+ if (pInf) {
+ return packFloat16(pSign ^ signflip, 0xff, 0);
+ }
+
+ if (pZero) {
+ if (cExp == 0) {
+ if (cSig == 0) {
+ /* Adding two exact zeroes */
+ if (pSign == cSign) {
+ zSign = pSign;
+ } else if (status->float_rounding_mode == float_round_down) {
+ zSign = 1;
+ } else {
+ zSign = 0;
+ }
+ return packFloat16(zSign ^ signflip, 0, 0);
+ }
+ /* Exact zero plus a denorm */
+ if (status->flush_to_zero) {
+ float_raise(float_flag_output_denormal, status);
+ return packFloat16(cSign ^ signflip, 0, 0);
+ }
+ }
+ /* Zero plus something non-zero : just return the something */
+ if (flags & float_muladd_halve_result) {
+ if (cExp == 0) {
+ normalizeFloat16Subnormal(cSig, &cExp, &cSig);
+ }
+ /* Subtract one to halve, and one again because roundAndPackFloat16
+ * wants one less than the true exponent.
+ */
+ cExp -= 2;
+ cSig = (cSig | 0x00800000) << 7;
+ return roundAndPackFloat16(cSign ^ signflip, cExp, cSig, true, status);
+ }
+ return packFloat16(cSign ^ signflip, cExp, cSig);
+ }
+
+ if (aExp == 0) {
+ normalizeFloat16Subnormal(aSig, &aExp, &aSig);
+ }
+ if (bExp == 0) {
+ normalizeFloat16Subnormal(bSig, &bExp, &bSig);
+ }
+
+ /* Calculate the actual result a * b + c */
+
+ /* Multiply first; this is easy. */
+ /* NB: we subtract 0x7e where float16_mul() subtracts 0x7f
+ * because we want the true exponent, not the "one-less-than"
+ * flavour that roundAndPackFloat16() takes.
+ */
+ pExp = aExp + bExp - 0x7e;
+ aSig = (aSig | 0x00800000) << 7;
+ bSig = (bSig | 0x00800000) << 8;
+ pSig64 = (uint64_t)aSig * bSig;
+ if ((int64_t)(pSig64 << 1) >= 0) {
+ pSig64 <<= 1;
+ pExp--;
+ }
+
+ zSign = pSign ^ signflip;
+
+ /* Now pSig64 is the significand of the multiply, with the explicit bit in
+ * position 62.
+ */
+ if (cExp == 0) {
+ if (!cSig) {
+ /* Throw out the special case of c being an exact zero now */
+ shift64RightJamming(pSig64, 32, &pSig64);
+ pSig = pSig64;
+ if (flags & float_muladd_halve_result) {
+ pExp--;
+ }
+ return roundAndPackFloat16(zSign, pExp - 1,
+ pSig, true, status);
+ }
+ normalizeFloat16Subnormal(cSig, &cExp, &cSig);
+ }
+
+ cSig64 = (uint64_t)cSig << (62 - 23);
+ cSig64 |= LIT64(0x4000000000000000);
+ expDiff = pExp - cExp;
+
+ if (pSign == cSign) {
+ /* Addition */
+ if (expDiff > 0) {
+ /* scale c to match p */
+ shift64RightJamming(cSig64, expDiff, &cSig64);
+ zExp = pExp;
+ } else if (expDiff < 0) {
+ /* scale p to match c */
+ shift64RightJamming(pSig64, -expDiff, &pSig64);
+ zExp = cExp;
+ } else {
+ /* no scaling needed */
+ zExp = cExp;
+ }
+ /* Add significands and make sure explicit bit ends up in posn 62 */
+ zSig64 = pSig64 + cSig64;
+ if ((int64_t)zSig64 < 0) {
+ shift64RightJamming(zSig64, 1, &zSig64);
+ } else {
+ zExp--;
+ }
+ } else {
+ /* Subtraction */
+ if (expDiff > 0) {
+ shift64RightJamming(cSig64, expDiff, &cSig64);
+ zSig64 = pSig64 - cSig64;
+ zExp = pExp;
+ } else if (expDiff < 0) {
+ shift64RightJamming(pSig64, -expDiff, &pSig64);
+ zSig64 = cSig64 - pSig64;
+ zExp = cExp;
+ zSign ^= 1;
+ } else {
+ zExp = pExp;
+ if (cSig64 < pSig64) {
+ zSig64 = pSig64 - cSig64;
+ } else if (pSig64 < cSig64) {
+ zSig64 = cSig64 - pSig64;
+ zSign ^= 1;
+ } else {
+ /* Exact zero */
+ zSign = signflip;
+ if (status->float_rounding_mode == float_round_down) {
+ zSign ^= 1;
+ }
+ return packFloat16(zSign, 0, 0);
+ }
+ }
+ --zExp;
+ /* Normalize to put the explicit bit back into bit 62. */
+ shiftcount = countLeadingZeros64(zSig64) - 1;
+ zSig64 <<= shiftcount;
+ zExp -= shiftcount;
+ }
+ if (flags & float_muladd_halve_result) {
+ zExp--;
+ }
+
+ shift64RightJamming(zSig64, 32, &zSig64);
+ return roundAndPackFloat16(zSign, zExp, zSig64, true, status);
+}
+
/*----------------------------------------------------------------------------
| Returns 1 if the half-precision floating-point value `a' is equal to
| the corresponding value `b', and 0 otherwise. The invalid exception is
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 76a8310780..a7435e2a5b 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -350,6 +350,8 @@ float16 float16_add(float16, float16, float_status *status);
float16 float16_sub(float16, float16, float_status *status);
float16 float16_mul(float16, float16, float_status *status);
float16 float16_div(float16, float16, float_status *status);
+float16 float16_rem(float16, float16, float_status *status);
+float16 float16_muladd(float16, float16, float16, int, float_status *status);
int float16_eq(float16, float16, float_status *status);
int float16_le(float16, float16, float_status *status);
int float16_lt(float16, float16, float_status *status);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) Alex Bennée
@ 2017-10-17 2:17 ` Richard Henderson
0 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-17 2:17 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm, Aurelien Jarno
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> +float16 float16_rem(float16 a, float16 b, float_status *status)
> +{
> + flag aSign, zSign;
> + int aExp, bExp, expDiff;
> + uint32_t aSig, bSig;
> + uint32_t q;
> + uint64_t aSig64, bSig64, q64;
> + uint32_t alternateASig;
> + int32_t sigMean;
> + a = float16_squash_input_denormal(a, status);
> + b = float16_squash_input_denormal(b, status);
> +
> + aSig = extractFloat32Frac( a );
> + aExp = extractFloat32Exp( a );
> + aSign = extractFloat32Sign( a );
> + bSig = extractFloat32Frac( b );
> + bExp = extractFloat32Exp( b );
> + if ( aExp == 0xFF ) {
> + if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
> + return propagateFloat32NaN(a, b, status);
> + }
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + if ( bExp == 0xFF ) {
> + if (bSig) {
> + return propagateFloat32NaN(a, b, status);
> + }
> + return a;
> + }
s/0xff/0x1f/.
> + if ( bExp == 0 ) {
> + if ( bSig == 0 ) {
> + float_raise(float_flag_invalid, status);
> + return float16_default_nan(status);
> + }
> + normalizeFloat32Subnormal( bSig, &bExp, &bSig );
> + }
> + if ( aExp == 0 ) {
> + if ( aSig == 0 ) return a;
> + normalizeFloat32Subnormal( aSig, &aExp, &aSig );
> + }
> + expDiff = aExp - bExp;
> + aSig |= 0x00800000;
> + bSig |= 0x00800000;
These implicit bits are set for float32.
> + if ( expDiff < 32 ) {
> + aSig <<= 8;
> + bSig <<= 8;
This algorithm isn't going to work unless the fractions are normalized to
0b1xxx_xxxx_xxx0_0000, just like for float32. Indeed, I think you should
actually share code.
> + return normalizeRoundAndPackFloat32(aSign ^ zSign, bExp, aSig, status);
... but you really will have to pack into the correct format.
> + if (((aExp == 0xff) && aSig) ||
> + ((bExp == 0xff) && bSig) ||
> + ((cExp == 0xff) && cSig)) {
0x1f, lots more times.
> + /* Calculate the actual result a * b + c */
> +
> + /* Multiply first; this is easy. */
> + /* NB: we subtract 0x7e where float16_mul() subtracts 0x7f
> + * because we want the true exponent, not the "one-less-than"
> + * flavour that roundAndPackFloat16() takes.
> + */
> + pExp = aExp + bExp - 0x7e;
> + aSig = (aSig | 0x00800000) << 7;
> + bSig = (bSig | 0x00800000) << 8;
All of these constants are for float32, not float16.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread
* [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (22 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 23/30] softfloat: add float16_rem and float16_muladd (!CHECK) Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int Alex Bennée
` (8 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
A mild re-factoring of the !is_double leg to gracefully handle both
single and half-precision operations.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 6 ++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 19 +++++++++++++------
3 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 137866732d..241fee9d93 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -578,6 +578,12 @@ float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp)
return float16_mul(a, b, fpst);
}
+/* fused multiply-accumulate */
+float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+{
+ float_status *fpst = fpstp;
+ return float16_muladd(a, b, c, 0, fpst);
+}
/*
* Floating point comparisons produce an integer result.
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 66c4062ea5..444d046500 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -53,6 +53,7 @@ DEF_HELPER_3(advsimd_minh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_maxnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_minnumh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr)
+DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_ceq_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4ad470d9e8..142b23abb5 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10757,7 +10757,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
TCGV_UNUSED_PTR(fpst);
}
- if (size == 3) {
+ if (size == MO_64) {
TCGv_i64 tcg_idx = tcg_temp_new_i64();
int pass;
@@ -10802,11 +10802,12 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_idx);
} else if (!is_long) {
- /* 32 bit floating point, or 16 or 32 bit integer.
+ /* 16 or 32 bit floating point, or 16 or 32 bit integer.
* For the 16 bit scalar case we use the usual Neon helpers and
* rely on the fact that 0 op 0 == 0 with no side effects.
*/
TCGv_i32 tcg_idx = tcg_temp_new_i32();
+ bool hp = (size == MO_16 ? true : false);
int pass, maxpasses;
if (is_scalar) {
@@ -10829,7 +10830,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
TCGv_i32 tcg_op = tcg_temp_new_i32();
TCGv_i32 tcg_res = tcg_temp_new_i32();
- read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
+ read_vec_element_i32(s, tcg_op, rn, pass, size);
switch (opcode) {
case 0x0: /* MLA */
@@ -10861,8 +10862,14 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
gen_helper_vfp_negs(tcg_op, tcg_op);
/* fall through */
case 0x1: /* FMLA */
- read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
- gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
+ read_vec_element_i32(s, tcg_res, rd, pass, size);
+ if (hp) {
+ gen_helper_advsimd_muladdh(tcg_res, tcg_op,
+ tcg_idx, tcg_res, fpst);
+ } else {
+ gen_helper_vfp_muladds(tcg_res, tcg_op,
+ tcg_idx, tcg_res, fpst);
+ }
break;
case 0x9: /* FMUL, FMULX */
switch (size) {
@@ -10909,7 +10916,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
if (is_scalar) {
write_fp_sreg(s, rd, tcg_res);
} else {
- write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
+ write_vec_element_i32(s, tcg_res, rd, pass, size);
}
tcg_temp_free_i32(tcg_op);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (23 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 24/30] disas_simd_indexed: support half-precision operations Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework Alex Bennée
` (7 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
Again a mechanical conversion.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 1 +
2 files changed, 83 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index f7473f97e3..dc7f5f6d88 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -3532,6 +3532,88 @@ static void normalizeFloat16Subnormal(uint32_t aSig, int *zExpPtr,
*zExpPtr = 1 - shiftCount;
}
+/*----------------------------------------------------------------------------
+| Rounds the half-precision floating-point value `a' to an integer,
+| and returns the result as a half-precision floating-point value. The
+| operation is performed according to the IEC/IEEE Standard for Binary
+| Floating-Point Arithmetic.
+*----------------------------------------------------------------------------*/
+
+float16 float16_round_to_int(float16 a, float_status *status)
+{
+ flag aSign;
+ int aExp;
+ uint16_t lastBitMask, roundBitsMask;
+ uint16_t z;
+ a = float16_squash_input_denormal(a, status);
+
+ aExp = extractFloat16Exp( a );
+ if ( 0x19 <= aExp ) {
+ if ( ( aExp == 0x1F ) && extractFloat16Frac( a ) ) {
+ return propagateFloat16NaN(a, a, status);
+ }
+ return a;
+ }
+ if ( aExp <= 0xE ) {
+ if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a;
+ status->float_exception_flags |= float_flag_inexact;
+ aSign = extractFloat16Sign( a );
+ switch (status->float_rounding_mode) {
+ case float_round_nearest_even:
+ if ( ( aExp == 0xE ) && extractFloat16Frac( a ) ) {
+ return packFloat16( aSign, 0xF, 0 );
+ }
+ break;
+ case float_round_ties_away:
+ if (aExp == 0xE) {
+ return packFloat16(aSign, 0xF, 0);
+ }
+ break;
+ case float_round_down:
+ return make_float16(aSign ? 0xBC00 : 0);
+ case float_round_up:
+ /* -0.0/1.0f */
+ return make_float16(aSign ? 0x8000 : 0x3C00);
+ }
+ return packFloat16( aSign, 0, 0 );
+ }
+ lastBitMask = 1;
+ lastBitMask <<= 0x19 - aExp;
+ roundBitsMask = lastBitMask - 1;
+ z = float16_val(a);
+ switch (status->float_rounding_mode) {
+ case float_round_nearest_even:
+ z += lastBitMask>>1;
+ if ((z & roundBitsMask) == 0) {
+ z &= ~lastBitMask;
+ }
+ break;
+ case float_round_ties_away:
+ z += lastBitMask >> 1;
+ break;
+ case float_round_to_zero:
+ break;
+ case float_round_up:
+ if (!extractFloat16Sign(make_float16(z))) {
+ z += roundBitsMask;
+ }
+ break;
+ case float_round_down:
+ if (extractFloat16Sign(make_float16(z))) {
+ z += roundBitsMask;
+ }
+ break;
+ default:
+ abort();
+ }
+ z &= ~ roundBitsMask;
+ if (z != float16_val(a)) {
+ status->float_exception_flags |= float_flag_inexact;
+ }
+ return make_float16(z);
+
+}
+
/*----------------------------------------------------------------------------
| Returns the result of adding the absolute values of the half-precision
| floating-point values `a' and `b'. If `zSign' is 1, the sum is negated
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index a7435e2a5b..856f67cf12 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -346,6 +346,7 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
| Software half-precision operations.
*----------------------------------------------------------------------------*/
+float16 float16_round_to_int(float16, float_status *status);
float16 float16_add(float16, float16, float_status *status);
float16 float16_sub(float16, float16, float_status *status);
float16 float16_mul(float16, float16, float_status *status);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (24 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 25/30] softfloat: float16_round_to_int Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc Alex Bennée
` (6 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
This is a simple pattern based framework for testing our softfloat
implementation. It is easier to use while debugging softfloat itself
than indirectly with a tool like risu.
As the softfloat library is built against given targets we need a
version per target architecture we build.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
tests/Makefile.include | 8 ++++++-
tests/test-softfloat.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 tests/test-softfloat.c
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 4ca15e6817..8bf1dfd19a 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -156,6 +156,10 @@ check-unit-y += tests/ptimer-test$(EXESUF)
gcov-files-ptimer-test-y = hw/core/ptimer.c
check-unit-y += tests/test-qapi-util$(EXESUF)
gcov-files-test-qapi-util-y = qapi/qapi-util.c
+check-unit-y += tests/test-softfloat$(EXESUF)
+gcov-files-test-softfloat-y = fpu/softfloat.c
+check-unit-y += tests/test-softfloat-aarch64$(EXESUF)
+gcov-files-test-softfloat-aarch64-y = fpu/softfloat.c
check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh
@@ -555,7 +559,7 @@ test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \
tests/rcutorture.o tests/test-rcu-list.o \
tests/test-qdist.o tests/test-shift128.o \
tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \
- tests/atomic_add-bench.o
+ tests/atomic_add-bench.o tests/test-softfloat.o
$(test-obj-y): QEMU_INCLUDES += -Itests
QEMU_CFLAGS += -I$(SRC_PATH)/tests
@@ -604,6 +608,8 @@ tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(tes
tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y)
tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y)
tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y)
+tests/test-softfloat$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o
+tests/test-softfloat-aarch64$(EXESUF): tests/test-softfloat.o $(BUILD_DIR)/aarch64-softmmu/fpu/softfloat.o
tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c
new file mode 100644
index 0000000000..d7b740e1cb
--- /dev/null
+++ b/tests/test-softfloat.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2017, Linaro
+ * Author: Alex Bennée <alex.bennee@linaro.org>
+ *
+ * License: GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "fpu/softfloat.h"
+
+typedef struct {
+ float_status initial_status;
+ float16 in;
+ float16 out;
+ uint8_t final_exception_flags;
+} f16_test_data;
+
+static void test_f16_round_to_int(void)
+{
+ int i;
+ float16 out;
+ float_status flags, *fp = &flags;
+ f16_test_data test_data[] = {
+ { { /* defaults */ }, 0x87FF, 0x8000 },
+ { { /* defaults */ }, 0xE850, 0xE850 },
+ { { /* defaults */ }, 0x0000, 0x0000 },
+ { { /* defaults */ }, 0x857F, 0x8000 },
+ { { /* defaults */ }, 0x74FB, 0x74FB },
+ /* from risu 3b4: 4ef98945 frintp v5.8h, v10.8h */
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x06b1, 0x3c00, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x6966, 0x6966, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x83c0, 0x8000, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xa619, 0x8000, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x9cf4, 0x8000, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee11, 0xee11, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee5c, 0xee5c, 0 },
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x8004, 0x8000, 0 }
+ };
+
+ for (i = 0; i < ARRAY_SIZE(test_data); ++i) {
+ flags = test_data[i].initial_status;
+ out = float16_round_to_int(test_data[i].in, fp);
+
+ if (!(test_data[i].out == out)) {
+ fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n",
+ __func__, i, test_data[i].out, out);
+ g_test_fail();
+ }
+ }
+}
+
+int main(int argc, char *argv[])
+{
+ g_test_init(&argc, &argv, NULL);
+ g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int);
+ return g_test_run();
+}
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (25 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 26/30] tests/test-softfloat: add a simple test framework Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion Alex Bennée
` (5 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 17 ++++++++++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 74 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 241fee9d93..63b2bbd4b2 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -585,6 +585,23 @@ float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
return float16_muladd(a, b, c, 0, fpst);
}
+/* round to integral */
+float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+{
+ int old_flags = get_float_exception_flags(fp_status), new_flags;
+ float16 ret;
+
+ ret = float16_round_to_int(x, fp_status);
+
+ /* Suppress any inexact exceptions the conversion produced */
+ if (!(old_flags & float_flag_inexact)) {
+ new_flags = get_float_exception_flags(fp_status);
+ set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
+ }
+
+ return ret;
+}
+
/*
* Floating point comparisons produce an integer result.
* Softfloat routines return 0/1, which we convert to the 0/-1 Neon requires.
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index 444d046500..ce36d81091 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -59,3 +59,4 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
+DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 142b23abb5..bbc0d96f01 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10588,6 +10588,12 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
{
int fpop, opcode, a;
int rn, rd;
+ int is_q;
+ int pass;
+ TCGv_i32 tcg_rmode;
+ TCGv_ptr tcg_fpstatus;
+ bool need_rmode = false;
+ int rmode;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
@@ -10608,12 +10614,62 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
case 0x6c: /* FCMGE (zero) */
case 0x6d: /* FCMLE (zero) */
handle_2misc_fcmp_zero(s, fpop, true, 0, false, 1, rn, rd);
+ return;
+ break;
+ case 0x28: /* FRINTP */
+ need_rmode = true;
+ rmode = FPROUNDING_POSINF;
break;
default:
fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
}
+ is_q = extract32(insn, 30, 1);
+
+ if (!fp_access_check(s)) {
+ return;
+ }
+
+ tcg_fpstatus = get_fpstatus_ptr();
+
+ if (need_rmode) {
+ tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ } else {
+ TCGV_UNUSED_I32(tcg_rmode);
+ }
+
+ for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
+ TCGv_i32 tcg_res = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
+
+ switch (fpop) {
+ case 0x28: /* FRINTP */
+ gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
+
+ tcg_temp_free_i32(tcg_res);
+ tcg_temp_free_i32(tcg_op);
+ }
+
+ if (!is_q) {
+ clear_vec_high(s, rd);
+ }
+
+ if (need_rmode) {
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
+ tcg_temp_free_i32(tcg_rmode);
+ }
+
+ tcg_temp_free_ptr(tcg_fpstatus);
}
/* AdvSIMD scalar x indexed element
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (26 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 27/30] target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test Alex Bennée
` (4 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson
Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée,
Aurelien Jarno
I didn't have another reference for this so I wrote it from first
principles. The roundAndPackInt16 works with the same shifted input as
roundAndPacknt32 but with different constants for invalid testing for
overflow.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
fpu/softfloat.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++++
include/fpu/softfloat.h | 1 +
2 files changed, 99 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index dc7f5f6d88..63f7cd1226 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -132,6 +132,62 @@ static inline flag extractFloat16Sign(float16 a)
return float16_val(a)>>15;
}
+/*----------------------------------------------------------------------------
+| Takes a 32-bit fixed-point value `absZ' with binary point between bits 6
+| and 7, and returns the properly rounded 16-bit integer corresponding to the
+| input. If `zSign' is 1, the input is negated before being converted to an
+| integer. Bit 31 of `absZ' must be zero. Ordinarily, the fixed-point input
+| is simply rounded to an integer, with the inexact exception raised if the
+| input cannot be represented exactly as an integer. However, if the fixed-
+| point input is too large, the invalid exception is raised and the largest
+| positive or negative integer is returned.
+*----------------------------------------------------------------------------*/
+
+static int16_t roundAndPackInt16(flag zSign, uint32_t absZ, float_status *status)
+{
+ int8_t roundingMode;
+ flag roundNearestEven;
+ int8_t roundIncrement, roundBits;
+ int16_t z;
+
+ roundingMode = status->float_rounding_mode;
+ roundNearestEven = ( roundingMode == float_round_nearest_even );
+
+ switch (roundingMode) {
+ case float_round_nearest_even:
+ case float_round_ties_away:
+ roundIncrement = 0x40;
+ break;
+ case float_round_to_zero:
+ roundIncrement = 0;
+ break;
+ case float_round_up:
+ roundIncrement = zSign ? 0 : 0x7f;
+ break;
+ case float_round_down:
+ roundIncrement = zSign ? 0x7f : 0;
+ break;
+ default:
+ abort();
+ }
+ roundBits = absZ & 0x7F;
+
+ absZ = ( absZ + roundIncrement )>>7;
+ absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
+ z = absZ;
+ if ( zSign ) z = - z;
+
+ if ( ( absZ>>16 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
+ float_raise(float_flag_invalid, status);
+ return zSign ? (int16_t) 0x8000 : 0x7FFF;
+ }
+ if (roundBits) {
+ status->float_exception_flags |= float_flag_inexact;
+ }
+ return z;
+
+}
+
/*----------------------------------------------------------------------------
| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
| and 7, and returns the properly rounded 32-bit integer corresponding to the
@@ -4509,6 +4565,48 @@ int float16_unordered_quiet(float16 a, float16 b, float_status *status)
return 0;
}
+/*----------------------------------------------------------------------------
+| Returns the result of converting the half-precision floating-point value
+| `a' to the 16-bit two's complement integer format. The conversion is
+| performed according to the IEC/IEEE Standard for Binary Floating-Point
+| Arithmetic---which means in particular that the conversion is rounded
+| according to the current rounding mode. If `a' is a NaN, the largest
+| positive integer is returned. Otherwise, if the conversion overflows, the
+| largest integer with the same sign as `a' is returned.
+*----------------------------------------------------------------------------*/
+
+int16_t float16_to_int16(float32 a, float_status *status)
+{
+ flag aSign;
+ int aExp;
+ uint32_t aSig;
+
+ a = float16_squash_input_denormal(a, status);
+ aSig = extractFloat16Frac( a );
+ aExp = extractFloat16Exp( a );
+ aSign = extractFloat16Sign( a );
+ if ( ( aExp == 0x1F ) && aSig ) aSign = 0;
+ if ( aExp ) aSig |= 0x0400; /* implicit bit */
+
+ /* At this point the binary point is between 10:9, we need to
+ * shift the significand it up by the +ve exponent to get the
+ * integer and then move the binary point down to the 7:6 for
+ * the final roundAnPackInt16.
+ *
+ * Even with the maximum +ve shift everything happily fits in the
+ * 32 bit aSig.
+ */
+ aExp -= 15; /* exp bias */
+ if (aExp >= 3) {
+ aSig <<= aExp - 3;
+ } else {
+ /* ensure small numbers still get rounded */
+ shift32RightJamming( aSig, 3 - aExp, &aSig );
+ }
+
+ return roundAndPackInt16(aSign, aSig, status);
+}
+
/* Half precision floats come in two formats: standard IEEE and "ARM" format.
The latter gains extra exponent range by omitting the NaN/Inf encodings. */
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 856f67cf12..49517b19ea 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -338,6 +338,7 @@ static inline float64 uint16_to_float64(uint16_t v, float_status *status)
| Software half-precision conversion routines.
*----------------------------------------------------------------------------*/
float16 float32_to_float16(float32, flag, float_status *status);
+int16_t float16_to_int16(float32 a, float_status *status);
float32 float16_to_float32(float16, flag, float_status *status);
float16 float64_to_float16(float64 a, flag ieee, float_status *status);
float64 float16_to_float64(float16 a, flag ieee, float_status *status);
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (27 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 28/30] softfloat: float16_to_int16 conversion Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc Alex Bennée
` (3 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
tests/test-softfloat.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/tests/test-softfloat.c b/tests/test-softfloat.c
index d7b740e1cb..e1f356572d 100644
--- a/tests/test-softfloat.c
+++ b/tests/test-softfloat.c
@@ -16,6 +16,31 @@ typedef struct {
uint8_t final_exception_flags;
} f16_test_data;
+static void test_f16_convert_to_int(void)
+{
+ int i;
+ float16 out;
+ float_status flags, *fp = &flags;
+ f16_test_data test_data[] = {
+ /* from risu fcvtps v23.4h, v16.4h */
+ { { .float_rounding_mode = float_round_up}, 0xa619, 0xb860, 0 },
+ { { .float_rounding_mode = float_round_up}, 0x83c0, 0xff91, 0 },
+ { { .float_rounding_mode = float_round_up}, 0x6966, 0x0001, 0 },
+ { { .float_rounding_mode = float_round_up}, 0x06b1, 0x0001, 0 },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(test_data); ++i) {
+ flags = test_data[i].initial_status;
+ out = float16_to_int16(test_data[i].in, fp);
+
+ if (!(test_data[i].out == out)) {
+ fprintf(stderr, "%s[%d]: expected %#04x got %#04x\n",
+ __func__, i, test_data[i].out, out);
+ g_test_fail();
+ }
+ }
+}
+
static void test_f16_round_to_int(void)
{
int i;
@@ -54,5 +79,6 @@ int main(int argc, char *argv[])
{
g_test_init(&argc, &argv, NULL);
g_test_add_func("/softfloat/f16/round_to_int", test_f16_round_to_int);
+ g_test_add_func("/softfloat/f16/convert_to_int", test_f16_convert_to_int);
return g_test_run();
}
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (28 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 29/30] tests/test-softfloat: add f16_to_int16 conversion test Alex Bennée
@ 2017-10-13 16:24 ` Alex Bennée
2017-10-13 16:58 ` [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) no-reply
` (2 subsequent siblings)
32 siblings, 0 replies; 59+ messages in thread
From: Alex Bennée @ 2017-10-13 16:24 UTC (permalink / raw)
To: richard.henderson; +Cc: peter.maydell, qemu-devel, qemu-arm, Alex Bennée
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper-a64.c | 20 ++++++++++++++++++++
target/arm/helper-a64.h | 1 +
target/arm/translate-a64.c | 7 +++++++
3 files changed, 28 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 63b2bbd4b2..1cc2758eac 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -639,3 +639,23 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
float16 f1 = float16_abs(b);
return -float16_lt(f1, f0, fpst);
}
+
+/*
+ * Half-precision floating point conversion functions
+ *
+ * There are a multitude of conversion functions with various
+ * different rounding modes. This is dealt with by the calling code
+ * setting the mode appropriately before calling the helper.
+ */
+
+uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+{
+ float_status *fpst = fpstp;
+
+ /* Invalid if we are passed a NaN */
+ if (float16_is_any_nan(a)) {
+ float_raise(float_flag_invalid, fpst);
+ return 0;
+ }
+ return float16_to_int16(a, fpst);
+}
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
index ce36d81091..73a985d1a4 100644
--- a/target/arm/helper-a64.h
+++ b/target/arm/helper-a64.h
@@ -60,3 +60,4 @@ DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr)
DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr)
DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
+DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bbc0d96f01..ac71911a1a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -10620,6 +10620,10 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
need_rmode = true;
rmode = FPROUNDING_POSINF;
break;
+ case 0x2a: /* FCVTPS */
+ need_rmode = true;
+ rmode = FPROUNDING_POSINF;
+ break;
default:
fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
g_assert_not_reached();
@@ -10647,6 +10651,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
switch (fpop) {
+ case 0x2a: /* FCVTPS */
+ gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
+ break;
case 0x28: /* FRINTP */
gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
break;
--
2.14.1
^ permalink raw reply related [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (29 preceding siblings ...)
2017-10-13 16:24 ` [Qemu-devel] [RFC PATCH 30/30] target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc Alex Bennée
@ 2017-10-13 16:58 ` no-reply
2017-10-13 16:59 ` no-reply
2017-10-17 2:34 ` Richard Henderson
32 siblings, 0 replies; 59+ messages in thread
From: no-reply @ 2017-10-13 16:58 UTC (permalink / raw)
To: alex.bennee; +Cc: famz, richard.henderson, peter.maydell, qemu-arm, qemu-devel
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Type: series
Message-id: 20171013162438.32458-1-alex.bennee@linaro.org
Subject: [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress)
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-quick@centos6
time make docker-test-build@min-glib
time make docker-test-mingw@fedora
time make docker-test-block@fedora
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/20171012095319.136610-1-vsementsov@virtuozzo.com -> patchew/20171012095319.136610-1-vsementsov@virtuozzo.com
* [new tag] patchew/20171013162438.32458-1-alex.bennee@linaro.org -> patchew/20171013162438.32458-1-alex.bennee@linaro.org
Switched to a new branch 'test'
a8d9e2a127 target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc
e47972bdb3 tests/test-softfloat: add f16_to_int16 conversion test
a60d18c62d softfloat: float16_to_int16 conversion
bfdf06e71c target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc
9743fd4234 tests/test-softfloat: add a simple test framework
c00f720eaa softfloat: float16_round_to_int
210fa92599 disas_simd_indexed: support half-precision operations
1ad1d7e5a4 softfloat: add float16_rem and float16_muladd (!CHECK)
13cc912be0 target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same
eae9498170 target/arm/translate-a64: add FP16 2-reg misc compare (zero)
3bd8bfc5fa softfloat: half-precision compare functions
6d48002215 Fix mask for AdvancedSIMD 2 reg misc
e2560b1cc1 target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton
fd8d37dc6b target/arm/translate-a64.c: add FP16 FMULX
023a4abddd target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub)
a484840d45 softfloat: half-precision add/sub/mul/div support
e708f32268 softfloat: 16 bit helpers for shr, clz and rounding and packing
2f65402d6d target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode
76387c084b target/arm/translate-a64.c: handle_3same_64 comment fix
4b10ff1a59 target/arm: implement half-precision F(MIN|MAX)(V|NMV)
ebbf91f0d9 softfloat: improve comments on ARM NaN propagation
c69770519b softfloat: propagate signalling NaNs in MINMAX
beeb3d9188 softfloat: add half-precision expansions for MINMAX fns
8db446be24 fpu/softfloat: implement float16_abs helper
97b4ec2f26 fpu/softfloat: implement float16_squash_input_denormal
fcac6b5acb softfloat: implement propagateFloat16NaN
cc5f898f35 target/arm/cpu.h: update comment for half-precision values
a3fa9b0170 include/exec/helper-head.h: support f16 in helper calls
a37d42107d arm: introduce ARM_V8_FP16 feature bit
e8c0401452 linux-user/main: support dfilter
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-9a_nc8id/src/dtc'...
Submodule path 'dtc': checked out '558cd81bdd432769b59bff01240c44f82cfb1a9d'
BUILD centos6
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-9a_nc8id/src'
GEN docker-src.2017-10-13-12.55.25.5914/qemu.tar
COPY RUNNER
RUN test-quick in qemu:centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
bison-2.4.1-5.el6.x86_64
bzip2-devel-1.0.5-7.el6_0.x86_64
ccache-3.1.6-2.el6.x86_64
csnappy-devel-0-6.20150729gitd7bc683.el6.x86_64
flex-2.5.35-9.el6.x86_64
gcc-4.4.7-18.el6.x86_64
gettext-0.17-18.el6.x86_64
git-1.7.1-9.el6_9.x86_64
glib2-devel-2.28.8-9.el6.x86_64
libepoxy-devel-1.2-3.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
librdmacm-devel-1.0.21-0.el6.x86_64
lzo-devel-2.03-3.1.el6_5.1.x86_64
make-3.81-23.el6.x86_64
mesa-libEGL-devel-11.0.7-4.el6.x86_64
mesa-libgbm-devel-11.0.7-4.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
spice-glib-devel-0.26-8.el6.x86_64
spice-server-devel-0.12.4-16.el6.x86_64
tar-1.23-15.el6_8.x86_64
vte-devel-0.25.1-9.el6.x86_64
xen-devel-4.6.6-2.el6.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=bison bzip2-devel ccache csnappy-devel flex g++ gcc gettext git glib2-devel libepoxy-devel libfdt-devel librdmacm-devel lzo-devel make mesa-libEGL-devel mesa-libgbm-devel pixman-devel SDL-devel spice-glib-devel spice-server-devel tar vte-devel xen-devel zlib-devel
HOSTNAME=f2e07f80306c
TERM=xterm
MAKEFLAGS= -j8
J=8
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
PATH=/usr/lib/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
FEATURES= dtc
DEBUG=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install
No C++ compiler available; disabling C++ specific optional code
Install prefix /tmp/qemu-test/install
BIOS directory /tmp/qemu-test/install/share/qemu
firmware path /tmp/qemu-test/install/share/qemu-firmware
binary directory /tmp/qemu-test/install/bin
library directory /tmp/qemu-test/install/lib
module directory /tmp/qemu-test/install/lib/qemu
libexec directory /tmp/qemu-test/install/libexec
include directory /tmp/qemu-test/install/include
config directory /tmp/qemu-test/install/etc
local state directory /tmp/qemu-test/install/var
Manual directory /tmp/qemu-test/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src
C compiler cc
Host C compiler cc
C++ compiler
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -DNCURSES_WIDECHAR -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all -I/usr/include/libpng12 -I/usr/include/libdrm -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/nss3 -I/usr/include/nspr4 -I/usr/include/spice-1
LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (1.2.14)
GTK support yes (2.24.23)
GTK GL support no
VTE support yes (0.25.1)
TLS priority NORMAL
GNUTLS support no
GNUTLS rnd no
libgcrypt no
libgcrypt kdf no
nettle no
nettle kdf no
libtasn1 no
curses support yes
virgl support no
curl support no
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
Multipath support no
VNC support yes
VNC SASL support no
VNC JPEG support yes
VNC PNG support yes
xen support yes
xen ctrl version 40600
pv dom build no
brlapi support no
bluez support no
Documentation no
PIE yes
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
TCG support yes
TCG debug enabled no
TCG interpreter no
RDMA support yes
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
vhost-user support yes
Trace backends log
spice support yes (0.12.6/0.12.4)
rbd support no
xfsctl support no
smartcard support yes
libusb no
usb net redir no
OpenGL support yes
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough yes
QOM debugging yes
Live block migration yes
lzo support yes
snappy support no
bzip2 support yes
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
mkdir -p dtc/libfdt
GEN x86_64-softmmu/config-devices.mak.tmp
mkdir -p dtc/tests
GEN aarch64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-visit.h
GEN qapi-types.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN qmp-marshal.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN hw/ide/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN accel/tcg/trace.h
GEN accel/kvm/trace.h
GEN nbd/trace.h
GEN scsi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN hw/ide/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN accel/tcg/trace.c
GEN accel/kvm/trace.c
GEN nbd/trace.c
GEN scsi/trace.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
LEX convert-dtsv0-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/srcpos.c
BISON dtc-parser.tab.c
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qmp-introspect.o
GEN qga/qapi-generated/qga-qapi-types.c
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qnum.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qlit.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-posix.o
CC util/compatfd.o
CC util/event_notifier-posix.o
CC util/mmap-alloc.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/bitops.o
CC util/acl.o
CC util/cacheinfo.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/pagesize.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC util/stats64.o
CC util/systemd.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC migration/trace.o
CC io/trace.o
CC block/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC hw/ide/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC accel/tcg/trace.o
CC accel/kvm/trace.o
CC nbd/trace.o
CC scsi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/change-state-handler.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/qmp_pc_dimm.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC stubs/pci-host-piix.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-posix.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC scsi/utils.o
CC scsi/pr-manager.o
CC scsi/pr-manager-helper.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-glib.o
CC crypto/hmac.o
CC crypto/hmac-glib.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/random-platform.o
CC crypto/pbkdf.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC qemu-io.o
CC scsi/qemu-pr-helper.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC bootdevice.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/spiceaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/rng-random.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC chardev/spice.o
CC disas/arm.o
CC disas/i386.o
CC fsdev/qemu-fsdev-dummy.o
CC fsdev/qemu-fsdev-throttle.o
CC fsdev/qemu-fsdev-opts.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/xen_disk.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/xen_console.o
CC hw/char/cadence_uart.o
CC hw/char/cmsdk-apb-uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/nmi.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/xenfb.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/tc6393xb.o
CC hw/display/qxl.o
CC hw/display/qxl-logger.o
CC hw/display/qxl-render.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/edu.o
CC hw/misc/unimp.o
CC hw/misc/arm_l2x0.o
CC hw/misc/a9scu.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/arm11scu.o
CC hw/net/xen_nic.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/ftgmac100.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_pci_bridge.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/mss-spi.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/cmsdk-apb-timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/mss-timer.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_passthrough.o
CC hw/tpm/tpm_util.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-xhci-nec.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/ccid-card-passthru.o
CC hw/usb/ccid-card-emulated.o
CC hw/usb/dev-mtp.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_aspeed.o
CC hw/xen/xen_backend.o
CC hw/xen/xen_devconfig.o
CC hw/xen/xen_pvdev.o
CC hw/xen/xen-common.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/channel.o
CC migration/savevm.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/vmstate-types.o
CC migration/page_cache.o
CC migration/qemu-file.o
CC migration/global_state.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/rdma.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/vhost-user.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC net/tap.o
CC net/tap-linux.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
/tmp/qemu-test/src/replay/replay-internal.c: In function 'replay_put_array':
/tmp/qemu-test/src/replay/replay-internal.c:65: warning: ignoring return value of 'fwrite', declared with attribute warn_unused_result
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_output.o
CC slirp/tcp_input.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
/tmp/qemu-test/src/slirp/tcp_input.c: In function 'tcp_input':
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_p' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_len' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_tos' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_id' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_off' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_ttl' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_sum' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_src.s_addr' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_dst.s_addr' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:220: warning: 'save_ip6.ip_nh' may be used uninitialized in this function
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-legacy.o
CC ui/input-keymap.o
CC ui/input-linux.o
CC ui/spice-core.o
CC ui/spice-input.o
CC ui/spice-display.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/x_keymap.o
CC ui/curses.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
CC ui/shader.o
VERT ui/shader/texture-blit-vert.h
FRAG ui/shader/texture-blit-frag.h
CC ui/egl-helpers.o
CC ui/egl-context.o
CC ui/gtk-egl.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-fe.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-parallel.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-socket.o
CC chardev/char-serial.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
LINK tests/qemu-iotests/socket_scm_helper
CC qga/commands.o
In file included from /usr/include/gtk-2.0/gtk/gtk.h:234,
from /tmp/qemu-test/src/include/ui/gtk.h:9,
from /tmp/qemu-test/src/ui/gtk-egl.c:20:
/usr/include/gtk-2.0/gtk/gtkitemfactory.h:47: warning: function declaration isn't a prototype
In file included from /usr/include/gtk-2.0/gtk/gtk.h:234,
from /tmp/qemu-test/src/include/ui/gtk.h:9,
from /tmp/qemu-test/src/ui/gtk.c:42:
/usr/include/gtk-2.0/gtk/gtkitemfactory.h:47: warning: function declaration isn't a prototype
CC qga/guest-agent-command-state.o
CC qga/main.o
AS optionrom/multiboot.o
AS optionrom/linuxboot.o
CC optionrom/linuxboot_dma.o
cc: unrecognized option '-no-integrated-as'
AS optionrom/kvmvapic.o
CC qga/commands-posix.o
BUILD optionrom/multiboot.img
BUILD optionrom/linuxboot.img
BUILD optionrom/linuxboot_dma.img
BUILD optionrom/kvmvapic.img
BUILD optionrom/multiboot.raw
BUILD optionrom/linuxboot.raw
CC qga/channel-posix.o
BUILD optionrom/linuxboot_dma.raw
CC qga/qapi-generated/qga-qapi-types.o
BUILD optionrom/kvmvapic.raw
SIGN optionrom/multiboot.bin
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
SIGN optionrom/linuxboot.bin
SIGN optionrom/linuxboot_dma.bin
SIGN optionrom/kvmvapic.bin
AR libqemuutil.a
CC qemu-img.o
LINK qemu-io
LINK scsi/qemu-pr-helper
LINK qemu-bridge-helper
CC ui/console-gl.o
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-ga
GEN aarch64-softmmu/hmp-commands.h
GEN aarch64-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/config-target.h
CC aarch64-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/exec.o
CC aarch64-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/optimize.o
CC aarch64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/tcg/tcg-common.o
GEN x86_64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/config-target.h
CC x86_64-softmmu/exec.o
CC x86_64-softmmu/tcg/tcg.o
CC aarch64-softmmu/disas.o
GEN aarch64-softmmu/gdbstub-xml.c
CC aarch64-softmmu/arch_init.o
CC aarch64-softmmu/cpus.o
CC x86_64-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/monitor.o
CC aarch64-softmmu/gdbstub.o
CC x86_64-softmmu/tcg/optimize.o
CC x86_64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/balloon.o
CC x86_64-softmmu/fpu/softfloat.o
CC x86_64-softmmu/disas.o
CC aarch64-softmmu/ioport.o
CC aarch64-softmmu/numa.o
GEN x86_64-softmmu/gdbstub-xml.c
CC x86_64-softmmu/arch_init.o
LINK qemu-img
CC aarch64-softmmu/qtest.o
CC x86_64-softmmu/cpus.o
CC aarch64-softmmu/memory.o
CC aarch64-softmmu/memory_mapping.o
CC aarch64-softmmu/dump.o
CC aarch64-softmmu/migration/ram.o
CC aarch64-softmmu/accel/accel.o
CC x86_64-softmmu/monitor.o
CC aarch64-softmmu/accel/stubs/hax-stub.o
CC aarch64-softmmu/accel/stubs/kvm-stub.o
CC aarch64-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/gdbstub.o
CC aarch64-softmmu/accel/tcg/cputlb.o
CC aarch64-softmmu/accel/tcg/tcg-runtime.o
CC aarch64-softmmu/accel/tcg/cpu-exec.o
CC aarch64-softmmu/accel/tcg/cpu-exec-common.o
CC x86_64-softmmu/balloon.o
CC aarch64-softmmu/accel/tcg/translate-all.o
CC aarch64-softmmu/accel/tcg/translator.o
CC x86_64-softmmu/ioport.o
CC aarch64-softmmu/hw/adc/stm32f2xx_adc.o
CC x86_64-softmmu/numa.o
CC aarch64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/qtest.o
CC x86_64-softmmu/memory.o
CC x86_64-softmmu/memory_mapping.o
CC x86_64-softmmu/dump.o
CC aarch64-softmmu/hw/block/dataplane/virtio-blk.o
CC x86_64-softmmu/migration/ram.o
CC x86_64-softmmu/accel/accel.o
CC x86_64-softmmu/accel/kvm/kvm-all.o
CC x86_64-softmmu/accel/stubs/hax-stub.o
CC aarch64-softmmu/hw/char/exynos4210_uart.o
CC x86_64-softmmu/accel/tcg/tcg-all.o
CC x86_64-softmmu/accel/tcg/cputlb.o
CC x86_64-softmmu/accel/tcg/tcg-runtime.o
CC x86_64-softmmu/accel/tcg/cpu-exec.o
CC aarch64-softmmu/hw/char/omap_uart.o
CC aarch64-softmmu/hw/char/digic-uart.o
CC aarch64-softmmu/hw/char/stm32f2xx_usart.o
CC aarch64-softmmu/hw/char/bcm2835_aux.o
CC x86_64-softmmu/accel/tcg/cpu-exec-common.o
CC x86_64-softmmu/accel/tcg/translate-all.o
CC aarch64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/accel/tcg/translator.o
CC x86_64-softmmu/hw/block/virtio-blk.o
CC x86_64-softmmu/hw/block/dataplane/virtio-blk.o
CC x86_64-softmmu/hw/char/virtio-serial-bus.o
CC x86_64-softmmu/hw/core/generic-loader.o
CC aarch64-softmmu/hw/core/generic-loader.o
CC x86_64-softmmu/hw/core/null-machine.o
CC aarch64-softmmu/hw/core/null-machine.o
CC x86_64-softmmu/hw/display/vga.o
CC aarch64-softmmu/hw/cpu/arm11mpcore.o
CC aarch64-softmmu/hw/cpu/realview_mpcore.o
CC aarch64-softmmu/hw/cpu/a9mpcore.o
CC aarch64-softmmu/hw/cpu/a15mpcore.o
CC aarch64-softmmu/hw/display/omap_dss.o
CC aarch64-softmmu/hw/display/omap_lcdc.o
CC aarch64-softmmu/hw/display/pxa2xx_lcd.o
CC aarch64-softmmu/hw/display/bcm2835_fb.o
CC aarch64-softmmu/hw/display/vga.o
CC x86_64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/display/virtio-gpu.o
CC aarch64-softmmu/hw/display/virtio-gpu-3d.o
CC aarch64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/hw/display/dpcd.o
CC aarch64-softmmu/hw/display/xlnx_dp.o
CC aarch64-softmmu/hw/dma/xlnx_dpdma.o
CC aarch64-softmmu/hw/dma/omap_dma.o
CC aarch64-softmmu/hw/dma/soc_dma.o
CC aarch64-softmmu/hw/dma/pxa2xx_dma.o
CC aarch64-softmmu/hw/dma/bcm2835_dma.o
CC x86_64-softmmu/hw/display/virtio-gpu-3d.o
CC aarch64-softmmu/hw/gpio/omap_gpio.o
CC aarch64-softmmu/hw/gpio/imx_gpio.o
CC aarch64-softmmu/hw/gpio/bcm2835_gpio.o
CC aarch64-softmmu/hw/i2c/omap_i2c.o
CC aarch64-softmmu/hw/input/pxa2xx_keypad.o
CC aarch64-softmmu/hw/input/tsc210x.o
CC aarch64-softmmu/hw/intc/armv7m_nvic.o
CC x86_64-softmmu/hw/display/virtio-gpu-pci.o
CC aarch64-softmmu/hw/intc/exynos4210_gic.o
CC aarch64-softmmu/hw/intc/exynos4210_combiner.o
CC aarch64-softmmu/hw/intc/omap_intc.o
CC aarch64-softmmu/hw/intc/bcm2835_ic.o
CC aarch64-softmmu/hw/intc/bcm2836_control.o
CC aarch64-softmmu/hw/intc/allwinner-a10-pic.o
CC aarch64-softmmu/hw/intc/aspeed_vic.o
CC x86_64-softmmu/hw/display/virtio-vga.o
CC aarch64-softmmu/hw/intc/arm_gicv3_cpuif.o
CC aarch64-softmmu/hw/misc/ivshmem.o
CC aarch64-softmmu/hw/misc/arm_sysctl.o
CC aarch64-softmmu/hw/misc/cbus.o
CC aarch64-softmmu/hw/misc/exynos4210_pmu.o
CC aarch64-softmmu/hw/misc/exynos4210_clk.o
CC x86_64-softmmu/hw/intc/apic.o
CC aarch64-softmmu/hw/misc/exynos4210_rng.o
CC aarch64-softmmu/hw/misc/imx_ccm.o
CC aarch64-softmmu/hw/misc/imx31_ccm.o
CC aarch64-softmmu/hw/misc/imx25_ccm.o
CC aarch64-softmmu/hw/misc/imx6_ccm.o
CC aarch64-softmmu/hw/misc/imx6_src.o
CC aarch64-softmmu/hw/misc/mst_fpga.o
CC aarch64-softmmu/hw/misc/omap_clk.o
CC aarch64-softmmu/hw/misc/omap_gpmc.o
CC aarch64-softmmu/hw/misc/omap_l4.o
CC aarch64-softmmu/hw/misc/omap_sdrc.o
CC aarch64-softmmu/hw/misc/omap_tap.o
CC aarch64-softmmu/hw/misc/bcm2835_mbox.o
CC x86_64-softmmu/hw/intc/apic_common.o
CC aarch64-softmmu/hw/misc/bcm2835_property.o
CC aarch64-softmmu/hw/misc/bcm2835_rng.o
CC x86_64-softmmu/hw/intc/ioapic.o
CC aarch64-softmmu/hw/misc/zynq_slcr.o
CC aarch64-softmmu/hw/misc/zynq-xadc.o
CC aarch64-softmmu/hw/misc/stm32f2xx_syscfg.o
CC x86_64-softmmu/hw/isa/lpc_ich9.o
CC x86_64-softmmu/hw/misc/vmport.o
CC aarch64-softmmu/hw/misc/mps2-scc.o
CC x86_64-softmmu/hw/misc/ivshmem.o
CC x86_64-softmmu/hw/misc/pvpanic.o
CC x86_64-softmmu/hw/misc/hyperv_testdev.o
CC x86_64-softmmu/hw/misc/mmio_interface.o
CC aarch64-softmmu/hw/misc/auxbus.o
CC aarch64-softmmu/hw/misc/aspeed_scu.o
CC x86_64-softmmu/hw/net/virtio-net.o
CC x86_64-softmmu/hw/net/vhost_net.o
CC x86_64-softmmu/hw/scsi/virtio-scsi.o
CC x86_64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC x86_64-softmmu/hw/scsi/vhost-scsi-common.o
CC x86_64-softmmu/hw/scsi/vhost-scsi.o
CC aarch64-softmmu/hw/misc/aspeed_sdmc.o
CC x86_64-softmmu/hw/scsi/vhost-user-scsi.o
CC x86_64-softmmu/hw/timer/mc146818rtc.o
CC x86_64-softmmu/hw/vfio/common.o
CC x86_64-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/misc/mmio_interface.o
CC x86_64-softmmu/hw/vfio/pci-quirks.o
CC x86_64-softmmu/hw/vfio/platform.o
CC x86_64-softmmu/hw/vfio/spapr.o
CC aarch64-softmmu/hw/misc/msf2-sysreg.o
CC x86_64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/net/virtio-net.o
CC x86_64-softmmu/hw/virtio/virtio-balloon.o
CC x86_64-softmmu/hw/virtio/vhost.o
CC x86_64-softmmu/hw/virtio/vhost-backend.o
CC x86_64-softmmu/hw/virtio/vhost-user.o
CC aarch64-softmmu/hw/net/vhost_net.o
CC x86_64-softmmu/hw/virtio/vhost-vsock.o
CC x86_64-softmmu/hw/virtio/virtio-crypto.o
CC x86_64-softmmu/hw/virtio/virtio-crypto-pci.o
CC x86_64-softmmu/hw/xen/xen-host-pci-device.o
CC x86_64-softmmu/hw/xen/xen_pt.o
CC aarch64-softmmu/hw/pcmcia/pxa2xx.o
CC x86_64-softmmu/hw/xen/xen_pt_config_init.o
CC x86_64-softmmu/hw/xen/xen_pt_graphics.o
CC x86_64-softmmu/hw/xen/xen_pt_msi.o
CC x86_64-softmmu/hw/i386/multiboot.o
CC x86_64-softmmu/hw/i386/pc.o
CC aarch64-softmmu/hw/scsi/virtio-scsi.o
CC x86_64-softmmu/hw/i386/pc_piix.o
CC x86_64-softmmu/hw/i386/pc_q35.o
CC aarch64-softmmu/hw/scsi/virtio-scsi-dataplane.o
CC x86_64-softmmu/hw/i386/pc_sysfw.o
CC x86_64-softmmu/hw/i386/x86-iommu.o
CC x86_64-softmmu/hw/i386/intel_iommu.o
CC aarch64-softmmu/hw/scsi/vhost-scsi-common.o
CC aarch64-softmmu/hw/scsi/vhost-scsi.o
/tmp/qemu-test/src/hw/i386/pc_piix.c: In function 'igd_passthrough_isa_bridge_create':
/tmp/qemu-test/src/hw/i386/pc_piix.c:1071: warning: 'pch_rev_id' may be used uninitialized in this function
CC aarch64-softmmu/hw/scsi/vhost-user-scsi.o
CC x86_64-softmmu/hw/i386/amd_iommu.o
CC aarch64-softmmu/hw/sd/omap_mmc.o
CC aarch64-softmmu/hw/sd/pxa2xx_mmci.o
CC aarch64-softmmu/hw/sd/bcm2835_sdhost.o
CC aarch64-softmmu/hw/ssi/omap_spi.o
CC aarch64-softmmu/hw/ssi/imx_spi.o
CC aarch64-softmmu/hw/timer/exynos4210_mct.o
CC aarch64-softmmu/hw/timer/exynos4210_pwm.o
CC aarch64-softmmu/hw/timer/exynos4210_rtc.o
CC aarch64-softmmu/hw/timer/omap_gptimer.o
CC aarch64-softmmu/hw/timer/omap_synctimer.o
CC aarch64-softmmu/hw/timer/pxa2xx_timer.o
CC aarch64-softmmu/hw/timer/digic-timer.o
CC aarch64-softmmu/hw/timer/allwinner-a10-pit.o
CC aarch64-softmmu/hw/usb/tusb6010.o
CC aarch64-softmmu/hw/vfio/common.o
CC aarch64-softmmu/hw/vfio/pci.o
CC aarch64-softmmu/hw/vfio/pci-quirks.o
CC aarch64-softmmu/hw/vfio/platform.o
CC aarch64-softmmu/hw/vfio/calxeda-xgmac.o
CC aarch64-softmmu/hw/vfio/amd-xgbe.o
CC aarch64-softmmu/hw/vfio/spapr.o
CC aarch64-softmmu/hw/virtio/virtio.o
CC aarch64-softmmu/hw/virtio/virtio-balloon.o
CC x86_64-softmmu/hw/i386/kvmvapic.o
CC aarch64-softmmu/hw/virtio/vhost.o
CC aarch64-softmmu/hw/virtio/vhost-backend.o
CC aarch64-softmmu/hw/virtio/vhost-user.o
CC x86_64-softmmu/hw/i386/acpi-build.o
CC aarch64-softmmu/hw/virtio/vhost-vsock.o
CC aarch64-softmmu/hw/virtio/virtio-crypto.o
CC aarch64-softmmu/hw/virtio/virtio-crypto-pci.o
CC aarch64-softmmu/hw/arm/boot.o
CC x86_64-softmmu/hw/i386/pci-assign-load-rom.o
CC aarch64-softmmu/hw/arm/collie.o
CC x86_64-softmmu/hw/i386/../xenpv/xen_machine_pv.o
CC x86_64-softmmu/hw/i386/kvm/clock.o
CC aarch64-softmmu/hw/arm/exynos4_boards.o
/tmp/qemu-test/src/hw/i386/acpi-build.c: In function 'build_append_pci_bus_devices':
/tmp/qemu-test/src/hw/i386/acpi-build.c:509: warning: 'notify_method' may be used uninitialized in this function
CC aarch64-softmmu/hw/arm/gumstix.o
CC x86_64-softmmu/hw/i386/kvm/apic.o
CC x86_64-softmmu/hw/i386/kvm/i8259.o
CC x86_64-softmmu/hw/i386/kvm/ioapic.o
CC aarch64-softmmu/hw/arm/highbank.o
CC aarch64-softmmu/hw/arm/digic_boards.o
CC aarch64-softmmu/hw/arm/integratorcp.o
CC aarch64-softmmu/hw/arm/mainstone.o
CC x86_64-softmmu/hw/i386/kvm/i8254.o
CC x86_64-softmmu/hw/i386/kvm/pci-assign.o
CC x86_64-softmmu/hw/i386/xen/xen_platform.o
CC x86_64-softmmu/hw/i386/xen/xen_apic.o
CC aarch64-softmmu/hw/arm/musicpal.o
CC aarch64-softmmu/hw/arm/nseries.o
CC aarch64-softmmu/hw/arm/omap_sx1.o
CC aarch64-softmmu/hw/arm/palm.o
CC x86_64-softmmu/hw/i386/xen/xen_pvdevice.o
CC x86_64-softmmu/hw/i386/xen/xen-hvm.o
CC x86_64-softmmu/hw/i386/xen/xen-mapcache.o
CC x86_64-softmmu/target/i386/helper.o
CC aarch64-softmmu/hw/arm/realview.o
CC aarch64-softmmu/hw/arm/spitz.o
CC aarch64-softmmu/hw/arm/stellaris.o
CC aarch64-softmmu/hw/arm/tosa.o
CC x86_64-softmmu/target/i386/cpu.o
CC x86_64-softmmu/target/i386/gdbstub.o
CC aarch64-softmmu/hw/arm/versatilepb.o
CC aarch64-softmmu/hw/arm/vexpress.o
CC x86_64-softmmu/target/i386/xsave_helper.o
CC x86_64-softmmu/target/i386/translate.o
CC x86_64-softmmu/target/i386/bpt_helper.o
CC x86_64-softmmu/target/i386/cc_helper.o
CC aarch64-softmmu/hw/arm/virt.o
CC aarch64-softmmu/hw/arm/xilinx_zynq.o
CC aarch64-softmmu/hw/arm/z2.o
CC aarch64-softmmu/hw/arm/virt-acpi-build.o
CC x86_64-softmmu/target/i386/excp_helper.o
CC aarch64-softmmu/hw/arm/netduino2.o
CC aarch64-softmmu/hw/arm/sysbus-fdt.o
CC x86_64-softmmu/target/i386/fpu_helper.o
CC x86_64-softmmu/target/i386/int_helper.o
CC aarch64-softmmu/hw/arm/armv7m.o
CC x86_64-softmmu/target/i386/mem_helper.o
CC aarch64-softmmu/hw/arm/exynos4210.o
CC aarch64-softmmu/hw/arm/pxa2xx.o
CC aarch64-softmmu/hw/arm/pxa2xx_gpio.o
CC x86_64-softmmu/target/i386/misc_helper.o
CC aarch64-softmmu/hw/arm/pxa2xx_pic.o
CC aarch64-softmmu/hw/arm/digic.o
CC x86_64-softmmu/target/i386/mpx_helper.o
CC x86_64-softmmu/target/i386/seg_helper.o
CC aarch64-softmmu/hw/arm/omap1.o
CC aarch64-softmmu/hw/arm/omap2.o
CC x86_64-softmmu/target/i386/smm_helper.o
CC aarch64-softmmu/hw/arm/strongarm.o
CC x86_64-softmmu/target/i386/svm_helper.o
CC aarch64-softmmu/hw/arm/allwinner-a10.o
CC aarch64-softmmu/hw/arm/cubieboard.o
CC aarch64-softmmu/hw/arm/bcm2835_peripherals.o
CC aarch64-softmmu/hw/arm/bcm2836.o
CC x86_64-softmmu/target/i386/machine.o
CC aarch64-softmmu/hw/arm/raspi.o
CC aarch64-softmmu/hw/arm/stm32f205_soc.o
CC aarch64-softmmu/hw/arm/xlnx-zynqmp.o
CC x86_64-softmmu/target/i386/arch_memory_mapping.o
CC aarch64-softmmu/hw/arm/xlnx-zcu102.o
CC x86_64-softmmu/target/i386/arch_dump.o
CC x86_64-softmmu/target/i386/monitor.o
CC x86_64-softmmu/target/i386/kvm.o
CC aarch64-softmmu/hw/arm/fsl-imx25.o
CC x86_64-softmmu/target/i386/hyperv.o
CC aarch64-softmmu/hw/arm/imx25_pdk.o
CC aarch64-softmmu/hw/arm/fsl-imx31.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/hw/arm/kzm.o
CC aarch64-softmmu/hw/arm/fsl-imx6.o
CC x86_64-softmmu/trace/control-target.o
CC aarch64-softmmu/hw/arm/sabrelite.o
CC aarch64-softmmu/hw/arm/aspeed_soc.o
CC aarch64-softmmu/hw/arm/aspeed.o
CC aarch64-softmmu/hw/arm/mps2.o
CC aarch64-softmmu/hw/arm/msf2-soc.o
CC aarch64-softmmu/hw/arm/msf2-som.o
CC aarch64-softmmu/target/arm/arm-semi.o
CC x86_64-softmmu/gdbstub-xml.o
CC aarch64-softmmu/target/arm/machine.o
CC aarch64-softmmu/target/arm/psci.o
CC x86_64-softmmu/trace/generated-helpers.o
CC aarch64-softmmu/target/arm/arch_dump.o
CC aarch64-softmmu/target/arm/monitor.o
CC aarch64-softmmu/target/arm/kvm-stub.o
CC aarch64-softmmu/target/arm/translate.o
CC aarch64-softmmu/target/arm/op_helper.o
CC aarch64-softmmu/target/arm/helper.o
CC aarch64-softmmu/target/arm/cpu.o
CC aarch64-softmmu/target/arm/neon_helper.o
CC aarch64-softmmu/target/arm/iwmmxt_helper.o
CC aarch64-softmmu/target/arm/gdbstub.o
CC aarch64-softmmu/target/arm/cpu64.o
CC aarch64-softmmu/target/arm/translate-a64.o
CC aarch64-softmmu/target/arm/helper-a64.o
CC aarch64-softmmu/target/arm/gdbstub64.o
CC aarch64-softmmu/target/arm/crypto_helper.o
CC aarch64-softmmu/target/arm/arm-powerctl.o
GEN trace/generated-helpers.c
CC aarch64-softmmu/trace/control-target.o
CC aarch64-softmmu/gdbstub-xml.o
CC aarch64-softmmu/trace/generated-helpers.o
LINK x86_64-softmmu/qemu-system-x86_64
/tmp/qemu-test/src/target/arm/translate-a64.c: In function 'handle_shri_with_rndacc':
/tmp/qemu-test/src/target/arm/translate-a64.c:6409: warning: 'tcg_src_hi' may be used uninitialized in this function
/tmp/qemu-test/src/target/arm/translate-a64.c: In function 'disas_simd_scalar_two_reg_misc':
/tmp/qemu-test/src/target/arm/translate-a64.c:8136: warning: 'rmode' may be used uninitialized in this function
LINK aarch64-softmmu/qemu-system-aarch64
TEST tests/qapi-schema/alternate-any.out
TEST tests/qapi-schema/alternate-array.out
TEST tests/qapi-schema/alternate-base.out
TEST tests/qapi-schema/alternate-clash.out
TEST tests/qapi-schema/alternate-conflict-dict.out
TEST tests/qapi-schema/alternate-conflict-enum-bool.out
TEST tests/qapi-schema/alternate-conflict-enum-int.out
TEST tests/qapi-schema/alternate-conflict-string.out
TEST tests/qapi-schema/alternate-conflict-bool-string.out
TEST tests/qapi-schema/alternate-conflict-num-string.out
TEST tests/qapi-schema/alternate-empty.out
TEST tests/qapi-schema/alternate-unknown.out
TEST tests/qapi-schema/alternate-nested.out
TEST tests/qapi-schema/args-alternate.out
TEST tests/qapi-schema/args-any.out
TEST tests/qapi-schema/args-array-empty.out
TEST tests/qapi-schema/args-array-unknown.out
TEST tests/qapi-schema/args-bad-boxed.out
TEST tests/qapi-schema/args-boxed-anon.out
TEST tests/qapi-schema/args-boxed-empty.out
TEST tests/qapi-schema/args-int.out
TEST tests/qapi-schema/args-boxed-string.out
TEST tests/qapi-schema/args-invalid.out
TEST tests/qapi-schema/args-member-array-bad.out
TEST tests/qapi-schema/args-member-case.out
TEST tests/qapi-schema/args-member-unknown.out
TEST tests/qapi-schema/args-name-clash.out
TEST tests/qapi-schema/args-union.out
TEST tests/qapi-schema/args-unknown.out
TEST tests/qapi-schema/bad-base.out
TEST tests/qapi-schema/bad-data.out
TEST tests/qapi-schema/bad-ident.out
TEST tests/qapi-schema/bad-type-bool.out
TEST tests/qapi-schema/bad-type-dict.out
TEST tests/qapi-schema/bad-type-int.out
TEST tests/qapi-schema/base-cycle-direct.out
TEST tests/qapi-schema/base-cycle-indirect.out
TEST tests/qapi-schema/command-int.out
TEST tests/qapi-schema/comments.out
TEST tests/qapi-schema/doc-bad-alternate-member.out
TEST tests/qapi-schema/doc-bad-command-arg.out
TEST tests/qapi-schema/doc-bad-symbol.out
TEST tests/qapi-schema/doc-bad-union-member.out
TEST tests/qapi-schema/doc-before-include.out
TEST tests/qapi-schema/doc-before-pragma.out
TEST tests/qapi-schema/doc-duplicated-arg.out
TEST tests/qapi-schema/doc-duplicated-return.out
TEST tests/qapi-schema/doc-duplicated-since.out
TEST tests/qapi-schema/doc-empty-arg.out
TEST tests/qapi-schema/doc-empty-section.out
TEST tests/qapi-schema/doc-empty-symbol.out
TEST tests/qapi-schema/doc-good.out
TEST tests/qapi-schema/doc-interleaved-section.out
TEST tests/qapi-schema/doc-invalid-end.out
TEST tests/qapi-schema/doc-invalid-end2.out
TEST tests/qapi-schema/doc-invalid-return.out
TEST tests/qapi-schema/doc-invalid-section.out
TEST tests/qapi-schema/doc-invalid-start.out
TEST tests/qapi-schema/doc-missing.out
TEST tests/qapi-schema/doc-missing-colon.out
TEST tests/qapi-schema/doc-missing-expr.out
TEST tests/qapi-schema/doc-missing-space.out
TEST tests/qapi-schema/doc-no-symbol.out
TEST tests/qapi-schema/double-data.out
TEST tests/qapi-schema/double-type.out
TEST tests/qapi-schema/duplicate-key.out
TEST tests/qapi-schema/empty.out
TEST tests/qapi-schema/enum-bad-name.out
TEST tests/qapi-schema/enum-bad-prefix.out
TEST tests/qapi-schema/enum-clash-member.out
TEST tests/qapi-schema/enum-dict-member.out
TEST tests/qapi-schema/enum-int-member.out
TEST tests/qapi-schema/enum-member-case.out
TEST tests/qapi-schema/enum-missing-data.out
TEST tests/qapi-schema/enum-wrong-data.out
TEST tests/qapi-schema/escape-outside-string.out
TEST tests/qapi-schema/escape-too-short.out
TEST tests/qapi-schema/escape-too-big.out
TEST tests/qapi-schema/event-boxed-empty.out
TEST tests/qapi-schema/event-case.out
TEST tests/qapi-schema/event-nest-struct.out
TEST tests/qapi-schema/flat-union-array-branch.out
TEST tests/qapi-schema/flat-union-bad-base.out
TEST tests/qapi-schema/flat-union-bad-discriminator.out
TEST tests/qapi-schema/flat-union-base-any.out
TEST tests/qapi-schema/flat-union-base-union.out
TEST tests/qapi-schema/flat-union-clash-member.out
TEST tests/qapi-schema/flat-union-empty.out
TEST tests/qapi-schema/flat-union-incomplete-branch.out
TEST tests/qapi-schema/flat-union-inline.out
TEST tests/qapi-schema/flat-union-int-branch.out
TEST tests/qapi-schema/flat-union-invalid-branch-key.out
TEST tests/qapi-schema/flat-union-invalid-discriminator.out
TEST tests/qapi-schema/flat-union-no-base.out
TEST tests/qapi-schema/flat-union-optional-discriminator.out
TEST tests/qapi-schema/flat-union-string-discriminator.out
TEST tests/qapi-schema/funny-char.out
TEST tests/qapi-schema/ident-with-escape.out
TEST tests/qapi-schema/include-before-err.out
TEST tests/qapi-schema/include-cycle.out
TEST tests/qapi-schema/include-extra-junk.out
TEST tests/qapi-schema/include-format-err.out
TEST tests/qapi-schema/include-nested-err.out
TEST tests/qapi-schema/include-no-file.out
TEST tests/qapi-schema/include-non-file.out
TEST tests/qapi-schema/include-relpath.out
TEST tests/qapi-schema/include-repetition.out
TEST tests/qapi-schema/include-self-cycle.out
TEST tests/qapi-schema/include-simple.out
TEST tests/qapi-schema/indented-expr.out
TEST tests/qapi-schema/leading-comma-list.out
TEST tests/qapi-schema/leading-comma-object.out
TEST tests/qapi-schema/missing-colon.out
TEST tests/qapi-schema/missing-comma-list.out
TEST tests/qapi-schema/missing-comma-object.out
TEST tests/qapi-schema/missing-type.out
TEST tests/qapi-schema/nested-struct-data.out
TEST tests/qapi-schema/non-objects.out
TEST tests/qapi-schema/pragma-doc-required-crap.out
TEST tests/qapi-schema/pragma-extra-junk.out
TEST tests/qapi-schema/pragma-name-case-whitelist-crap.out
TEST tests/qapi-schema/pragma-non-dict.out
TEST tests/qapi-schema/pragma-returns-whitelist-crap.out
TEST tests/qapi-schema/qapi-schema-test.out
TEST tests/qapi-schema/redefined-builtin.out
TEST tests/qapi-schema/redefined-command.out
TEST tests/qapi-schema/quoted-structural-chars.out
TEST tests/qapi-schema/redefined-event.out
TEST tests/qapi-schema/redefined-type.out
TEST tests/qapi-schema/reserved-command-q.out
TEST tests/qapi-schema/reserved-enum-q.out
TEST tests/qapi-schema/reserved-member-has.out
TEST tests/qapi-schema/reserved-member-q.out
TEST tests/qapi-schema/reserved-member-u.out
TEST tests/qapi-schema/reserved-member-underscore.out
TEST tests/qapi-schema/reserved-type-kind.out
TEST tests/qapi-schema/reserved-type-list.out
TEST tests/qapi-schema/returns-alternate.out
TEST tests/qapi-schema/returns-array-bad.out
TEST tests/qapi-schema/returns-dict.out
TEST tests/qapi-schema/returns-unknown.out
TEST tests/qapi-schema/returns-whitelist.out
TEST tests/qapi-schema/struct-base-clash-deep.out
TEST tests/qapi-schema/struct-base-clash.out
TEST tests/qapi-schema/struct-data-invalid.out
TEST tests/qapi-schema/struct-member-invalid.out
TEST tests/qapi-schema/trailing-comma-list.out
TEST tests/qapi-schema/trailing-comma-object.out
TEST tests/qapi-schema/type-bypass-bad-gen.out
TEST tests/qapi-schema/unclosed-list.out
TEST tests/qapi-schema/unclosed-object.out
TEST tests/qapi-schema/unclosed-string.out
TEST tests/qapi-schema/unicode-str.out
TEST tests/qapi-schema/union-base-empty.out
TEST tests/qapi-schema/union-base-no-discriminator.out
TEST tests/qapi-schema/union-branch-case.out
TEST tests/qapi-schema/union-clash-branches.out
TEST tests/qapi-schema/union-empty.out
TEST tests/qapi-schema/union-invalid-base.out
TEST tests/qapi-schema/union-optional-branch.out
TEST tests/qapi-schema/union-unknown.out
TEST tests/qapi-schema/unknown-escape.out
TEST tests/qapi-schema/unknown-expr-key.out
GEN tests/qapi-schema/doc-good.test.texi
CC tests/check-qdict.o
CC tests/test-char.o
CC tests/check-qnum.o
CC tests/check-qstring.o
CC tests/check-qlist.o
CC tests/check-qnull.o
CC tests/check-qjson.o
CC tests/check-qlit.o
CC tests/test-qobject-output-visitor.o
GEN tests/test-qapi-visit.c
GEN tests/test-qapi-types.c
GEN tests/test-qapi-event.c
GEN tests/test-qmp-introspect.c
CC tests/test-clone-visitor.o
CC tests/test-qobject-input-visitor.o
CC tests/test-qmp-commands.o
GEN tests/test-qmp-marshal.c
CC tests/test-string-input-visitor.o
CC tests/test-string-output-visitor.o
CC tests/test-qmp-event.o
CC tests/test-opts-visitor.o
CC tests/test-coroutine.o
CC tests/iothread.o
CC tests/test-visitor-serialization.o
CC tests/test-iov.o
CC tests/test-aio.o
CC tests/test-aio-multithread.o
CC tests/test-throttle.o
CC tests/test-thread-pool.o
CC tests/test-hbitmap.o
CC tests/test-blockjob.o
CC tests/test-blockjob-txn.o
CC tests/test-x86-cpuid.o
CC tests/test-xbzrle.o
CC tests/test-vmstate.o
CC tests/test-cutils.o
CC tests/test-shift128.o
CC tests/test-mul64.o
CC tests/test-int128.o
CC tests/rcutorture.o
CC tests/test-rcu-list.o
CC tests/test-qdist.o
CC tests/test-qht.o
/tmp/qemu-test/src/tests/test-int128.c:180: warning: '__noclone__' attribute directive ignored
CC tests/test-qht-par.o
CC tests/qht-bench.o
CC tests/test-bitops.o
CC tests/test-bitcnt.o
CC tests/check-qom-interface.o
CC tests/check-qom-proplist.o
CC tests/test-qemu-opts.o
CC tests/test-keyval.o
CC tests/test-write-threshold.o
CC tests/test-crypto-hash.o
CC tests/test-crypto-hmac.o
CC tests/test-crypto-cipher.o
CC tests/test-crypto-secret.o
CC tests/test-qga.o
CC tests/libqtest.o
CC tests/test-timed-average.o
CC tests/test-io-task.o
CC tests/test-io-channel-socket.o
CC tests/io-channel-helpers.o
CC tests/test-io-channel-file.o
CC tests/test-io-channel-command.o
CC tests/test-io-channel-buffer.o
CC tests/test-base64.o
CC tests/test-crypto-ivgen.o
CC tests/test-crypto-afsplit.o
CC tests/test-crypto-xts.o
CC tests/test-crypto-block.o
CC tests/test-logging.o
CC tests/test-replication.o
CC tests/test-bufferiszero.o
CC tests/test-uuid.o
CC tests/ptimer-test.o
CC tests/ptimer-test-stubs.o
CC tests/test-qapi-util.o
CC tests/test-softfloat.o
CC tests/vhost-user-test.o
/tmp/qemu-test/src/tests/test-softfloat.c: In function 'test_f16_convert_to_int':
/tmp/qemu-test/src/tests/test-softfloat.c:39: warning: implicit declaration of function 'g_test_fail'
/tmp/qemu-test/src/tests/test-softfloat.c:39: warning: nested extern declaration of 'g_test_fail'
CC tests/libqos/pci.o
CC tests/libqos/fw_cfg.o
CC tests/libqos/malloc.o
CC tests/libqos/i2c.o
CC tests/libqos/libqos.o
CC tests/libqos/malloc-spapr.o
CC tests/libqos/libqos-spapr.o
CC tests/libqos/rtas.o
CC tests/libqos/pci-spapr.o
CC tests/libqos/pci-pc.o
CC tests/libqos/malloc-pc.o
CC tests/libqos/libqos-pc.o
CC tests/libqos/ahci.o
CC tests/libqos/virtio.o
CC tests/libqos/virtio-pci.o
CC tests/libqos/virtio-mmio.o
CC tests/libqos/malloc-generic.o
CC tests/endianness-test.o
CC tests/fdc-test.o
CC tests/ide-test.o
CC tests/ahci-test.o
CC tests/hd-geo-test.o
CC tests/boot-order-test.o
CC tests/bios-tables-test.o
CC tests/boot-sector.o
CC tests/acpi-utils.o
CC tests/boot-serial-test.o
CC tests/pxe-test.o
CC tests/rtc-test.o
CC tests/ipmi-kcs-test.o
CC tests/ipmi-bt-test.o
CC tests/i440fx-test.o
CC tests/fw_cfg-test.o
CC tests/drive_del-test.o
CC tests/wdt_ib700-test.o
CC tests/tco-test.o
CC tests/e1000-test.o
CC tests/e1000e-test.o
CC tests/rtl8139-test.o
CC tests/pcnet-test.o
CC tests/eepro100-test.o
CC tests/ne2000-test.o
CC tests/nvme-test.o
CC tests/ac97-test.o
CC tests/es1370-test.o
CC tests/virtio-net-test.o
CC tests/virtio-balloon-test.o
CC tests/virtio-blk-test.o
CC tests/virtio-rng-test.o
CC tests/virtio-scsi-test.o
CC tests/virtio-serial-test.o
CC tests/virtio-console-test.o
CC tests/tpci200-test.o
CC tests/ipoctal232-test.o
CC tests/display-vga-test.o
CC tests/intel-hda-test.o
CC tests/ivshmem-test.o
CC tests/megasas-test.o
CC tests/vmxnet3-test.o
CC tests/pvpanic-test.o
CC tests/i82801b11-test.o
CC tests/ioh3420-test.o
CC tests/usb-hcd-ohci-test.o
CC tests/libqos/usb.o
CC tests/usb-hcd-uhci-test.o
CC tests/usb-hcd-ehci-test.o
CC tests/usb-hcd-xhci-test.o
CC tests/pc-cpu-test.o
CC tests/q35-test.o
CC tests/vmgenid-test.o
CC tests/test-netfilter.o
CC tests/test-filter-mirror.o
CC tests/test-filter-redirector.o
CC tests/postcopy-test.o
CC tests/test-x86-cpuid-compat.o
CC tests/numa-test.o
CC tests/qmp-test.o
CC tests/device-introspect-test.o
CC tests/qom-test.o
CC tests/test-hmp.o
LINK tests/check-qdict
LINK tests/test-char
LINK tests/check-qnum
LINK tests/check-qstring
LINK tests/check-qlist
LINK tests/check-qnull
LINK tests/check-qjson
LINK tests/check-qlit
CC tests/test-qapi-types.o
CC tests/test-qapi-event.o
CC tests/test-qapi-visit.o
CC tests/test-qmp-introspect.o
CC tests/test-qmp-marshal.o
LINK tests/test-coroutine
LINK tests/test-iov
LINK tests/test-aio
LINK tests/test-aio-multithread
LINK tests/test-throttle
LINK tests/test-thread-pool
LINK tests/test-hbitmap
LINK tests/test-blockjob
LINK tests/test-blockjob-txn
LINK tests/test-x86-cpuid
LINK tests/test-xbzrle
LINK tests/test-vmstate
LINK tests/test-cutils
LINK tests/test-shift128
LINK tests/test-mul64
LINK tests/test-int128
LINK tests/rcutorture
LINK tests/test-rcu-list
LINK tests/test-qdist
LINK tests/test-qht
LINK tests/qht-bench
LINK tests/test-bitops
LINK tests/test-bitcnt
LINK tests/check-qom-interface
LINK tests/check-qom-proplist
LINK tests/test-qemu-opts
LINK tests/test-keyval
LINK tests/test-write-threshold
LINK tests/test-crypto-hash
LINK tests/test-crypto-hmac
LINK tests/test-crypto-cipher
LINK tests/test-crypto-secret
LINK tests/test-qga
LINK tests/test-timed-average
LINK tests/test-io-task
LINK tests/test-io-channel-socket
LINK tests/test-io-channel-file
LINK tests/test-io-channel-command
LINK tests/test-io-channel-buffer
LINK tests/test-base64
LINK tests/test-crypto-ivgen
LINK tests/test-crypto-afsplit
LINK tests/test-crypto-xts
LINK tests/test-crypto-block
LINK tests/test-logging
LINK tests/test-replication
LINK tests/test-bufferiszero
LINK tests/test-uuid
LINK tests/ptimer-test
LINK tests/test-qapi-util
GTESTER tests/test-softfloat-aarch64
LINK tests/test-softfloat
LINK tests/vhost-user-test
(gtester:10598): GLib-WARNING **: Failed to execute test binary: tests/test-softfloat-aarch64: Failed to execute child process "tests/test-softfloat-aarch64" (No such file or directory)
tests/test-softfloat.o: In function `test_f16_convert_to_int':
/tmp/qemu-test/src/tests/test-softfloat.c:39: undefined reference to `g_test_fail'
tests/test-softfloat.o: In function `test_f16_round_to_int':
/tmp/qemu-test/src/tests/test-softfloat.c:73: undefined reference to `g_test_fail'
collect2: ld returned 1 exit status
make: *** [tests/test-softfloat] Error 1
make: *** Waiting for unfinished jobs....
Traceback (most recent call last):
File "./tests/docker/docker.py", line 385, in <module>
sys.exit(main())
File "./tests/docker/docker.py", line 382, in main
return args.cmdobj.run(args, argv)
File "./tests/docker/docker.py", line 239, in run
return Docker().run(argv, args.keep, quiet=args.quiet)
File "./tests/docker/docker.py", line 207, in run
quiet=quiet)
File "./tests/docker/docker.py", line 125, in _do_check
return subprocess.check_call(self._command + cmd, **kwargs)
File "/usr/lib64/python2.7/subprocess.py", line 186, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['docker', 'run', '--label', 'com.qemu.instance.uuid=4fd24d88b03711e7b01952540069c830', '-u', '0', '-t', '--security-opt', 'seccomp=unconfined', '--rm', '--net=none', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=8', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/root/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-9a_nc8id/src/docker-src.2017-10-13-12.55.25.5914:/var/tmp/qemu:z,ro', 'qemu:centos6', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2
make[1]: *** [tests/docker/Makefile.include:129: docker-run] Error 1
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-9a_nc8id/src'
make: *** [tests/docker/Makefile.include:161: docker-run-test-quick@centos6] Error 2
real 3m36.772s
user 0m1.368s
sys 0m1.616s
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (30 preceding siblings ...)
2017-10-13 16:58 ` [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) no-reply
@ 2017-10-13 16:59 ` no-reply
2017-10-17 2:34 ` Richard Henderson
32 siblings, 0 replies; 59+ messages in thread
From: no-reply @ 2017-10-13 16:59 UTC (permalink / raw)
To: alex.bennee; +Cc: famz, richard.henderson, peter.maydell, qemu-arm, qemu-devel
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20171013162438.32458-1-alex.bennee@linaro.org
Subject: [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress)
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
a8d9e2a127 target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc
e47972bdb3 tests/test-softfloat: add f16_to_int16 conversion test
a60d18c62d softfloat: float16_to_int16 conversion
bfdf06e71c target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc
9743fd4234 tests/test-softfloat: add a simple test framework
c00f720eaa softfloat: float16_round_to_int
210fa92599 disas_simd_indexed: support half-precision operations
1ad1d7e5a4 softfloat: add float16_rem and float16_muladd (!CHECK)
13cc912be0 target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same
eae9498170 target/arm/translate-a64: add FP16 2-reg misc compare (zero)
3bd8bfc5fa softfloat: half-precision compare functions
6d48002215 Fix mask for AdvancedSIMD 2 reg misc
e2560b1cc1 target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton
fd8d37dc6b target/arm/translate-a64.c: add FP16 FMULX
023a4abddd target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub)
a484840d45 softfloat: half-precision add/sub/mul/div support
e708f32268 softfloat: 16 bit helpers for shr, clz and rounding and packing
2f65402d6d target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode
76387c084b target/arm/translate-a64.c: handle_3same_64 comment fix
4b10ff1a59 target/arm: implement half-precision F(MIN|MAX)(V|NMV)
ebbf91f0d9 softfloat: improve comments on ARM NaN propagation
c69770519b softfloat: propagate signalling NaNs in MINMAX
beeb3d9188 softfloat: add half-precision expansions for MINMAX fns
8db446be24 fpu/softfloat: implement float16_abs helper
97b4ec2f26 fpu/softfloat: implement float16_squash_input_denormal
fcac6b5acb softfloat: implement propagateFloat16NaN
cc5f898f35 target/arm/cpu.h: update comment for half-precision values
a3fa9b0170 include/exec/helper-head.h: support f16 in helper calls
a37d42107d arm: introduce ARM_V8_FP16 feature bit
e8c0401452 linux-user/main: support dfilter
=== OUTPUT BEGIN ===
Checking PATCH 1/30: linux-user/main: support dfilter...
ERROR: space required after that ',' (ctx:VxV)
#33: FILE: linux-user/main.c:4063:
+ "range[,...]","filter logging based on address range"},
^
total: 1 errors, 0 warnings, 19 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 2/30: arm: introduce ARM_V8_FP16 feature bit...
Checking PATCH 3/30: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 4/30: target/arm/cpu.h: update comment for half-precision values...
Checking PATCH 5/30: softfloat: implement propagateFloat16NaN...
Checking PATCH 6/30: fpu/softfloat: implement float16_squash_input_denormal...
Checking PATCH 7/30: fpu/softfloat: implement float16_abs helper...
Checking PATCH 8/30: softfloat: add half-precision expansions for MINMAX fns...
Checking PATCH 9/30: softfloat: propagate signalling NaNs in MINMAX...
Checking PATCH 10/30: softfloat: improve comments on ARM NaN propagation...
WARNING: line over 80 characters
#29: FILE: fpu/softfloat-specialize.h:450:
+ /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take the first of:
total: 0 errors, 1 warnings, 19 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 11/30: target/arm: implement half-precision F(MIN|MAX)(V|NMV)...
ERROR: space required before the open parenthesis '('
#126: FILE: target/arm/translate-a64.c:5646:
+ switch(fpopcode) {
WARNING: line over 80 characters
#152: FILE: target/arm/translate-a64.c:5672:
+ fprintf(stderr, "%s: fpopcode %x not handled\n", __func__, fpopcode);
total: 1 errors, 1 warnings, 208 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 12/30: target/arm/translate-a64.c: handle_3same_64 comment fix...
Checking PATCH 13/30: target/arm/translate-a64.c: AdvSIMD scalar 3 Same FP16 initial decode...
WARNING: line over 80 characters
#82: FILE: target/arm/translate-a64.c:9810:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode);
ERROR: space required after that ',' (ctx:VxV)
#82: FILE: target/arm/translate-a64.c:9810:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpopcode);
^
total: 1 errors, 1 warnings, 88 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 14/30: softfloat: 16 bit helpers for shr, clz and rounding and packing...
ERROR: space prohibited after that open parenthesis '('
#38: FILE: fpu/softfloat-macros.h:105:
+ if ( count == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#38: FILE: fpu/softfloat-macros.h:105:
+ if ( count == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#41: FILE: fpu/softfloat-macros.h:108:
+ else if ( count < 16 ) {
ERROR: space prohibited before that close parenthesis ')'
#41: FILE: fpu/softfloat-macros.h:108:
+ else if ( count < 16 ) {
ERROR: else should follow close brace '}'
#41: FILE: fpu/softfloat-macros.h:108:
+ }
+ else if ( count < 16 ) {
ERROR: spaces required around that '>>' (ctx:VxV)
#42: FILE: fpu/softfloat-macros.h:109:
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
^
ERROR: spaces required around that '<<' (ctx:VxV)
#42: FILE: fpu/softfloat-macros.h:109:
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
^
ERROR: space prohibited after that '-' (ctx:WxW)
#42: FILE: fpu/softfloat-macros.h:109:
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
^
ERROR: space prohibited after that open parenthesis '('
#42: FILE: fpu/softfloat-macros.h:109:
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
ERROR: space prohibited before that close parenthesis ')'
#42: FILE: fpu/softfloat-macros.h:109:
+ z = ( a>>count ) | ( ( a<<( ( - count ) & 16 ) ) != 0 );
ERROR: else should follow close brace '}'
#44: FILE: fpu/softfloat-macros.h:111:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#45: FILE: fpu/softfloat-macros.h:112:
+ z = ( a != 0 );
ERROR: space prohibited before that close parenthesis ')'
#45: FILE: fpu/softfloat-macros.h:112:
+ z = ( a != 0 );
ERROR: space prohibited after that open parenthesis '('
#60: FILE: fpu/softfloat-macros.h:697:
+static int8_t countLeadingZeros16( uint16_t a )
ERROR: space prohibited before that close parenthesis ')'
#60: FILE: fpu/softfloat-macros.h:697:
+static int8_t countLeadingZeros16( uint16_t a )
ERROR: space prohibited after that open parenthesis '('
#96: FILE: fpu/softfloat.c:3506:
+ shiftCount = countLeadingZeros16( zSig ) - 1;
ERROR: space prohibited before that close parenthesis ')'
#96: FILE: fpu/softfloat.c:3506:
+ shiftCount = countLeadingZeros16( zSig ) - 1;
ERROR: spaces required around that '<<' (ctx:VxV)
#97: FILE: fpu/softfloat.c:3507:
+ return roundAndPackFloat16(zSign, zExp - shiftCount, zSig<<shiftCount,
^
total: 18 errors, 0 warnings, 78 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/30: softfloat: half-precision add/sub/mul/div support...
ERROR: space prohibited after that open parenthesis '('
#40: FILE: fpu/softfloat.c:3550:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited before that close parenthesis ')'
#40: FILE: fpu/softfloat.c:3550:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited after that open parenthesis '('
#41: FILE: fpu/softfloat.c:3551:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#41: FILE: fpu/softfloat.c:3551:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited after that open parenthesis '('
#42: FILE: fpu/softfloat.c:3552:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited before that close parenthesis ')'
#42: FILE: fpu/softfloat.c:3552:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited after that open parenthesis '('
#43: FILE: fpu/softfloat.c:3553:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited before that close parenthesis ')'
#43: FILE: fpu/softfloat.c:3553:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited after that open parenthesis '('
#47: FILE: fpu/softfloat.c:3557:
+ if ( 0 < expDiff ) {
ERROR: space prohibited before that close parenthesis ')'
#47: FILE: fpu/softfloat.c:3557:
+ if ( 0 < expDiff ) {
ERROR: space prohibited after that open parenthesis '('
#48: FILE: fpu/softfloat.c:3558:
+ if ( aExp == 0x1F ) {
ERROR: space prohibited before that close parenthesis ')'
#48: FILE: fpu/softfloat.c:3558:
+ if ( aExp == 0x1F ) {
ERROR: space prohibited after that open parenthesis '('
#54: FILE: fpu/softfloat.c:3564:
+ if ( bExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#54: FILE: fpu/softfloat.c:3564:
+ if ( bExp == 0 ) {
ERROR: else should follow close brace '}'
#57: FILE: fpu/softfloat.c:3567:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#60: FILE: fpu/softfloat.c:3570:
+ shift16RightJamming( bSig, expDiff, &bSig );
ERROR: space prohibited before that close parenthesis ')'
#60: FILE: fpu/softfloat.c:3570:
+ shift16RightJamming( bSig, expDiff, &bSig );
ERROR: space prohibited after that open parenthesis '('
#63: FILE: fpu/softfloat.c:3573:
+ else if ( expDiff < 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#63: FILE: fpu/softfloat.c:3573:
+ else if ( expDiff < 0 ) {
ERROR: else should follow close brace '}'
#63: FILE: fpu/softfloat.c:3573:
+ }
+ else if ( expDiff < 0 ) {
ERROR: space prohibited after that open parenthesis '('
#64: FILE: fpu/softfloat.c:3574:
+ if ( bExp == 0x1F ) {
ERROR: space prohibited before that close parenthesis ')'
#64: FILE: fpu/softfloat.c:3574:
+ if ( bExp == 0x1F ) {
ERROR: space prohibited after that open parenthesis '('
#68: FILE: fpu/softfloat.c:3578:
+ return packFloat16( zSign, 0x1F, 0 );
ERROR: space prohibited before that close parenthesis ')'
#68: FILE: fpu/softfloat.c:3578:
+ return packFloat16( zSign, 0x1F, 0 );
ERROR: space prohibited after that open parenthesis '('
#70: FILE: fpu/softfloat.c:3580:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#70: FILE: fpu/softfloat.c:3580:
+ if ( aExp == 0 ) {
ERROR: else should follow close brace '}'
#73: FILE: fpu/softfloat.c:3583:
+ }
+ else {
ERROR: space prohibited after that '-' (ctx:WxW)
#76: FILE: fpu/softfloat.c:3586:
+ shift16RightJamming( aSig, - expDiff, &aSig );
^
ERROR: space prohibited after that open parenthesis '('
#76: FILE: fpu/softfloat.c:3586:
+ shift16RightJamming( aSig, - expDiff, &aSig );
ERROR: space prohibited before that close parenthesis ')'
#76: FILE: fpu/softfloat.c:3586:
+ shift16RightJamming( aSig, - expDiff, &aSig );
ERROR: else should follow close brace '}'
#79: FILE: fpu/softfloat.c:3589:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#80: FILE: fpu/softfloat.c:3590:
+ if ( aExp == 0x1F ) {
ERROR: space prohibited before that close parenthesis ')'
#80: FILE: fpu/softfloat.c:3590:
+ if ( aExp == 0x1F ) {
ERROR: space prohibited after that open parenthesis '('
#86: FILE: fpu/softfloat.c:3596:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#86: FILE: fpu/softfloat.c:3596:
+ if ( aExp == 0 ) {
ERROR: spaces required around that '>>' (ctx:VxV)
#93: FILE: fpu/softfloat.c:3603:
+ return packFloat16( zSign, 0, ( aSig + bSig )>>3 );
^
ERROR: space prohibited after that open parenthesis '('
#93: FILE: fpu/softfloat.c:3603:
+ return packFloat16( zSign, 0, ( aSig + bSig )>>3 );
ERROR: space prohibited before that close parenthesis ')'
#93: FILE: fpu/softfloat.c:3603:
+ return packFloat16( zSign, 0, ( aSig + bSig )>>3 );
ERROR: spaces required around that '<<' (ctx:VxV)
#100: FILE: fpu/softfloat.c:3610:
+ zSig = ( aSig + bSig )<<1;
^
ERROR: space prohibited after that open parenthesis '('
#100: FILE: fpu/softfloat.c:3610:
+ zSig = ( aSig + bSig )<<1;
ERROR: space prohibited before that close parenthesis ')'
#100: FILE: fpu/softfloat.c:3610:
+ zSig = ( aSig + bSig )<<1;
ERROR: space prohibited after that open parenthesis '('
#102: FILE: fpu/softfloat.c:3612:
+ if ( (int16_t) zSig < 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#102: FILE: fpu/softfloat.c:3612:
+ if ( (int16_t) zSig < 0 ) {
ERROR: space prohibited after that open parenthesis '('
#126: FILE: fpu/softfloat.c:3636:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited before that close parenthesis ')'
#126: FILE: fpu/softfloat.c:3636:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited after that open parenthesis '('
#127: FILE: fpu/softfloat.c:3637:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#127: FILE: fpu/softfloat.c:3637:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited after that open parenthesis '('
#128: FILE: fpu/softfloat.c:3638:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited before that close parenthesis ')'
#128: FILE: fpu/softfloat.c:3638:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited after that open parenthesis '('
#129: FILE: fpu/softfloat.c:3639:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited before that close parenthesis ')'
#129: FILE: fpu/softfloat.c:3639:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited after that open parenthesis '('
#133: FILE: fpu/softfloat.c:3643:
+ if ( 0 < expDiff ) goto aExpBigger;
ERROR: space prohibited before that close parenthesis ')'
#133: FILE: fpu/softfloat.c:3643:
+ if ( 0 < expDiff ) goto aExpBigger;
ERROR: trailing statements should be on next line
#133: FILE: fpu/softfloat.c:3643:
+ if ( 0 < expDiff ) goto aExpBigger;
ERROR: braces {} are necessary for all arms of this statement
#133: FILE: fpu/softfloat.c:3643:
+ if ( 0 < expDiff ) goto aExpBigger;
[...]
ERROR: space prohibited after that open parenthesis '('
#134: FILE: fpu/softfloat.c:3644:
+ if ( expDiff < 0 ) goto bExpBigger;
ERROR: space prohibited before that close parenthesis ')'
#134: FILE: fpu/softfloat.c:3644:
+ if ( expDiff < 0 ) goto bExpBigger;
ERROR: trailing statements should be on next line
#134: FILE: fpu/softfloat.c:3644:
+ if ( expDiff < 0 ) goto bExpBigger;
ERROR: braces {} are necessary for all arms of this statement
#134: FILE: fpu/softfloat.c:3644:
+ if ( expDiff < 0 ) goto bExpBigger;
[...]
ERROR: space prohibited after that open parenthesis '('
#135: FILE: fpu/softfloat.c:3645:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#135: FILE: fpu/softfloat.c:3645:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#142: FILE: fpu/softfloat.c:3652:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#142: FILE: fpu/softfloat.c:3652:
+ if ( aExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#146: FILE: fpu/softfloat.c:3656:
+ if ( bSig < aSig ) goto aBigger;
ERROR: space prohibited before that close parenthesis ')'
#146: FILE: fpu/softfloat.c:3656:
+ if ( bSig < aSig ) goto aBigger;
ERROR: trailing statements should be on next line
#146: FILE: fpu/softfloat.c:3656:
+ if ( bSig < aSig ) goto aBigger;
ERROR: braces {} are necessary for all arms of this statement
#146: FILE: fpu/softfloat.c:3656:
+ if ( bSig < aSig ) goto aBigger;
[...]
ERROR: space prohibited after that open parenthesis '('
#147: FILE: fpu/softfloat.c:3657:
+ if ( aSig < bSig ) goto bBigger;
ERROR: space prohibited before that close parenthesis ')'
#147: FILE: fpu/softfloat.c:3657:
+ if ( aSig < bSig ) goto bBigger;
ERROR: trailing statements should be on next line
#147: FILE: fpu/softfloat.c:3657:
+ if ( aSig < bSig ) goto bBigger;
ERROR: braces {} are necessary for all arms of this statement
#147: FILE: fpu/softfloat.c:3657:
+ if ( aSig < bSig ) goto bBigger;
[...]
ERROR: space prohibited after that open parenthesis '('
#150: FILE: fpu/softfloat.c:3660:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#150: FILE: fpu/softfloat.c:3660:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#154: FILE: fpu/softfloat.c:3664:
+ return packFloat16( zSign ^ 1, 0xFF, 0 );
ERROR: space prohibited before that close parenthesis ')'
#154: FILE: fpu/softfloat.c:3664:
+ return packFloat16( zSign ^ 1, 0xFF, 0 );
ERROR: space prohibited after that open parenthesis '('
#156: FILE: fpu/softfloat.c:3666:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#156: FILE: fpu/softfloat.c:3666:
+ if ( aExp == 0 ) {
ERROR: else should follow close brace '}'
#159: FILE: fpu/softfloat.c:3669:
+ }
+ else {
ERROR: space prohibited after that '-' (ctx:WxW)
#162: FILE: fpu/softfloat.c:3672:
+ shift16RightJamming( aSig, - expDiff, &aSig );
^
ERROR: space prohibited after that open parenthesis '('
#162: FILE: fpu/softfloat.c:3672:
+ shift16RightJamming( aSig, - expDiff, &aSig );
ERROR: space prohibited before that close parenthesis ')'
#162: FILE: fpu/softfloat.c:3672:
+ shift16RightJamming( aSig, - expDiff, &aSig );
ERROR: space prohibited after that open parenthesis '('
#170: FILE: fpu/softfloat.c:3680:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#170: FILE: fpu/softfloat.c:3680:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#176: FILE: fpu/softfloat.c:3686:
+ if ( bExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#176: FILE: fpu/softfloat.c:3686:
+ if ( bExp == 0 ) {
ERROR: else should follow close brace '}'
#179: FILE: fpu/softfloat.c:3689:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#182: FILE: fpu/softfloat.c:3692:
+ shift16RightJamming( bSig, expDiff, &bSig );
ERROR: space prohibited before that close parenthesis ')'
#182: FILE: fpu/softfloat.c:3692:
+ shift16RightJamming( bSig, expDiff, &bSig );
ERROR: space prohibited after that open parenthesis '('
#205: FILE: fpu/softfloat.c:3715:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#205: FILE: fpu/softfloat.c:3715:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#206: FILE: fpu/softfloat.c:3716:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#206: FILE: fpu/softfloat.c:3716:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited after that open parenthesis '('
#207: FILE: fpu/softfloat.c:3717:
+ if ( aSign == bSign ) {
ERROR: space prohibited before that close parenthesis ')'
#207: FILE: fpu/softfloat.c:3717:
+ if ( aSign == bSign ) {
ERROR: else should follow close brace '}'
#210: FILE: fpu/softfloat.c:3720:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#228: FILE: fpu/softfloat.c:3738:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#228: FILE: fpu/softfloat.c:3738:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#229: FILE: fpu/softfloat.c:3739:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#229: FILE: fpu/softfloat.c:3739:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited after that open parenthesis '('
#230: FILE: fpu/softfloat.c:3740:
+ if ( aSign == bSign ) {
ERROR: space prohibited before that close parenthesis ')'
#230: FILE: fpu/softfloat.c:3740:
+ if ( aSign == bSign ) {
ERROR: else should follow close brace '}'
#233: FILE: fpu/softfloat.c:3743:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#255: FILE: fpu/softfloat.c:3765:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited before that close parenthesis ')'
#255: FILE: fpu/softfloat.c:3765:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited after that open parenthesis '('
#256: FILE: fpu/softfloat.c:3766:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#256: FILE: fpu/softfloat.c:3766:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited after that open parenthesis '('
#257: FILE: fpu/softfloat.c:3767:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#257: FILE: fpu/softfloat.c:3767:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#258: FILE: fpu/softfloat.c:3768:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited before that close parenthesis ')'
#258: FILE: fpu/softfloat.c:3768:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited after that open parenthesis '('
#259: FILE: fpu/softfloat.c:3769:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited before that close parenthesis ')'
#259: FILE: fpu/softfloat.c:3769:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited after that open parenthesis '('
#260: FILE: fpu/softfloat.c:3770:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#260: FILE: fpu/softfloat.c:3770:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited after that open parenthesis '('
#262: FILE: fpu/softfloat.c:3772:
+ if ( aExp == 0x1F ) {
ERROR: space prohibited before that close parenthesis ')'
#262: FILE: fpu/softfloat.c:3772:
+ if ( aExp == 0x1F ) {
ERROR: space prohibited after that open parenthesis '('
#263: FILE: fpu/softfloat.c:3773:
+ if ( aSig || ( ( bExp == 0x1F ) && bSig ) ) {
ERROR: space prohibited before that close parenthesis ')'
#263: FILE: fpu/softfloat.c:3773:
+ if ( aSig || ( ( bExp == 0x1F ) && bSig ) ) {
ERROR: space prohibited after that open parenthesis '('
#266: FILE: fpu/softfloat.c:3776:
+ if ( ( bExp | bSig ) == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#266: FILE: fpu/softfloat.c:3776:
+ if ( ( bExp | bSig ) == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#270: FILE: fpu/softfloat.c:3780:
+ return packFloat16( zSign, 0x1F, 0 );
ERROR: space prohibited before that close parenthesis ')'
#270: FILE: fpu/softfloat.c:3780:
+ return packFloat16( zSign, 0x1F, 0 );
ERROR: space prohibited after that open parenthesis '('
#272: FILE: fpu/softfloat.c:3782:
+ if ( bExp == 0x1F ) {
ERROR: space prohibited before that close parenthesis ')'
#272: FILE: fpu/softfloat.c:3782:
+ if ( bExp == 0x1F ) {
ERROR: space prohibited after that open parenthesis '('
#276: FILE: fpu/softfloat.c:3786:
+ if ( ( aExp | aSig ) == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#276: FILE: fpu/softfloat.c:3786:
+ if ( ( aExp | aSig ) == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#280: FILE: fpu/softfloat.c:3790:
+ return packFloat16( zSign, 0x1F, 0 );
ERROR: space prohibited before that close parenthesis ')'
#280: FILE: fpu/softfloat.c:3790:
+ return packFloat16( zSign, 0x1F, 0 );
ERROR: space prohibited after that open parenthesis '('
#282: FILE: fpu/softfloat.c:3792:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#282: FILE: fpu/softfloat.c:3792:
+ if ( aExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#283: FILE: fpu/softfloat.c:3793:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: space prohibited before that close parenthesis ')'
#283: FILE: fpu/softfloat.c:3793:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: trailing statements should be on next line
#283: FILE: fpu/softfloat.c:3793:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: braces {} are necessary for all arms of this statement
#283: FILE: fpu/softfloat.c:3793:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#284: FILE: fpu/softfloat.c:3794:
+ normalizeFloat16Subnormal( aSig, &aExp, &aSig );
ERROR: space prohibited before that close parenthesis ')'
#284: FILE: fpu/softfloat.c:3794:
+ normalizeFloat16Subnormal( aSig, &aExp, &aSig );
ERROR: space prohibited after that open parenthesis '('
#286: FILE: fpu/softfloat.c:3796:
+ if ( bExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#286: FILE: fpu/softfloat.c:3796:
+ if ( bExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#287: FILE: fpu/softfloat.c:3797:
+ if ( bSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: space prohibited before that close parenthesis ')'
#287: FILE: fpu/softfloat.c:3797:
+ if ( bSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: trailing statements should be on next line
#287: FILE: fpu/softfloat.c:3797:
+ if ( bSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: braces {} are necessary for all arms of this statement
#287: FILE: fpu/softfloat.c:3797:
+ if ( bSig == 0 ) return packFloat16( zSign, 0, 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#288: FILE: fpu/softfloat.c:3798:
+ normalizeFloat16Subnormal( bSig, &bExp, &bSig );
ERROR: space prohibited before that close parenthesis ')'
#288: FILE: fpu/softfloat.c:3798:
+ normalizeFloat16Subnormal( bSig, &bExp, &bSig );
ERROR: spaces required around that '<<' (ctx:VxV)
#292: FILE: fpu/softfloat.c:3802:
+ aSig = ( aSig | 0x0400 )<<4;
^
ERROR: space prohibited after that open parenthesis '('
#292: FILE: fpu/softfloat.c:3802:
+ aSig = ( aSig | 0x0400 )<<4;
ERROR: space prohibited before that close parenthesis ')'
#292: FILE: fpu/softfloat.c:3802:
+ aSig = ( aSig | 0x0400 )<<4;
ERROR: spaces required around that '<<' (ctx:VxV)
#293: FILE: fpu/softfloat.c:3803:
+ bSig = ( bSig | 0x0400 )<<5;
^
ERROR: space prohibited after that open parenthesis '('
#293: FILE: fpu/softfloat.c:3803:
+ bSig = ( bSig | 0x0400 )<<5;
ERROR: space prohibited before that close parenthesis ')'
#293: FILE: fpu/softfloat.c:3803:
+ bSig = ( bSig | 0x0400 )<<5;
ERROR: space prohibited after that open parenthesis '('
#297: FILE: fpu/softfloat.c:3807:
+ shift32RightJamming( ( (uint32_t) aSig ) * bSig, 7, &zSig32 );
ERROR: space prohibited before that close parenthesis ')'
#297: FILE: fpu/softfloat.c:3807:
+ shift32RightJamming( ( (uint32_t) aSig ) * bSig, 7, &zSig32 );
ERROR: spaces required around that '<<' (ctx:VxV)
#300: FILE: fpu/softfloat.c:3810:
+ if ( 0 <= (int32_t) ( zSig32<<1 ) ) {
^
ERROR: space prohibited after that open parenthesis '('
#300: FILE: fpu/softfloat.c:3810:
+ if ( 0 <= (int32_t) ( zSig32<<1 ) ) {
ERROR: space prohibited before that close parenthesis ')'
#300: FILE: fpu/softfloat.c:3810:
+ if ( 0 <= (int32_t) ( zSig32<<1 ) ) {
ERROR: space prohibited after that open parenthesis '('
#321: FILE: fpu/softfloat.c:3831:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited before that close parenthesis ')'
#321: FILE: fpu/softfloat.c:3831:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited after that open parenthesis '('
#322: FILE: fpu/softfloat.c:3832:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#322: FILE: fpu/softfloat.c:3832:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited after that open parenthesis '('
#323: FILE: fpu/softfloat.c:3833:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#323: FILE: fpu/softfloat.c:3833:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#324: FILE: fpu/softfloat.c:3834:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited before that close parenthesis ')'
#324: FILE: fpu/softfloat.c:3834:
+ bSig = extractFloat16Frac( b );
ERROR: space prohibited after that open parenthesis '('
#325: FILE: fpu/softfloat.c:3835:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited before that close parenthesis ')'
#325: FILE: fpu/softfloat.c:3835:
+ bExp = extractFloat16Exp( b );
ERROR: space prohibited after that open parenthesis '('
#326: FILE: fpu/softfloat.c:3836:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#326: FILE: fpu/softfloat.c:3836:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited after that open parenthesis '('
#328: FILE: fpu/softfloat.c:3838:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#328: FILE: fpu/softfloat.c:3838:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#332: FILE: fpu/softfloat.c:3842:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#332: FILE: fpu/softfloat.c:3842:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#339: FILE: fpu/softfloat.c:3849:
+ return packFloat16( zSign, 0xFF, 0 );
ERROR: space prohibited before that close parenthesis ')'
#339: FILE: fpu/softfloat.c:3849:
+ return packFloat16( zSign, 0xFF, 0 );
ERROR: space prohibited after that open parenthesis '('
#341: FILE: fpu/softfloat.c:3851:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#341: FILE: fpu/softfloat.c:3851:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#345: FILE: fpu/softfloat.c:3855:
+ return packFloat16( zSign, 0, 0 );
ERROR: space prohibited before that close parenthesis ')'
#345: FILE: fpu/softfloat.c:3855:
+ return packFloat16( zSign, 0, 0 );
ERROR: space prohibited after that open parenthesis '('
#347: FILE: fpu/softfloat.c:3857:
+ if ( bExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#347: FILE: fpu/softfloat.c:3857:
+ if ( bExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#348: FILE: fpu/softfloat.c:3858:
+ if ( bSig == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#348: FILE: fpu/softfloat.c:3858:
+ if ( bSig == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#349: FILE: fpu/softfloat.c:3859:
+ if ( ( aExp | aSig ) == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#349: FILE: fpu/softfloat.c:3859:
+ if ( ( aExp | aSig ) == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#354: FILE: fpu/softfloat.c:3864:
+ return packFloat16( zSign, 0xFF, 0 );
ERROR: space prohibited before that close parenthesis ')'
#354: FILE: fpu/softfloat.c:3864:
+ return packFloat16( zSign, 0xFF, 0 );
ERROR: space prohibited after that open parenthesis '('
#356: FILE: fpu/softfloat.c:3866:
+ normalizeFloat16Subnormal( bSig, &bExp, &bSig );
ERROR: space prohibited before that close parenthesis ')'
#356: FILE: fpu/softfloat.c:3866:
+ normalizeFloat16Subnormal( bSig, &bExp, &bSig );
ERROR: space prohibited after that open parenthesis '('
#358: FILE: fpu/softfloat.c:3868:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#358: FILE: fpu/softfloat.c:3868:
+ if ( aExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#359: FILE: fpu/softfloat.c:3869:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: space prohibited before that close parenthesis ')'
#359: FILE: fpu/softfloat.c:3869:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: trailing statements should be on next line
#359: FILE: fpu/softfloat.c:3869:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
ERROR: braces {} are necessary for all arms of this statement
#359: FILE: fpu/softfloat.c:3869:
+ if ( aSig == 0 ) return packFloat16( zSign, 0, 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#360: FILE: fpu/softfloat.c:3870:
+ normalizeFloat16Subnormal( aSig, &aExp, &aSig );
ERROR: space prohibited before that close parenthesis ')'
#360: FILE: fpu/softfloat.c:3870:
+ normalizeFloat16Subnormal( aSig, &aExp, &aSig );
ERROR: spaces required around that '<<' (ctx:VxV)
#363: FILE: fpu/softfloat.c:3873:
+ aSig = ( aSig | 0x00800000 )<<7;
^
ERROR: space prohibited after that open parenthesis '('
#363: FILE: fpu/softfloat.c:3873:
+ aSig = ( aSig | 0x00800000 )<<7;
ERROR: space prohibited before that close parenthesis ')'
#363: FILE: fpu/softfloat.c:3873:
+ aSig = ( aSig | 0x00800000 )<<7;
ERROR: spaces required around that '<<' (ctx:VxV)
#364: FILE: fpu/softfloat.c:3874:
+ bSig = ( bSig | 0x00800000 )<<8;
^
ERROR: space prohibited after that open parenthesis '('
#364: FILE: fpu/softfloat.c:3874:
+ bSig = ( bSig | 0x00800000 )<<8;
ERROR: space prohibited before that close parenthesis ')'
#364: FILE: fpu/softfloat.c:3874:
+ bSig = ( bSig | 0x00800000 )<<8;
ERROR: space prohibited after that open parenthesis '('
#365: FILE: fpu/softfloat.c:3875:
+ if ( bSig <= ( aSig + aSig ) ) {
ERROR: space prohibited before that close parenthesis ')'
#365: FILE: fpu/softfloat.c:3875:
+ if ( bSig <= ( aSig + aSig ) ) {
ERROR: spaces required around that '<<' (ctx:VxV)
#369: FILE: fpu/softfloat.c:3879:
+ zSig = ( ( (uint64_t) aSig )<<16 ) / bSig;
^
ERROR: space prohibited after that open parenthesis '('
#369: FILE: fpu/softfloat.c:3879:
+ zSig = ( ( (uint64_t) aSig )<<16 ) / bSig;
ERROR: space prohibited before that close parenthesis ')'
#369: FILE: fpu/softfloat.c:3879:
+ zSig = ( ( (uint64_t) aSig )<<16 ) / bSig;
ERROR: space prohibited after that open parenthesis '('
#370: FILE: fpu/softfloat.c:3880:
+ if ( ( zSig & 0x3F ) == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#370: FILE: fpu/softfloat.c:3880:
+ if ( ( zSig & 0x3F ) == 0 ) {
ERROR: spaces required around that '<<' (ctx:VxV)
#371: FILE: fpu/softfloat.c:3881:
+ zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 );
^
ERROR: space prohibited after that open parenthesis '('
#371: FILE: fpu/softfloat.c:3881:
+ zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 );
ERROR: space prohibited before that close parenthesis ')'
#371: FILE: fpu/softfloat.c:3881:
+ zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<16 );
total: 211 errors, 0 warnings, 370 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/30: target/arm/translate-a64.c: add FP16 FADD/FMUL/FDIV to AdvSIMD 3 Same (!sub)...
ERROR: space required after that ',' (ctx:VxV)
#65: FILE: target/arm/translate-a64.c:9819:
+ fprintf(stderr,"%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
^
total: 1 errors, 0 warnings, 39 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/30: target/arm/translate-a64.c: add FP16 FMULX...
WARNING: line over 80 characters
#107: FILE: target/arm/translate-a64.c:10823:
+ gen_helper_advsimd_mulxh(tcg_res, tcg_op, tcg_idx, fpst);
total: 0 errors, 1 warnings, 95 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 18/30: target/arm/translate-a64.c: add AdvSIMD scalar two-reg misc skeleton...
ERROR: space required after that ',' (ctx:VxV)
#52: FILE: target/arm/translate-a64.c:10599:
+ fprintf(stderr,"%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
^
total: 1 errors, 0 warnings, 47 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 19/30: Fix mask for AdvancedSIMD 2 reg misc...
Checking PATCH 20/30: softfloat: half-precision compare functions...
ERROR: space prohibited after that open parenthesis '('
#37: FILE: fpu/softfloat.c:3900:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#37: FILE: fpu/softfloat.c:3900:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#38: FILE: fpu/softfloat.c:3901:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#38: FILE: fpu/softfloat.c:3901:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: spaces required around that '<<' (ctx:VxV)
#45: FILE: fpu/softfloat.c:3908:
+ return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
^
ERROR: space prohibited after that open parenthesis '('
#45: FILE: fpu/softfloat.c:3908:
+ return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: space prohibited before that close parenthesis ')'
#45: FILE: fpu/softfloat.c:3908:
+ return ( av == bv ) || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: space prohibited after that open parenthesis '('
#62: FILE: fpu/softfloat.c:3925:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#62: FILE: fpu/softfloat.c:3925:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#63: FILE: fpu/softfloat.c:3926:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#63: FILE: fpu/softfloat.c:3926:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited after that open parenthesis '('
#68: FILE: fpu/softfloat.c:3931:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#68: FILE: fpu/softfloat.c:3931:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#69: FILE: fpu/softfloat.c:3932:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#69: FILE: fpu/softfloat.c:3932:
+ bSign = extractFloat16Sign( b );
WARNING: line over 80 characters
#72: FILE: fpu/softfloat.c:3935:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: spaces required around that '<<' (ctx:VxV)
#72: FILE: fpu/softfloat.c:3935:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
^
ERROR: space prohibited after that open parenthesis '('
#72: FILE: fpu/softfloat.c:3935:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: space prohibited before that close parenthesis ')'
#72: FILE: fpu/softfloat.c:3935:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: trailing statements should be on next line
#72: FILE: fpu/softfloat.c:3935:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: braces {} are necessary for all arms of this statement
#72: FILE: fpu/softfloat.c:3935:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#73: FILE: fpu/softfloat.c:3936:
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
ERROR: space prohibited before that close parenthesis ')'
#73: FILE: fpu/softfloat.c:3936:
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
ERROR: space prohibited after that open parenthesis '('
#91: FILE: fpu/softfloat.c:3954:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#91: FILE: fpu/softfloat.c:3954:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#92: FILE: fpu/softfloat.c:3955:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#92: FILE: fpu/softfloat.c:3955:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited after that open parenthesis '('
#97: FILE: fpu/softfloat.c:3960:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#97: FILE: fpu/softfloat.c:3960:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#98: FILE: fpu/softfloat.c:3961:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#98: FILE: fpu/softfloat.c:3961:
+ bSign = extractFloat16Sign( b );
WARNING: line over 80 characters
#101: FILE: fpu/softfloat.c:3964:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: spaces required around that '<<' (ctx:VxV)
#101: FILE: fpu/softfloat.c:3964:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
^
ERROR: space prohibited after that open parenthesis '('
#101: FILE: fpu/softfloat.c:3964:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: space prohibited before that close parenthesis ')'
#101: FILE: fpu/softfloat.c:3964:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: trailing statements should be on next line
#101: FILE: fpu/softfloat.c:3964:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: braces {} are necessary for all arms of this statement
#101: FILE: fpu/softfloat.c:3964:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#102: FILE: fpu/softfloat.c:3965:
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
ERROR: space prohibited before that close parenthesis ')'
#102: FILE: fpu/softfloat.c:3965:
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
ERROR: space prohibited after that open parenthesis '('
#118: FILE: fpu/softfloat.c:3981:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#118: FILE: fpu/softfloat.c:3981:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#119: FILE: fpu/softfloat.c:3982:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#119: FILE: fpu/softfloat.c:3982:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited after that open parenthesis '('
#139: FILE: fpu/softfloat.c:4002:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#139: FILE: fpu/softfloat.c:4002:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#140: FILE: fpu/softfloat.c:4003:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#140: FILE: fpu/softfloat.c:4003:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited after that open parenthesis '('
#148: FILE: fpu/softfloat.c:4011:
+ return ( float16_val(a) == float16_val(b) ) ||
ERROR: space prohibited before that close parenthesis ')'
#148: FILE: fpu/softfloat.c:4011:
+ return ( float16_val(a) == float16_val(b) ) ||
ERROR: spaces required around that '<<' (ctx:VxV)
#149: FILE: fpu/softfloat.c:4012:
+ ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 );
^
ERROR: space prohibited after that open parenthesis '('
#149: FILE: fpu/softfloat.c:4012:
+ ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 );
ERROR: space prohibited before that close parenthesis ')'
#149: FILE: fpu/softfloat.c:4012:
+ ( (uint32_t) ( ( float16_val(a) | float16_val(b) )<<1 ) == 0 );
ERROR: space prohibited after that open parenthesis '('
#166: FILE: fpu/softfloat.c:4029:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#166: FILE: fpu/softfloat.c:4029:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#167: FILE: fpu/softfloat.c:4030:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#167: FILE: fpu/softfloat.c:4030:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited after that open parenthesis '('
#175: FILE: fpu/softfloat.c:4038:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#175: FILE: fpu/softfloat.c:4038:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#176: FILE: fpu/softfloat.c:4039:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#176: FILE: fpu/softfloat.c:4039:
+ bSign = extractFloat16Sign( b );
WARNING: line over 80 characters
#179: FILE: fpu/softfloat.c:4042:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: spaces required around that '<<' (ctx:VxV)
#179: FILE: fpu/softfloat.c:4042:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
^
ERROR: space prohibited after that open parenthesis '('
#179: FILE: fpu/softfloat.c:4042:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: space prohibited before that close parenthesis ')'
#179: FILE: fpu/softfloat.c:4042:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: trailing statements should be on next line
#179: FILE: fpu/softfloat.c:4042:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
ERROR: braces {} are necessary for all arms of this statement
#179: FILE: fpu/softfloat.c:4042:
+ if ( aSign != bSign ) return aSign || ( (uint32_t) ( ( av | bv )<<1 ) == 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#180: FILE: fpu/softfloat.c:4043:
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
ERROR: space prohibited before that close parenthesis ')'
#180: FILE: fpu/softfloat.c:4043:
+ return ( av == bv ) || ( aSign ^ ( av < bv ) );
ERROR: space prohibited after that open parenthesis '('
#198: FILE: fpu/softfloat.c:4061:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#198: FILE: fpu/softfloat.c:4061:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#199: FILE: fpu/softfloat.c:4062:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#199: FILE: fpu/softfloat.c:4062:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited after that open parenthesis '('
#207: FILE: fpu/softfloat.c:4070:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#207: FILE: fpu/softfloat.c:4070:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#208: FILE: fpu/softfloat.c:4071:
+ bSign = extractFloat16Sign( b );
ERROR: space prohibited before that close parenthesis ')'
#208: FILE: fpu/softfloat.c:4071:
+ bSign = extractFloat16Sign( b );
WARNING: line over 80 characters
#211: FILE: fpu/softfloat.c:4074:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: spaces required around that '<<' (ctx:VxV)
#211: FILE: fpu/softfloat.c:4074:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
^
ERROR: space prohibited after that open parenthesis '('
#211: FILE: fpu/softfloat.c:4074:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: space prohibited before that close parenthesis ')'
#211: FILE: fpu/softfloat.c:4074:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: trailing statements should be on next line
#211: FILE: fpu/softfloat.c:4074:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
ERROR: braces {} are necessary for all arms of this statement
#211: FILE: fpu/softfloat.c:4074:
+ if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( av | bv )<<1 ) != 0 );
[...]
ERROR: space prohibited after that open parenthesis '('
#212: FILE: fpu/softfloat.c:4075:
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
ERROR: space prohibited before that close parenthesis ')'
#212: FILE: fpu/softfloat.c:4075:
+ return ( av != bv ) && ( aSign ^ ( av < bv ) );
ERROR: space prohibited after that open parenthesis '('
#228: FILE: fpu/softfloat.c:4091:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited before that close parenthesis ')'
#228: FILE: fpu/softfloat.c:4091:
+ if ( ( ( extractFloat16Exp( a ) == 0x1F ) && extractFloat16Frac( a ) )
ERROR: space prohibited after that open parenthesis '('
#229: FILE: fpu/softfloat.c:4092:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
ERROR: space prohibited before that close parenthesis ')'
#229: FILE: fpu/softfloat.c:4092:
+ || ( ( extractFloat16Exp( b ) == 0x1F ) && extractFloat16Frac( b ) )
total: 84 errors, 4 warnings, 236 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 21/30: target/arm/translate-a64: add FP16 2-reg misc compare (zero)...
Checking PATCH 22/30: target/arm/translate-a64.c: add FP16 FAGCT to AdvSIMD 3 Same...
Checking PATCH 23/30: softfloat: add float16_rem and float16_muladd (!CHECK)...
ERROR: space prohibited after that open parenthesis '('
#100: FILE: fpu/softfloat.c:3905:
+ aSig = extractFloat32Frac( a );
ERROR: space prohibited before that close parenthesis ')'
#100: FILE: fpu/softfloat.c:3905:
+ aSig = extractFloat32Frac( a );
ERROR: space prohibited after that open parenthesis '('
#101: FILE: fpu/softfloat.c:3906:
+ aExp = extractFloat32Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#101: FILE: fpu/softfloat.c:3906:
+ aExp = extractFloat32Exp( a );
ERROR: space prohibited after that open parenthesis '('
#102: FILE: fpu/softfloat.c:3907:
+ aSign = extractFloat32Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#102: FILE: fpu/softfloat.c:3907:
+ aSign = extractFloat32Sign( a );
ERROR: space prohibited after that open parenthesis '('
#103: FILE: fpu/softfloat.c:3908:
+ bSig = extractFloat32Frac( b );
ERROR: space prohibited before that close parenthesis ')'
#103: FILE: fpu/softfloat.c:3908:
+ bSig = extractFloat32Frac( b );
ERROR: space prohibited after that open parenthesis '('
#104: FILE: fpu/softfloat.c:3909:
+ bExp = extractFloat32Exp( b );
ERROR: space prohibited before that close parenthesis ')'
#104: FILE: fpu/softfloat.c:3909:
+ bExp = extractFloat32Exp( b );
ERROR: space prohibited after that open parenthesis '('
#105: FILE: fpu/softfloat.c:3910:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#105: FILE: fpu/softfloat.c:3910:
+ if ( aExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#106: FILE: fpu/softfloat.c:3911:
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
ERROR: space prohibited before that close parenthesis ')'
#106: FILE: fpu/softfloat.c:3911:
+ if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
ERROR: space prohibited after that open parenthesis '('
#112: FILE: fpu/softfloat.c:3917:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited before that close parenthesis ')'
#112: FILE: fpu/softfloat.c:3917:
+ if ( bExp == 0xFF ) {
ERROR: space prohibited after that open parenthesis '('
#118: FILE: fpu/softfloat.c:3923:
+ if ( bExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#118: FILE: fpu/softfloat.c:3923:
+ if ( bExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#119: FILE: fpu/softfloat.c:3924:
+ if ( bSig == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#119: FILE: fpu/softfloat.c:3924:
+ if ( bSig == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#123: FILE: fpu/softfloat.c:3928:
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );
ERROR: space prohibited before that close parenthesis ')'
#123: FILE: fpu/softfloat.c:3928:
+ normalizeFloat32Subnormal( bSig, &bExp, &bSig );
ERROR: space prohibited after that open parenthesis '('
#125: FILE: fpu/softfloat.c:3930:
+ if ( aExp == 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#125: FILE: fpu/softfloat.c:3930:
+ if ( aExp == 0 ) {
ERROR: space prohibited after that open parenthesis '('
#126: FILE: fpu/softfloat.c:3931:
+ if ( aSig == 0 ) return a;
ERROR: space prohibited before that close parenthesis ')'
#126: FILE: fpu/softfloat.c:3931:
+ if ( aSig == 0 ) return a;
ERROR: trailing statements should be on next line
#126: FILE: fpu/softfloat.c:3931:
+ if ( aSig == 0 ) return a;
ERROR: braces {} are necessary for all arms of this statement
#126: FILE: fpu/softfloat.c:3931:
+ if ( aSig == 0 ) return a;
[...]
ERROR: space prohibited after that open parenthesis '('
#127: FILE: fpu/softfloat.c:3932:
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );
ERROR: space prohibited before that close parenthesis ')'
#127: FILE: fpu/softfloat.c:3932:
+ normalizeFloat32Subnormal( aSig, &aExp, &aSig );
ERROR: space prohibited after that open parenthesis '('
#132: FILE: fpu/softfloat.c:3937:
+ if ( expDiff < 32 ) {
ERROR: space prohibited before that close parenthesis ')'
#132: FILE: fpu/softfloat.c:3937:
+ if ( expDiff < 32 ) {
ERROR: space prohibited after that open parenthesis '('
#135: FILE: fpu/softfloat.c:3940:
+ if ( expDiff < 0 ) {
ERROR: space prohibited before that close parenthesis ')'
#135: FILE: fpu/softfloat.c:3940:
+ if ( expDiff < 0 ) {
ERROR: space prohibited after that open parenthesis '('
#136: FILE: fpu/softfloat.c:3941:
+ if ( expDiff < -1 ) return a;
ERROR: space prohibited before that close parenthesis ')'
#136: FILE: fpu/softfloat.c:3941:
+ if ( expDiff < -1 ) return a;
ERROR: trailing statements should be on next line
#136: FILE: fpu/softfloat.c:3941:
+ if ( expDiff < -1 ) return a;
ERROR: braces {} are necessary for all arms of this statement
#136: FILE: fpu/softfloat.c:3941:
+ if ( expDiff < -1 ) return a;
[...]
ERROR: space prohibited after that open parenthesis '('
#139: FILE: fpu/softfloat.c:3944:
+ q = ( bSig <= aSig );
ERROR: space prohibited before that close parenthesis ')'
#139: FILE: fpu/softfloat.c:3944:
+ q = ( bSig <= aSig );
ERROR: space prohibited after that open parenthesis '('
#140: FILE: fpu/softfloat.c:3945:
+ if ( q ) aSig -= bSig;
ERROR: space prohibited before that close parenthesis ')'
#140: FILE: fpu/softfloat.c:3945:
+ if ( q ) aSig -= bSig;
ERROR: trailing statements should be on next line
#140: FILE: fpu/softfloat.c:3945:
+ if ( q ) aSig -= bSig;
ERROR: braces {} are necessary for all arms of this statement
#140: FILE: fpu/softfloat.c:3945:
+ if ( q ) aSig -= bSig;
[...]
ERROR: space prohibited after that open parenthesis '('
#141: FILE: fpu/softfloat.c:3946:
+ if ( 0 < expDiff ) {
ERROR: space prohibited before that close parenthesis ')'
#141: FILE: fpu/softfloat.c:3946:
+ if ( 0 < expDiff ) {
ERROR: spaces required around that '<<' (ctx:VxV)
#142: FILE: fpu/softfloat.c:3947:
+ q = ( ( (uint64_t) aSig )<<32 ) / bSig;
^
ERROR: space prohibited after that open parenthesis '('
#142: FILE: fpu/softfloat.c:3947:
+ q = ( ( (uint64_t) aSig )<<32 ) / bSig;
ERROR: space prohibited before that close parenthesis ')'
#142: FILE: fpu/softfloat.c:3947:
+ q = ( ( (uint64_t) aSig )<<32 ) / bSig;
ERROR: spaces required around that '>>' (ctx:VxV)
#145: FILE: fpu/softfloat.c:3950:
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
^
ERROR: spaces required around that '<<' (ctx:VxV)
#145: FILE: fpu/softfloat.c:3950:
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
^
ERROR: space prohibited after that open parenthesis '('
#145: FILE: fpu/softfloat.c:3950:
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
ERROR: space prohibited before that close parenthesis ')'
#145: FILE: fpu/softfloat.c:3950:
+ aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;
ERROR: else should follow close brace '}'
#147: FILE: fpu/softfloat.c:3952:
+ }
+ else {
ERROR: else should follow close brace '}'
#152: FILE: fpu/softfloat.c:3957:
+ }
+ else {
ERROR: space prohibited after that open parenthesis '('
#153: FILE: fpu/softfloat.c:3958:
+ if ( bSig <= aSig ) aSig -= bSig;
ERROR: space prohibited before that close parenthesis ')'
#153: FILE: fpu/softfloat.c:3958:
+ if ( bSig <= aSig ) aSig -= bSig;
ERROR: trailing statements should be on next line
#153: FILE: fpu/softfloat.c:3958:
+ if ( bSig <= aSig ) aSig -= bSig;
ERROR: braces {} are necessary for all arms of this statement
#153: FILE: fpu/softfloat.c:3958:
+ if ( bSig <= aSig ) aSig -= bSig;
[...]
ERROR: spaces required around that '<<' (ctx:VxV)
#154: FILE: fpu/softfloat.c:3959:
+ aSig64 = ( (uint64_t) aSig )<<40;
^
ERROR: space prohibited after that open parenthesis '('
#154: FILE: fpu/softfloat.c:3959:
+ aSig64 = ( (uint64_t) aSig )<<40;
ERROR: space prohibited before that close parenthesis ')'
#154: FILE: fpu/softfloat.c:3959:
+ aSig64 = ( (uint64_t) aSig )<<40;
ERROR: spaces required around that '<<' (ctx:VxV)
#155: FILE: fpu/softfloat.c:3960:
+ bSig64 = ( (uint64_t) bSig )<<40;
^
ERROR: space prohibited after that open parenthesis '('
#155: FILE: fpu/softfloat.c:3960:
+ bSig64 = ( (uint64_t) bSig )<<40;
ERROR: space prohibited before that close parenthesis ')'
#155: FILE: fpu/softfloat.c:3960:
+ bSig64 = ( (uint64_t) bSig )<<40;
ERROR: space prohibited after that open parenthesis '('
#157: FILE: fpu/softfloat.c:3962:
+ while ( 0 < expDiff ) {
ERROR: space prohibited before that close parenthesis ')'
#157: FILE: fpu/softfloat.c:3962:
+ while ( 0 < expDiff ) {
ERROR: space prohibited after that open parenthesis '('
#158: FILE: fpu/softfloat.c:3963:
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );
ERROR: space prohibited before that close parenthesis ')'
#158: FILE: fpu/softfloat.c:3963:
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );
ERROR: space prohibited after that open parenthesis '('
#159: FILE: fpu/softfloat.c:3964:
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;
ERROR: space prohibited before that close parenthesis ')'
#159: FILE: fpu/softfloat.c:3964:
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;
ERROR: space prohibited after that '-' (ctx:WxW)
#160: FILE: fpu/softfloat.c:3965:
+ aSig64 = - ( ( bSig * q64 )<<38 );
^
ERROR: spaces required around that '<<' (ctx:VxV)
#160: FILE: fpu/softfloat.c:3965:
+ aSig64 = - ( ( bSig * q64 )<<38 );
^
ERROR: space prohibited after that open parenthesis '('
#160: FILE: fpu/softfloat.c:3965:
+ aSig64 = - ( ( bSig * q64 )<<38 );
ERROR: space prohibited before that close parenthesis ')'
#160: FILE: fpu/softfloat.c:3965:
+ aSig64 = - ( ( bSig * q64 )<<38 );
ERROR: space prohibited after that open parenthesis '('
#164: FILE: fpu/softfloat.c:3969:
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );
ERROR: space prohibited before that close parenthesis ')'
#164: FILE: fpu/softfloat.c:3969:
+ q64 = estimateDiv128To64( aSig64, 0, bSig64 );
ERROR: space prohibited after that open parenthesis '('
#165: FILE: fpu/softfloat.c:3970:
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;
ERROR: space prohibited before that close parenthesis ')'
#165: FILE: fpu/softfloat.c:3970:
+ q64 = ( 2 < q64 ) ? q64 - 2 : 0;
ERROR: spaces required around that '>>' (ctx:VxV)
#166: FILE: fpu/softfloat.c:3971:
+ q = q64>>( 64 - expDiff );
^
ERROR: space prohibited after that open parenthesis '('
#166: FILE: fpu/softfloat.c:3971:
+ q = q64>>( 64 - expDiff );
ERROR: space prohibited before that close parenthesis ')'
#166: FILE: fpu/softfloat.c:3971:
+ q = q64>>( 64 - expDiff );
ERROR: spaces required around that '>>' (ctx:VxV)
#168: FILE: fpu/softfloat.c:3973:
+ aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
^
ERROR: spaces required around that '<<' (ctx:VxV)
#168: FILE: fpu/softfloat.c:3973:
+ aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
^
ERROR: space prohibited after that open parenthesis '('
#168: FILE: fpu/softfloat.c:3973:
+ aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
ERROR: space prohibited before that close parenthesis ')'
#168: FILE: fpu/softfloat.c:3973:
+ aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;
ERROR: space prohibited after that open parenthesis '('
#174: FILE: fpu/softfloat.c:3979:
+ } while ( 0 <= (int32_t) aSig );
ERROR: space prohibited before that close parenthesis ')'
#174: FILE: fpu/softfloat.c:3979:
+ } while ( 0 <= (int32_t) aSig );
ERROR: space prohibited after that open parenthesis '('
#176: FILE: fpu/softfloat.c:3981:
+ if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
ERROR: space prohibited before that close parenthesis ')'
#176: FILE: fpu/softfloat.c:3981:
+ if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {
ERROR: space prohibited after that open parenthesis '('
#179: FILE: fpu/softfloat.c:3984:
+ zSign = ( (int32_t) aSig < 0 );
ERROR: space prohibited before that close parenthesis ')'
#179: FILE: fpu/softfloat.c:3984:
+ zSign = ( (int32_t) aSig < 0 );
ERROR: space prohibited after that '-' (ctx:WxW)
#180: FILE: fpu/softfloat.c:3985:
+ if ( zSign ) aSig = - aSig;
^
ERROR: space prohibited after that open parenthesis '('
#180: FILE: fpu/softfloat.c:3985:
+ if ( zSign ) aSig = - aSig;
ERROR: space prohibited before that close parenthesis ')'
#180: FILE: fpu/softfloat.c:3985:
+ if ( zSign ) aSig = - aSig;
ERROR: trailing statements should be on next line
#180: FILE: fpu/softfloat.c:3985:
+ if ( zSign ) aSig = - aSig;
ERROR: braces {} are necessary for all arms of this statement
#180: FILE: fpu/softfloat.c:3985:
+ if ( zSign ) aSig = - aSig;
[...]
WARNING: line over 80 characters
#296: FILE: fpu/softfloat.c:4101:
+ return roundAndPackFloat16(cSign ^ signflip, cExp, cSig, true, status);
total: 97 errors, 1 warnings, 399 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/30: disas_simd_indexed: support half-precision operations...
Checking PATCH 25/30: softfloat: float16_round_to_int...
ERROR: space prohibited after that open parenthesis '('
#36: FILE: fpu/softfloat.c:3550:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#36: FILE: fpu/softfloat.c:3550:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited after that open parenthesis '('
#37: FILE: fpu/softfloat.c:3551:
+ if ( 0x19 <= aExp ) {
ERROR: space prohibited before that close parenthesis ')'
#37: FILE: fpu/softfloat.c:3551:
+ if ( 0x19 <= aExp ) {
ERROR: space prohibited after that open parenthesis '('
#38: FILE: fpu/softfloat.c:3552:
+ if ( ( aExp == 0x1F ) && extractFloat16Frac( a ) ) {
ERROR: space prohibited before that close parenthesis ')'
#38: FILE: fpu/softfloat.c:3552:
+ if ( ( aExp == 0x1F ) && extractFloat16Frac( a ) ) {
ERROR: space prohibited after that open parenthesis '('
#43: FILE: fpu/softfloat.c:3557:
+ if ( aExp <= 0xE ) {
ERROR: space prohibited before that close parenthesis ')'
#43: FILE: fpu/softfloat.c:3557:
+ if ( aExp <= 0xE ) {
ERROR: spaces required around that '<<' (ctx:VxV)
#44: FILE: fpu/softfloat.c:3558:
+ if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a;
^
ERROR: space prohibited after that open parenthesis '('
#44: FILE: fpu/softfloat.c:3558:
+ if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a;
ERROR: space prohibited before that close parenthesis ')'
#44: FILE: fpu/softfloat.c:3558:
+ if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a;
ERROR: trailing statements should be on next line
#44: FILE: fpu/softfloat.c:3558:
+ if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a;
ERROR: braces {} are necessary for all arms of this statement
#44: FILE: fpu/softfloat.c:3558:
+ if ( (uint16_t) ( float16_val(a)<<1 ) == 0 ) return a;
[...]
ERROR: space prohibited after that open parenthesis '('
#46: FILE: fpu/softfloat.c:3560:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#46: FILE: fpu/softfloat.c:3560:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#49: FILE: fpu/softfloat.c:3563:
+ if ( ( aExp == 0xE ) && extractFloat16Frac( a ) ) {
ERROR: space prohibited before that close parenthesis ')'
#49: FILE: fpu/softfloat.c:3563:
+ if ( ( aExp == 0xE ) && extractFloat16Frac( a ) ) {
ERROR: space prohibited after that open parenthesis '('
#50: FILE: fpu/softfloat.c:3564:
+ return packFloat16( aSign, 0xF, 0 );
ERROR: space prohibited before that close parenthesis ')'
#50: FILE: fpu/softfloat.c:3564:
+ return packFloat16( aSign, 0xF, 0 );
ERROR: space prohibited after that open parenthesis '('
#64: FILE: fpu/softfloat.c:3578:
+ return packFloat16( aSign, 0, 0 );
ERROR: space prohibited before that close parenthesis ')'
#64: FILE: fpu/softfloat.c:3578:
+ return packFloat16( aSign, 0, 0 );
ERROR: spaces required around that '>>' (ctx:VxV)
#72: FILE: fpu/softfloat.c:3586:
+ z += lastBitMask>>1;
^
ERROR: space prohibited after that '~' (ctx:WxW)
#95: FILE: fpu/softfloat.c:3609:
+ z &= ~ roundBitsMask;
^
total: 23 errors, 0 warnings, 95 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 26/30: tests/test-softfloat: add a simple test framework...
WARNING: line over 80 characters
#88: FILE: tests/test-softfloat.c:31:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x06b1, 0x3c00, 0 },
WARNING: line over 80 characters
#89: FILE: tests/test-softfloat.c:32:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x6966, 0x6966, 0 },
WARNING: line over 80 characters
#90: FILE: tests/test-softfloat.c:33:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x83c0, 0x8000, 0 },
WARNING: line over 80 characters
#91: FILE: tests/test-softfloat.c:34:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xa619, 0x8000, 0 },
WARNING: line over 80 characters
#92: FILE: tests/test-softfloat.c:35:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x9cf4, 0x8000, 0 },
WARNING: line over 80 characters
#93: FILE: tests/test-softfloat.c:36:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee11, 0xee11, 0 },
WARNING: line over 80 characters
#94: FILE: tests/test-softfloat.c:37:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0xee5c, 0xee5c, 0 },
WARNING: line over 80 characters
#95: FILE: tests/test-softfloat.c:38:
+ { { .float_detect_tininess = 1, .float_rounding_mode = 2}, 0x8004, 0x8000, 0 }
total: 0 errors, 8 warnings, 84 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 27/30: target/arm/translate-a64.c: add FP16 FRINTP to 2 reg misc...
Checking PATCH 28/30: softfloat: float16_to_int16 conversion...
WARNING: line over 80 characters
#35: FILE: fpu/softfloat.c:146:
+static int16_t roundAndPackInt16(flag zSign, uint32_t absZ, float_status *status)
ERROR: space prohibited after that open parenthesis '('
#43: FILE: fpu/softfloat.c:154:
+ roundNearestEven = ( roundingMode == float_round_nearest_even );
ERROR: space prohibited before that close parenthesis ')'
#43: FILE: fpu/softfloat.c:154:
+ roundNearestEven = ( roundingMode == float_round_nearest_even );
ERROR: spaces required around that '>>' (ctx:VxV)
#64: FILE: fpu/softfloat.c:175:
+ absZ = ( absZ + roundIncrement )>>7;
^
ERROR: space prohibited after that open parenthesis '('
#64: FILE: fpu/softfloat.c:175:
+ absZ = ( absZ + roundIncrement )>>7;
ERROR: space prohibited before that close parenthesis ')'
#64: FILE: fpu/softfloat.c:175:
+ absZ = ( absZ + roundIncrement )>>7;
ERROR: space prohibited after that '~' (ctx:WxW)
#65: FILE: fpu/softfloat.c:176:
+ absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
^
ERROR: space prohibited after that open parenthesis '('
#65: FILE: fpu/softfloat.c:176:
+ absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
ERROR: space prohibited before that close parenthesis ')'
#65: FILE: fpu/softfloat.c:176:
+ absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
ERROR: space prohibited after that '-' (ctx:WxW)
#67: FILE: fpu/softfloat.c:178:
+ if ( zSign ) z = - z;
^
ERROR: space prohibited after that open parenthesis '('
#67: FILE: fpu/softfloat.c:178:
+ if ( zSign ) z = - z;
ERROR: space prohibited before that close parenthesis ')'
#67: FILE: fpu/softfloat.c:178:
+ if ( zSign ) z = - z;
ERROR: trailing statements should be on next line
#67: FILE: fpu/softfloat.c:178:
+ if ( zSign ) z = - z;
ERROR: braces {} are necessary for all arms of this statement
#67: FILE: fpu/softfloat.c:178:
+ if ( zSign ) z = - z;
[...]
ERROR: spaces required around that '>>' (ctx:VxV)
#69: FILE: fpu/softfloat.c:180:
+ if ( ( absZ>>16 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
^
ERROR: space prohibited after that open parenthesis '('
#69: FILE: fpu/softfloat.c:180:
+ if ( ( absZ>>16 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
ERROR: space prohibited before that close parenthesis ')'
#69: FILE: fpu/softfloat.c:180:
+ if ( ( absZ>>16 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
ERROR: space prohibited after that open parenthesis '('
#105: FILE: fpu/softfloat.c:4585:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited before that close parenthesis ')'
#105: FILE: fpu/softfloat.c:4585:
+ aSig = extractFloat16Frac( a );
ERROR: space prohibited after that open parenthesis '('
#106: FILE: fpu/softfloat.c:4586:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited before that close parenthesis ')'
#106: FILE: fpu/softfloat.c:4586:
+ aExp = extractFloat16Exp( a );
ERROR: space prohibited after that open parenthesis '('
#107: FILE: fpu/softfloat.c:4587:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited before that close parenthesis ')'
#107: FILE: fpu/softfloat.c:4587:
+ aSign = extractFloat16Sign( a );
ERROR: space prohibited after that open parenthesis '('
#108: FILE: fpu/softfloat.c:4588:
+ if ( ( aExp == 0x1F ) && aSig ) aSign = 0;
ERROR: space prohibited before that close parenthesis ')'
#108: FILE: fpu/softfloat.c:4588:
+ if ( ( aExp == 0x1F ) && aSig ) aSign = 0;
ERROR: trailing statements should be on next line
#108: FILE: fpu/softfloat.c:4588:
+ if ( ( aExp == 0x1F ) && aSig ) aSign = 0;
ERROR: braces {} are necessary for all arms of this statement
#108: FILE: fpu/softfloat.c:4588:
+ if ( ( aExp == 0x1F ) && aSig ) aSign = 0;
[...]
ERROR: space prohibited after that open parenthesis '('
#109: FILE: fpu/softfloat.c:4589:
+ if ( aExp ) aSig |= 0x0400; /* implicit bit */
ERROR: space prohibited before that close parenthesis ')'
#109: FILE: fpu/softfloat.c:4589:
+ if ( aExp ) aSig |= 0x0400; /* implicit bit */
ERROR: trailing statements should be on next line
#109: FILE: fpu/softfloat.c:4589:
+ if ( aExp ) aSig |= 0x0400; /* implicit bit */
ERROR: braces {} are necessary for all arms of this statement
#109: FILE: fpu/softfloat.c:4589:
+ if ( aExp ) aSig |= 0x0400; /* implicit bit */
[...]
ERROR: space prohibited after that open parenthesis '('
#124: FILE: fpu/softfloat.c:4604:
+ shift32RightJamming( aSig, 3 - aExp, &aSig );
ERROR: space prohibited before that close parenthesis ')'
#124: FILE: fpu/softfloat.c:4604:
+ shift32RightJamming( aSig, 3 - aExp, &aSig );
total: 32 errors, 1 warnings, 117 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 29/30: tests/test-softfloat: add f16_to_int16 conversion test...
Checking PATCH 30/30: target/arm/translate-a64.c: add FP16 FCVTPS to 2 reg misc...
=== OUTPUT END ===
Test command exited with code: 1
---
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Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 59+ messages in thread* Re: [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress)
2017-10-13 16:24 [Qemu-devel] [RFC PATCH 00/30] v8.2 half-precision support (work-in-progress) Alex Bennée
` (31 preceding siblings ...)
2017-10-13 16:59 ` no-reply
@ 2017-10-17 2:34 ` Richard Henderson
32 siblings, 0 replies; 59+ messages in thread
From: Richard Henderson @ 2017-10-17 2:34 UTC (permalink / raw)
To: Alex Bennée; +Cc: peter.maydell, qemu-devel, qemu-arm
On 10/13/2017 09:24 AM, Alex Bennée wrote:
> SoftFloat
> =========
>
> Previously I had pondered if switching to the newer SoftFloat3 would
> be a worthwhile. While the upstream project is certainly open to
> accepting patches it would be a slow process given the changes we've
> made over the years. As a result I've decided to stick with expanding
> our current code.
>
> Most of the helpers have been done fairly mechanically by copying the
> float32 equivalent, filing off the 32's, replacing with 16's and
> adjusting the constants appropriately (min/max exp, NaNs etc). I've
> done this in conjunction with reading the SoftFloat3 code as a sanity
> check although in places the design is a little different.
I think we need a re-think of the approach here.
For the most part, the code would be sharable *if* our internal representation
between float32 and float16 were identical. So that all that's different are
unpacking and repacking routines at the beginning and end.
Unfortunately, the existing float32 code does lots of random unpacking in the
middle of other classification. Fixing that would be a prerequisite. Is it
worth upending our code base to make this happen?
Failing that, we need to stop using magic numbers, since so many of them were
wrong. We need names for these. We can start with float16 and then later
backport those numbers into larger formats.
r~
^ permalink raw reply [flat|nested] 59+ messages in thread