From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: cota@braap.org, Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v6 04/50] tcg: Propagate TCGOp down to allocators
Date: Mon, 16 Oct 2017 10:25:23 -0700 [thread overview]
Message-ID: <20171016172609.23422-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20171016172609.23422-1-richard.henderson@linaro.org>
From: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/tcg.c | 78 ++++++++++++++++++++++++++++++++-------------------------------
1 file changed, 40 insertions(+), 38 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4f56077f64..147b8904d8 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2334,25 +2334,24 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
}
}
-static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
- TCGLifeData arg_life)
+static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op)
{
- TCGTemp *ots = &s->temps[args[0]];
- tcg_target_ulong val = args[1];
+ TCGTemp *ots = &s->temps[op->args[0]];
+ tcg_target_ulong val = op->args[1];
- tcg_reg_alloc_do_movi(s, ots, val, arg_life);
+ tcg_reg_alloc_do_movi(s, ots, val, op->life);
}
-static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
- const TCGArg *args, TCGLifeData arg_life)
+static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
{
+ const TCGLifeData arg_life = op->life;
TCGRegSet allocated_regs;
TCGTemp *ts, *ots;
TCGType otype, itype;
allocated_regs = s->reserved_regs;
- ots = &s->temps[args[0]];
- ts = &s->temps[args[1]];
+ ots = &s->temps[op->args[0]];
+ ts = &s->temps[op->args[1]];
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
@@ -2382,7 +2381,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
liveness analysis disabled). */
tcg_debug_assert(NEED_SYNC_ARG(0));
if (!ots->mem_allocated) {
- temp_allocate_frame(s, args[0]);
+ temp_allocate_frame(s, op->args[0]);
}
tcg_out_st(s, otype, ts->reg, ots->mem_base->reg, ots->mem_offset);
if (IS_DEAD_ARG(1)) {
@@ -2416,10 +2415,10 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
}
}
-static void tcg_reg_alloc_op(TCGContext *s,
- const TCGOpDef *def, TCGOpcode opc,
- const TCGArg *args, TCGLifeData arg_life)
+static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
{
+ const TCGLifeData arg_life = op->life;
+ const TCGOpDef * const def = &tcg_op_defs[op->opc];
TCGRegSet i_allocated_regs;
TCGRegSet o_allocated_regs;
int i, k, nb_iargs, nb_oargs;
@@ -2430,21 +2429,24 @@ static void tcg_reg_alloc_op(TCGContext *s,
TCGArg new_args[TCG_MAX_OP_ARGS];
int const_args[TCG_MAX_OP_ARGS];
+ /* Sanity check that we've not introduced any unhandled opcodes. */
+ tcg_debug_assert(!(def->flags & TCG_OPF_NOT_PRESENT));
+
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
/* copy constants */
memcpy(new_args + nb_oargs + nb_iargs,
- args + nb_oargs + nb_iargs,
+ op->args + nb_oargs + nb_iargs,
sizeof(TCGArg) * def->nb_cargs);
i_allocated_regs = s->reserved_regs;
o_allocated_regs = s->reserved_regs;
/* satisfy input constraints */
- for(k = 0; k < nb_iargs; k++) {
+ for (k = 0; k < nb_iargs; k++) {
i = def->sorted_args[nb_oargs + k];
- arg = args[i];
+ arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = &s->temps[arg];
@@ -2462,7 +2464,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
if (ts->fixed_reg) {
/* if fixed register, we must allocate a new register
if the alias is not the same register */
- if (arg != args[arg_ct->alias_index])
+ if (arg != op->args[arg_ct->alias_index])
goto allocate_in_reg;
} else {
/* if the input is aliased to an output and if it is
@@ -2503,7 +2505,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* mark dead temporaries and free the associated registers */
for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
if (IS_DEAD_ARG(i)) {
- temp_dead(s, &s->temps[args[i]]);
+ temp_dead(s, &s->temps[op->args[i]]);
}
}
@@ -2527,7 +2529,7 @@ static void tcg_reg_alloc_op(TCGContext *s,
/* satisfy the output constraints */
for(k = 0; k < nb_oargs; k++) {
i = def->sorted_args[k];
- arg = args[i];
+ arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = &s->temps[arg];
if ((arg_ct->ct & TCG_CT_ALIAS)
@@ -2566,11 +2568,11 @@ static void tcg_reg_alloc_op(TCGContext *s,
}
/* emit instruction */
- tcg_out_op(s, opc, new_args, const_args);
+ tcg_out_op(s, op->opc, new_args, const_args);
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
- ts = &s->temps[args[i]];
+ ts = &s->temps[op->args[i]];
reg = new_args[i];
if (ts->fixed_reg && ts->reg != reg) {
tcg_out_mov(s, ts->type, ts->reg, reg);
@@ -2589,9 +2591,11 @@ static void tcg_reg_alloc_op(TCGContext *s,
#define STACK_DIR(x) (x)
#endif
-static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
- const TCGArg * const args, TCGLifeData arg_life)
+static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
{
+ const int nb_oargs = op->callo;
+ const int nb_iargs = op->calli;
+ const TCGLifeData arg_life = op->life;
int flags, nb_regs, i;
TCGReg reg;
TCGArg arg;
@@ -2602,8 +2606,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
int allocate_args;
TCGRegSet allocated_regs;
- func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
- flags = args[nb_oargs + nb_iargs + 1];
+ func_addr = (tcg_insn_unit *)(intptr_t)op->args[nb_oargs + nb_iargs];
+ flags = op->args[nb_oargs + nb_iargs + 1];
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
if (nb_regs > nb_iargs) {
@@ -2622,8 +2626,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
}
stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
- for(i = nb_regs; i < nb_iargs; i++) {
- arg = args[nb_oargs + i];
+ for (i = nb_regs; i < nb_iargs; i++) {
+ arg = op->args[nb_oargs + i];
#ifdef TCG_TARGET_STACK_GROWSUP
stack_offset -= sizeof(tcg_target_long);
#endif
@@ -2640,8 +2644,8 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
/* assign input registers */
allocated_regs = s->reserved_regs;
- for(i = 0; i < nb_regs; i++) {
- arg = args[nb_oargs + i];
+ for (i = 0; i < nb_regs; i++) {
+ arg = op->args[nb_oargs + i];
if (arg != TCG_CALL_DUMMY_ARG) {
ts = &s->temps[arg];
reg = tcg_target_call_iarg_regs[i];
@@ -2663,9 +2667,9 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
}
/* mark dead temporaries and free the associated registers */
- for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
+ for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
if (IS_DEAD_ARG(i)) {
- temp_dead(s, &s->temps[args[i]]);
+ temp_dead(s, &s->temps[op->args[i]]);
}
}
@@ -2690,7 +2694,7 @@ static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
/* assign output registers and emit moves if needed */
for(i = 0; i < nb_oargs; i++) {
- arg = args[i];
+ arg = op->args[i];
ts = &s->temps[arg];
reg = tcg_target_call_oarg_regs[i];
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
@@ -2838,8 +2842,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
TCGOp * const op = &s->gen_op_buf[oi];
TCGOpcode opc = op->opc;
- const TCGOpDef *def = &tcg_op_defs[opc];
- TCGLifeData arg_life = op->life;
oi_next = op->next;
#ifdef CONFIG_PROFILER
@@ -2849,11 +2851,11 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
- tcg_reg_alloc_mov(s, def, op->args, arg_life);
+ tcg_reg_alloc_mov(s, op);
break;
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
- tcg_reg_alloc_movi(s, op->args, arg_life);
+ tcg_reg_alloc_movi(s, op);
break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
@@ -2878,7 +2880,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
tcg_out_label(s, arg_label(op->args[0]), s->code_ptr);
break;
case INDEX_op_call:
- tcg_reg_alloc_call(s, op->callo, op->calli, op->args, arg_life);
+ tcg_reg_alloc_call(s, op);
break;
default:
/* Sanity check that we've not introduced any unhandled opcodes. */
@@ -2886,7 +2888,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
/* Note: in order to speed up the code, it would be much
faster to have specialized register allocator functions for
some common argument patterns */
- tcg_reg_alloc_op(s, def, opc, op->args, arg_life);
+ tcg_reg_alloc_op(s, op);
break;
}
#ifdef CONFIG_DEBUG_TCG
--
2.13.6
next prev parent reply other threads:[~2017-10-16 17:26 UTC|newest]
Thread overview: 94+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-16 17:25 [Qemu-devel] [PATCH v6 00/50] tcg tb_lock removal Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 01/50] tcg: Merge opcode arguments into TCGOp Richard Henderson
2017-10-17 20:04 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 02/50] tcg: Propagate args to op->args in optimizer Richard Henderson
2017-10-17 20:28 ` Emilio G. Cota
2017-10-17 20:33 ` Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 03/50] tcg: Propagate args to op->args in tcg.c Richard Henderson
2017-10-17 20:29 ` Emilio G. Cota
2017-10-16 17:25 ` Richard Henderson [this message]
2017-10-17 20:33 ` [Qemu-devel] [PATCH v6 04/50] tcg: Propagate TCGOp down to allocators Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 05/50] tcg: Introduce arg_temp Richard Henderson
2017-10-17 20:43 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 06/50] tcg: Add temp_global bit to TCGTemp Richard Henderson
2017-10-17 20:43 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 07/50] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG Richard Henderson
2017-10-17 20:56 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 08/50] tcg: Introduce temp_arg Richard Henderson
2017-10-17 21:00 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 09/50] tcg: Use per-temp state data in liveness Richard Henderson
2017-10-17 21:50 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 10/50] tcg: Avoid loops against variable bounds Richard Henderson
2017-10-17 22:03 ` Emilio G. Cota
2017-10-18 4:30 ` Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 11/50] tcg: Change temp_allocate_frame arg to TCGTemp Richard Henderson
2017-10-17 22:07 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 12/50] tcg: Remove unused TCG_CALL_DUMMY_TCGV Richard Henderson
2017-10-17 22:07 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 13/50] tcg: Export temp_idx Richard Henderson
2017-10-17 22:10 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 14/50] tcg: Use per-temp state data in optimize Richard Henderson
2017-10-17 22:16 ` Emilio G. Cota
2017-10-18 4:31 ` Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 15/50] tcg: Push tcg_ctx into generator functions Richard Henderson
2017-10-17 22:17 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 16/50] tcg: Push tcg_ctx into tcg_gen_callN Richard Henderson
2017-10-17 22:18 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 17/50] tcg: Introduce index_arg Richard Henderson
2017-10-17 22:52 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 18/50] tcg: Reserve temporary index 0 Richard Henderson
2017-10-17 23:19 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 19/50] target/alpha: Avoid translate_init unless tcg_enabled Richard Henderson
2017-10-17 23:27 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 20/50] qom: Introduce CPUClass.tcg_initialize Richard Henderson
2017-10-17 23:53 ` Emilio G. Cota
2017-10-18 19:12 ` Andreas Färber
2017-10-18 21:35 ` Philippe Mathieu-Daudé
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 21/50] tcg: Use pointers in TCGOp->args Richard Henderson
2017-10-18 4:13 ` Emilio G. Cota
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 22/50] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 23/50] hack dump tb->flags and tb->cflags Richard Henderson
2017-10-18 4:15 ` Emilio G. Cota
2017-10-18 4:49 ` Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 24/50] tcg: Add CPUState step_next_tb Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 25/50] tcg: Include CF_COUNT_MASK in CF_HASH_MASK Richard Henderson
2017-10-18 4:31 ` Emilio G. Cota
2017-10-20 2:27 ` Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 26/50] tcg: convert tb->cflags reads to tb_cflags(tb) Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 27/50] target/arm: check CF_PARALLEL instead of parallel_cpus Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 28/50] target/hppa: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 29/50] target/i386: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 30/50] target/m68k: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 31/50] target/s390x: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 32/50] target/sh4: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 33/50] target/sparc: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 34/50] tcg: " Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 35/50] cpu-exec: lookup/generate TB outside exclusive region during step_atomic Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 36/50] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 37/50] tcg: Remove CF_IGNORE_ICOUNT Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 38/50] translate-all: use a binary search tree to track TBs in TBContext Richard Henderson
2017-10-18 7:41 ` Paolo Bonzini
2017-10-18 18:19 ` Emilio G. Cota
2017-10-20 2:30 ` Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 39/50] exec-all: rename tb_free to tb_remove Richard Henderson
2017-10-16 17:25 ` [Qemu-devel] [PATCH v6 40/50] translate-all: report correct avg host TB size Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 41/50] tcg: take tb_ctx out of TCGContext Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 42/50] tcg: define tcg_init_ctx and make tcg_ctx a pointer Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 43/50] gen-icount: fold exitreq_label into TCGContext Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 44/50] tcg: introduce **tcg_ctxs to keep track of all TCGContext's Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 45/50] tcg: distribute profiling counters across TCGContext's Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 46/50] tcg: allocate optimizer temps with tcg_malloc Richard Henderson
2017-10-18 4:35 ` Emilio G. Cota
2017-10-18 20:24 ` Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 47/50] osdep: introduce qemu_mprotect_rwx/none Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 48/50] translate-all: use qemu_protect_rwx/none helpers Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 49/50] tcg: introduce regions to split code_gen_buffer Richard Henderson
2017-10-16 17:26 ` [Qemu-devel] [PATCH v6 50/50] tcg: enable multiple TCG contexts in softmmu Richard Henderson
2017-10-16 18:45 ` [Qemu-devel] [PATCH v6 00/50] tcg tb_lock removal no-reply
2017-10-18 4:04 ` Emilio G. Cota
2017-10-18 22:45 ` Emilio G. Cota
2017-10-19 13:05 ` Paolo Bonzini
2017-10-19 20:11 ` Emilio G. Cota
2017-10-20 7:10 ` Paolo Bonzini
2017-10-21 2:34 ` Emilio G. Cota
2017-10-26 1:47 ` Emilio G. Cota
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