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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: ehabkost@redhat.com, agraf@suse.de, imammedo@redhat.com,
	groug@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 27/34] ppc: pnv: normalize core/chip type names
Date: Tue, 17 Oct 2017 15:21:45 +1100	[thread overview]
Message-ID: <20171017042152.29443-28-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20171017042152.29443-1-david@gibson.dropbear.id.au>

From: Igor Mammedov <imammedo@redhat.com>

typically for cpus/core type names following convention is used

   new_type_prefix-superclass_typename

make PNV core/chip to follow common convention.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/pnv.c              |  2 +-
 hw/ppc/pnv_core.c         |  2 +-
 include/hw/ppc/pnv.h      | 11 +++++++----
 include/hw/ppc/pnv_core.h |  2 ++
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a2cb4a40ff..1e78b685a3 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -608,7 +608,7 @@ static void ppc_powernv_init(MachineState *machine)
 
     /* Create the processor chips */
     i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
-    chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%.*s",
+    chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
                                     i, machine->cpu_type);
     if (!object_class_by_name(chip_typename)) {
         error_report("invalid CPU model '%.*s' for %s machine",
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 91f02cb324..85b39a5b5e 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -252,5 +252,5 @@ type_init(pnv_core_register_types)
 
 char *pnv_core_typename(const char *model)
 {
-    return g_strdup_printf(TYPE_PNV_CORE "-%s", model);
+    return g_strdup_printf(PNV_CORE_TYPE_NAME("%s"), model);
 }
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index d80fa44bf0..f1bfa6c499 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -80,19 +80,22 @@ typedef struct PnvChipClass {
     uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
 } PnvChipClass;
 
-#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-power8e_v2.1"
+#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
+#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
+
+#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
 #define PNV_CHIP_POWER8E(obj) \
     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
 
-#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-power8_v2.0"
+#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
 #define PNV_CHIP_POWER8(obj) \
     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
 
-#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-power8nvl_v1.0"
+#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
 #define PNV_CHIP_POWER8NVL(obj) \
     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
 
-#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-power9_v2.0"
+#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
 #define PNV_CHIP_POWER9(obj) \
     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
 
diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
index 2955a41c90..3360c4b12d 100644
--- a/include/hw/ppc/pnv_core.h
+++ b/include/hw/ppc/pnv_core.h
@@ -45,6 +45,8 @@ typedef struct PnvCoreClass {
     ObjectClass *cpu_oc;
 } PnvCoreClass;
 
+#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
+#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
 extern char *pnv_core_typename(const char *model);
 
 #endif /* _PPC_PNV_CORE_H */
-- 
2.13.6

  parent reply	other threads:[~2017-10-17  4:22 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-17  4:21 [Qemu-devel] [PULL 00/34] ppc-for-2.11 queue 20171017 David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 01/34] macio: add missing registers to VMStateDescription David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 02/34] hw/ppc: use 0 instead of fdt_path_offset(fdt, "/") David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 03/34] target/ppc: Remove unused PPC 460 and 460F definitions David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 04/34] spapr: fix OF word name in comment David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 05/34] spapr: sanity check size of the CAS buffer David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 06/34] target/ppc: Add POWER9 DD2.0 model information David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 07/34] target/ppc: Fix carry flag setting for shift algebraic instructions David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 08/34] hw/ppc/spapr.c: abort unplug_request if previous unplug isn't done David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 09/34] qom: introduce type_register_static_array() David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 10/34] qom: add helper macro DEFINE_TYPES() David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 11/34] ppc: mpc8544ds/e500plat: use generic cpu_model parsing David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 12/34] ppc: mac_newworld: " David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 13/34] ppc: mac_oldworld: " David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 14/34] ppc: bamboo: " David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 15/34] ppc: replace cpu_model with cpu_type on ref405ep, taihu boards David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 16/34] ppc: virtex-ml507: replace cpu_model with cpu_type David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 17/34] ppc: 40p/prep: " David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 18/34] ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model() David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 19/34] ppc: move '-cpu foo, compat=xxx' parsing into ppc_cpu_parse_featurestr() David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 20/34] ppc: spapr: define core types statically David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 21/34] ppc: spapr: use cpu type name directly David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 22/34] ppc: spapr: register 'host' core type along with the rest of core types David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 23/34] ppc: spapr: use cpu model names as tcg defaults instead of aliases David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 24/34] ppc: move ppc_cpu_lookup_alias() before its first user David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 25/34] ppc: spapr: use generic cpu_model parsing David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 26/34] ppc: pnv: " David Gibson
2017-10-17  4:21 ` David Gibson [this message]
2017-10-17  4:21 ` [Qemu-devel] [PULL 28/34] ppc: pnv: drop PnvCoreClass::cpu_oc field David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 29/34] ppc: pnv: define core types statically David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 30/34] ppc: pnv: drop PnvChipClass::cpu_model field David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 31/34] ppc: pnv: consolidate type definitions and batch register them David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 32/34] spapr: Correct RAM size calculation for HPT resizing David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 33/34] spapr_pci: fail gracefully with non-pseries machine types David Gibson
2017-10-17  4:21 ` [Qemu-devel] [PULL 34/34] spapr_cpu_core: rewrite machine type sanity check David Gibson
2017-10-19  9:52 ` [Qemu-devel] [PULL 00/34] ppc-for-2.11 queue 20171017 Peter Maydell

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