From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: ehabkost@redhat.com, agraf@suse.de, imammedo@redhat.com,
groug@kaod.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Thomas Huth <thuth@redhat.com>,
David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PULL 03/34] target/ppc: Remove unused PPC 460 and 460F definitions
Date: Tue, 17 Oct 2017 15:21:21 +1100 [thread overview]
Message-ID: <20171017042152.29443-4-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20171017042152.29443-1-david@gibson.dropbear.id.au>
From: Thomas Huth <thuth@redhat.com>
We don't have any 460 or 460F CPUs in QEMU, so the init functions
are just dead code. Let's simply remove them (translate_init.c
is already big enough without them).
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate_init.c | 217 --------------------------------------------
1 file changed, 217 deletions(-)
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index c6399a3a0d..0d6379fcc5 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -4176,223 +4176,6 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_460 (CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MCSR, "MCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_CCR1, "CCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_BookE(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(20, 24, 28, 32);
-}
-
-POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 460 (guessed)";
- pcc->init_proc = init_proc_460;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_DCR | PPC_DCRX | PPC_DCRUX |
- PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVA |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
-static void init_proc_460F(CPUPPCState *env)
-{
- /* Time base */
- gen_tbl(env);
- gen_spr_BookE(env, 0x000000000000FFFFULL);
- gen_spr_440(env);
- gen_spr_usprgh(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_BOOKE_MCSR, "MCSR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_440_CCR1, "CCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
- &spr_read_generic, &spr_write_generic,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Memory management */
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = 64;
- env->nb_ways = 1;
- env->id_tlbs = 0;
- env->tlb_type = TLB_EMB;
-#endif
- init_excp_BookE(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* XXX: TODO: allocate internal IRQ controller */
-
- SET_FIT_PERIOD(12, 16, 20, 24);
- SET_WDT_PERIOD(20, 24, 28, 32);
-}
-
-POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "PowerPC 460F (guessed)";
- pcc->init_proc = init_proc_460F;
- pcc->check_pow = check_pow_nocheck;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
- PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
- PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
- PPC_FLOAT_STFIWX | PPC_MFTB |
- PPC_DCR | PPC_DCRX | PPC_DCRUX |
- PPC_WRTEE | PPC_MFAPIDI |
- PPC_CACHE | PPC_CACHE_ICBI |
- PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
- PPC_MEM_TLBSYNC | PPC_TLBIVA |
- PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
- PPC_440_SPEC;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_CE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_DWE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR);
- pcc->mmu_model = POWERPC_MMU_BOOKE;
- pcc->excp_model = POWERPC_EXCP_BOOKE;
- pcc->bus_model = PPC_FLAGS_INPUT_BookE;
- pcc->bfd_mach = bfd_mach_ppc_403;
- pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
- POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
-}
-
static void init_proc_MPC5xx(CPUPPCState *env)
{
/* Time base */
--
2.13.6
next prev parent reply other threads:[~2017-10-17 4:22 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-17 4:21 [Qemu-devel] [PULL 00/34] ppc-for-2.11 queue 20171017 David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 01/34] macio: add missing registers to VMStateDescription David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 02/34] hw/ppc: use 0 instead of fdt_path_offset(fdt, "/") David Gibson
2017-10-17 4:21 ` David Gibson [this message]
2017-10-17 4:21 ` [Qemu-devel] [PULL 04/34] spapr: fix OF word name in comment David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 05/34] spapr: sanity check size of the CAS buffer David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 06/34] target/ppc: Add POWER9 DD2.0 model information David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 07/34] target/ppc: Fix carry flag setting for shift algebraic instructions David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 08/34] hw/ppc/spapr.c: abort unplug_request if previous unplug isn't done David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 09/34] qom: introduce type_register_static_array() David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 10/34] qom: add helper macro DEFINE_TYPES() David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 11/34] ppc: mpc8544ds/e500plat: use generic cpu_model parsing David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 12/34] ppc: mac_newworld: " David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 13/34] ppc: mac_oldworld: " David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 14/34] ppc: bamboo: " David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 15/34] ppc: replace cpu_model with cpu_type on ref405ep, taihu boards David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 16/34] ppc: virtex-ml507: replace cpu_model with cpu_type David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 17/34] ppc: 40p/prep: " David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 18/34] ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model() David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 19/34] ppc: move '-cpu foo, compat=xxx' parsing into ppc_cpu_parse_featurestr() David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 20/34] ppc: spapr: define core types statically David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 21/34] ppc: spapr: use cpu type name directly David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 22/34] ppc: spapr: register 'host' core type along with the rest of core types David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 23/34] ppc: spapr: use cpu model names as tcg defaults instead of aliases David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 24/34] ppc: move ppc_cpu_lookup_alias() before its first user David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 25/34] ppc: spapr: use generic cpu_model parsing David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 26/34] ppc: pnv: " David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 27/34] ppc: pnv: normalize core/chip type names David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 28/34] ppc: pnv: drop PnvCoreClass::cpu_oc field David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 29/34] ppc: pnv: define core types statically David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 30/34] ppc: pnv: drop PnvChipClass::cpu_model field David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 31/34] ppc: pnv: consolidate type definitions and batch register them David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 32/34] spapr: Correct RAM size calculation for HPT resizing David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 33/34] spapr_pci: fail gracefully with non-pseries machine types David Gibson
2017-10-17 4:21 ` [Qemu-devel] [PULL 34/34] spapr_cpu_core: rewrite machine type sanity check David Gibson
2017-10-19 9:52 ` [Qemu-devel] [PULL 00/34] ppc-for-2.11 queue 20171017 Peter Maydell
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