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From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	"Andrew Jeffery" <andrew@aj.id.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH v6 1/8] aspeed: use a ROM memory region to catch invalid writes
Date: Thu, 19 Oct 2017 18:35:39 +0200	[thread overview]
Message-ID: <20171019163546.2039-2-clg@kaod.org> (raw)
In-Reply-To: <20171019163546.2039-1-clg@kaod.org>

Some legacy firmwares access unimplemented addresses on the Aspeed SoC
(old U-Boot code using variables in the bss when it shouldn't do).
Let's use a ROM memory region to catch the invalid writes and support
new boards without using the 'ignore_memory_transaction_failures'
flag.

This change is breaking migration compatibility for the Aspeed
machines.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---

 Changes since v5 :

 - added a comment on migration compatibility
 - created the ROM memory region even if there is no file backend
   specified by the user

 Changes since v4 :

 - use a ROM memory region

 hw/arm/aspeed.c | 51 ++++++++++++++++++++++++++++++++++++---------------
 1 file changed, 36 insertions(+), 15 deletions(-)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index ab895ad490af..e6a890659a97 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -166,12 +166,31 @@ static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
     }
 }
 
+/*
+ * This is to track invalid writes done in the ROM by some legacy
+ * firmwares
+ */
+static void boot_rom_write(void *opaque, hwaddr offset, uint64_t value,
+                           unsigned size)
+{
+    qemu_log_mask(LOG_GUEST_ERROR,
+                  "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
+                  __func__, offset, value, size);
+}
+
+static const MemoryRegionOps boot_rom_ops = {
+    .write = boot_rom_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
 static void aspeed_board_init(MachineState *machine,
                               const AspeedBoardConfig *cfg)
 {
     AspeedBoardState *bmc;
     AspeedSoCClass *sc;
     DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
+    MemoryRegion *boot_rom;
+    size_t boot_rom_size;
 
     bmc = g_new0(AspeedBoardState, 1);
     object_initialize(&bmc->soc, (sizeof(bmc->soc)), cfg->soc_name);
@@ -205,22 +224,24 @@ static void aspeed_board_init(MachineState *machine,
     aspeed_board_init_flashes(&bmc->soc.fmc, cfg->fmc_model, &error_abort);
     aspeed_board_init_flashes(&bmc->soc.spi[0], cfg->spi_model, &error_abort);
 
-    /* Install first FMC flash content as a boot rom. */
+    /*
+     * create a ROM region using the default mapping window size of
+     * the FMC CS0 flash module. The window size is 64MB for the
+     * AST2400 SoC and 128MB for the AST2500 SoC, which is twice as
+     * big as needed by the flash modules of the Aspeed machines.
+     */
+    boot_rom = g_new(MemoryRegion, 1);
+    boot_rom_size = bmc->soc.fmc.flashes[0].size;
+
+    memory_region_init_rom_device(boot_rom, OBJECT(bmc), &boot_rom_ops,
+                                  NULL, "aspeed.boot_rom", boot_rom_size,
+                                  &error_abort);
+    memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
+                                boot_rom);
+
+    /* Install first FMC flash content (if any) as a boot rom. */
     if (drive0) {
-        AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
-        MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
-
-        /*
-         * create a ROM region using the default mapping window size of
-         * the flash module. The window size is 64MB for the AST2400
-         * SoC and 128MB for the AST2500 SoC, which is twice as big as
-         * needed by the flash modules of the Aspeed machines.
-         */
-        memory_region_init_rom_nomigrate(boot_rom, OBJECT(bmc), "aspeed.boot_rom",
-                               fl->size, &error_abort);
-        memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
-                                    boot_rom);
-        write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
+        write_boot_rom(drive0, FIRMWARE_ADDR, boot_rom_size, &error_abort);
     }
 
     aspeed_board_binfo.kernel_filename = machine->kernel_filename;
-- 
2.13.6

  reply	other threads:[~2017-10-19 16:36 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-19 16:35 [Qemu-devel] [PATCH v6 0/8] aspeed: add a witherspoon-bmc machine Cédric Le Goater
2017-10-19 16:35 ` Cédric Le Goater [this message]
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 2/8] aspeed: remove ignore_memory_transaction_failures on all boards Cédric Le Goater
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 3/8] aspeed: add support for the witherspoon-bmc board Cédric Le Goater
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 4/8] aspeed: add an I2C RTC device to all machines Cédric Le Goater
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 5/8] smbus: add a smbus_eeprom_init_one() routine Cédric Le Goater
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 6/8] aspeed: Add EEPROM I2C devices Cédric Le Goater
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 7/8] misc: add pca9552 LED blinker model Cédric Le Goater
2017-10-20  2:58   ` Philippe Mathieu-Daudé
2017-10-20  6:11     ` Cédric Le Goater
2017-10-19 16:35 ` [Qemu-devel] [PATCH v6 8/8] aspeed: add the pc9552 chips to the witherspoon machine Cédric Le Goater
2017-10-20  2:59   ` Philippe Mathieu-Daudé
2017-10-20  6:15     ` Cédric Le Goater

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