From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: cota@braap.org, f4bug@amsat.org, pbonzini@redhat.com
Subject: [Qemu-devel] [PATCH v7 17/52] tcg: Introduce temp_tcgv_{i32, i64, ptr}
Date: Fri, 20 Oct 2017 16:19:48 -0700 [thread overview]
Message-ID: <20171020232023.15010-18-richard.henderson@linaro.org> (raw)
In-Reply-To: <20171020232023.15010-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 26 +++++++++++++++++-----
tcg/tcg.c | 74 +++++++++++++++++++++++++++------------------------------------
2 files changed, 53 insertions(+), 47 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index fb8ce01664..9432962d7b 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -786,6 +786,21 @@ static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr t)
return arg_temp(tcgv_ptr_arg(t));
}
+static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
+{
+ return (TCGv_i32)temp_idx(t);
+}
+
+static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
+{
+ return (TCGv_i64)temp_idx(t);
+}
+
+static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
+{
+ return (TCGv_ptr)temp_idx(t);
+}
+
static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
{
tcg_ctx.gen_op_buf[op_idx].args[arg] = v;
@@ -837,7 +852,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
-int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
+TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
+ intptr_t, const char *);
TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
@@ -851,8 +867,8 @@ void tcg_temp_free_i64(TCGv_i64 arg);
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
{
- int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
- return MAKE_TCGV_I32(idx);
+ TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
+ return temp_tcgv_i32(t);
}
static inline TCGv_i32 tcg_temp_new_i32(void)
@@ -868,8 +884,8 @@ static inline TCGv_i32 tcg_temp_local_new_i32(void)
static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
const char *name)
{
- int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
- return MAKE_TCGV_I64(idx);
+ TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
+ return temp_tcgv_i64(t);
}
static inline TCGv_i64 tcg_temp_new_i64(void)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index cb985aabdc..0a9bfa4236 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -492,8 +492,8 @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s)
return ts;
}
-static int tcg_global_reg_new_internal(TCGContext *s, TCGType type,
- TCGReg reg, const char *name)
+static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
+ TCGReg reg, const char *name)
{
TCGTemp *ts;
@@ -509,44 +509,43 @@ static int tcg_global_reg_new_internal(TCGContext *s, TCGType type,
ts->name = name;
tcg_regset_set_reg(s->reserved_regs, reg);
- return temp_idx(ts);
+ return ts;
}
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size)
{
- int idx;
s->frame_start = start;
s->frame_end = start + size;
- idx = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
- s->frame_temp = &s->temps[idx];
+ s->frame_temp
+ = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame");
}
TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name)
{
TCGContext *s = &tcg_ctx;
- int idx;
+ TCGTemp *t;
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
tcg_abort();
}
- idx = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
- return MAKE_TCGV_I32(idx);
+ t = tcg_global_reg_new_internal(s, TCG_TYPE_I32, reg, name);
+ return temp_tcgv_i32(t);
}
TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name)
{
TCGContext *s = &tcg_ctx;
- int idx;
+ TCGTemp *t;
if (tcg_regset_test_reg(s->reserved_regs, reg)) {
tcg_abort();
}
- idx = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
- return MAKE_TCGV_I64(idx);
+ t = tcg_global_reg_new_internal(s, TCG_TYPE_I64, reg, name);
+ return temp_tcgv_i64(t);
}
-int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
- intptr_t offset, const char *name)
+TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
+ intptr_t offset, const char *name)
{
TCGContext *s = &tcg_ctx;
TCGTemp *base_ts = &s->temps[GET_TCGV_PTR(base)];
@@ -598,10 +597,10 @@ int tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
ts->mem_offset = offset;
ts->name = name;
}
- return temp_idx(ts);
+ return ts;
}
-static int tcg_temp_new_internal(TCGType type, int temp_local)
+static TCGTemp *tcg_temp_new_internal(TCGType type, int temp_local)
{
TCGContext *s = &tcg_ctx;
TCGTemp *ts;
@@ -638,36 +637,30 @@ static int tcg_temp_new_internal(TCGType type, int temp_local)
ts->temp_allocated = 1;
ts->temp_local = temp_local;
}
- idx = temp_idx(ts);
}
#if defined(CONFIG_DEBUG_TCG)
s->temps_in_use++;
#endif
- return idx;
+ return ts;
}
TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
{
- int idx;
-
- idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
- return MAKE_TCGV_I32(idx);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
+ return temp_tcgv_i32(t);
}
TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
{
- int idx;
-
- idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
- return MAKE_TCGV_I64(idx);
+ TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
+ return temp_tcgv_i64(t);
}
-static void tcg_temp_free_internal(int idx)
+static void tcg_temp_free_internal(TCGTemp *ts)
{
TCGContext *s = &tcg_ctx;
- TCGTemp *ts;
- int k;
+ int k, idx;
#if defined(CONFIG_DEBUG_TCG)
s->temps_in_use--;
@@ -676,23 +669,23 @@ static void tcg_temp_free_internal(int idx)
}
#endif
- tcg_debug_assert(idx >= s->nb_globals && idx < s->nb_temps);
- ts = &s->temps[idx];
+ tcg_debug_assert(ts->temp_global == 0);
tcg_debug_assert(ts->temp_allocated != 0);
ts->temp_allocated = 0;
+ idx = temp_idx(ts);
k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
set_bit(idx, s->free_temps[k].l);
}
void tcg_temp_free_i32(TCGv_i32 arg)
{
- tcg_temp_free_internal(GET_TCGV_I32(arg));
+ tcg_temp_free_internal(tcgv_i32_temp(arg));
}
void tcg_temp_free_i64(TCGv_i64 arg)
{
- tcg_temp_free_internal(GET_TCGV_I64(arg));
+ tcg_temp_free_internal(tcgv_i64_temp(arg));
}
TCGv_i32 tcg_const_i32(int32_t val)
@@ -1001,7 +994,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = real_args = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (is_64bit) {
- TCGv_i64 orig = MAKE_TCGV_I64(temp_idx(args[i]));
+ TCGv_i64 orig = temp_tcgv_i64(args[i]);
TCGv_i32 h = tcg_temp_new_i32();
TCGv_i32 l = tcg_temp_new_i32();
tcg_gen_extr_i64_i32(l, h, orig);
@@ -1021,7 +1014,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
int is_signed = sizemask & (2 << (i+1)*2);
if (!is_64bit) {
TCGv_i64 temp = tcg_temp_new_i64();
- TCGv_i64 orig = MAKE_TCGV_I64(temp_idx(args[i]));
+ TCGv_i64 orig = temp_tcgv_i64(args[i]);
if (is_signed) {
tcg_gen_ext32s_i64(temp, orig);
} else {
@@ -1130,10 +1123,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = real_args = 0; i < orig_nargs; ++i) {
int is_64bit = orig_sizemask & (1 << (i+1)*2);
if (is_64bit) {
- TCGv_i32 h = MAKE_TCGV_I32(temp_idx(args[real_args++]));
- TCGv_i32 l = MAKE_TCGV_I32(temp_idx(args[real_args++]));
- tcg_temp_free_i32(h);
- tcg_temp_free_i32(l);
+ tcg_temp_free_internal(args[real_args++]);
+ tcg_temp_free_internal(args[real_args++]);
} else {
real_args++;
}
@@ -1142,7 +1133,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
/* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
Note that describing these as TCGv_i64 eliminates an unnecessary
zero-extension that tcg_gen_concat_i32_i64 would create. */
- tcg_gen_concat32_i64(MAKE_TCGV_I64(temp_idx(ret)), retl, reth);
+ tcg_gen_concat32_i64(temp_tcgv_i64(ret), retl, reth);
tcg_temp_free_i64(retl);
tcg_temp_free_i64(reth);
}
@@ -1150,8 +1141,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
for (i = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
if (!is_64bit) {
- TCGv_i64 temp = MAKE_TCGV_I64(temp_idx(args[i]));
- tcg_temp_free_i64(temp);
+ tcg_temp_free_internal(args[i]);
}
}
#endif /* TCG_TARGET_EXTEND_ARGS */
--
2.13.6
next prev parent reply other threads:[~2017-10-20 23:20 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-20 23:19 [Qemu-devel] [PATCH v7 00/52] tcg queued patches Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 01/52] tcg: Merge opcode arguments into TCGOp Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 02/52] tcg: Propagate args to op->args in optimizer Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 03/52] tcg: Propagate args to op->args in tcg.c Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 04/52] tcg: Propagate TCGOp down to allocators Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 05/52] tcg: Introduce arg_temp Richard Henderson
2017-10-24 2:45 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 06/52] tcg: Add temp_global bit to TCGTemp Richard Henderson
2017-10-24 2:49 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 07/52] tcg: Return NULL temp for TCG_CALL_DUMMY_ARG Richard Henderson
2017-10-24 3:09 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 08/52] tcg: Introduce temp_arg, export temp_idx Richard Henderson
2017-10-23 17:09 ` Emilio G. Cota
2017-10-24 2:47 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 09/52] tcg: Use per-temp state data in liveness Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 10/52] tcg: Avoid loops against variable bounds Richard Henderson
2017-10-24 2:51 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 11/52] tcg: Change temp_allocate_frame arg to TCGTemp Richard Henderson
2017-10-24 2:52 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 12/52] tcg: Remove unused TCG_CALL_DUMMY_TCGV Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 13/52] tcg: Use per-temp state data in optimize Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 14/52] tcg: Push tcg_ctx into generator functions Richard Henderson
2017-10-24 2:56 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 15/52] tcg: Push tcg_ctx into tcg_gen_callN Richard Henderson
2017-10-24 2:57 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 16/52] tcg: Introduce tcgv_{i32, i64, ptr}_{arg, temp} Richard Henderson
2017-10-23 17:10 ` Emilio G. Cota
2017-10-24 3:02 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` Richard Henderson [this message]
2017-10-23 17:10 ` [Qemu-devel] [PATCH v7 17/52] tcg: Introduce temp_tcgv_{i32, i64, ptr} Emilio G. Cota
2017-10-24 3:05 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 18/52] tcg: Remove GET_TCGV_* and MAKE_TCGV_* Richard Henderson
2017-10-23 17:12 ` Emilio G. Cota
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 19/52] tcg: Remove TCGV_EQUAL* Richard Henderson
2017-10-23 17:13 ` Emilio G. Cota
2017-10-24 3:11 ` Philippe Mathieu-Daudé
2017-10-24 19:56 ` Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 20/52] qom: Introduce CPUClass.tcg_initialize Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 21/52] tcg: Use offsets not indices for TCGv_* Richard Henderson
2017-10-23 17:37 ` Emilio G. Cota
2017-10-24 3:23 ` Philippe Mathieu-Daudé
2017-10-24 3:22 ` Philippe Mathieu-Daudé
2017-10-24 3:30 ` Philippe Mathieu-Daudé
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 22/52] tcg: Use pointers in TCGOp->args Richard Henderson
2017-10-23 17:37 ` Emilio G. Cota
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 23/52] tcg: define CF_PARALLEL and use it for TB hashing along with CF_COUNT_MASK Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 24/52] tcg: Add CPUState cflags_next_tb Richard Henderson
2017-10-23 17:53 ` Emilio G. Cota
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 25/52] tcg: Include CF_COUNT_MASK in CF_HASH_MASK Richard Henderson
2017-10-23 17:53 ` Emilio G. Cota
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 26/52] tcg: convert tb->cflags reads to tb_cflags(tb) Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 27/52] target/arm: check CF_PARALLEL instead of parallel_cpus Richard Henderson
2017-10-20 23:19 ` [Qemu-devel] [PATCH v7 28/52] target/hppa: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 29/52] target/i386: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 30/52] target/m68k: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 31/52] target/s390x: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 32/52] target/sh4: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 33/52] target/sparc: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 34/52] tcg: " Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 35/52] cpu-exec: lookup/generate TB outside exclusive region during step_atomic Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 36/52] tcg: Add CF_LAST_IO + CF_USE_ICOUNT to CF_HASH_MASK Richard Henderson
2017-10-23 17:57 ` Emilio G. Cota
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 37/52] tcg: Remove CF_IGNORE_ICOUNT Richard Henderson
2017-10-23 18:06 ` Emilio G. Cota
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 38/52] translate-all: use a binary search tree to track TBs in TBContext Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 39/52] exec-all: rename tb_free to tb_remove Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 40/52] translate-all: report correct avg host TB size Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 41/52] tcg: take tb_ctx out of TCGContext Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 42/52] tcg: define tcg_init_ctx and make tcg_ctx a pointer Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 43/52] gen-icount: fold exitreq_label into TCGContext Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 44/52] tcg: introduce **tcg_ctxs to keep track of all TCGContext's Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 45/52] tcg: distribute profiling counters across TCGContext's Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 46/52] tcg: allocate optimizer temps with tcg_malloc Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 47/52] osdep: introduce qemu_mprotect_rwx/none Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 48/52] translate-all: use qemu_protect_rwx/none helpers Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 49/52] tcg: introduce regions to split code_gen_buffer Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 50/52] tcg: enable multiple TCG contexts in softmmu Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 51/52] tcg: Initialize cpu_env generically Richard Henderson
2017-10-20 23:20 ` [Qemu-devel] [PATCH v7 52/52] translate-all: exit from tb_phys_invalidate if qht_remove fails Richard Henderson
2017-10-21 0:24 ` [Qemu-devel] [PATCH v7 00/52] tcg queued patches no-reply
2017-10-21 18:43 ` Richard Henderson
2017-10-21 0:44 ` no-reply
2017-10-23 18:14 ` Emilio G. Cota
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