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From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>,
	Greg Kurz <groug@kaod.org>,
	Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: "Cédric Le Goater" <clg@kaod.org>
Subject: [Qemu-devel] [PATCH 3/8] pnv: introduce an irq_test() operation
Date: Sun, 29 Oct 2017 19:12:12 +0100	[thread overview]
Message-ID: <20171029181217.9927-4-clg@kaod.org> (raw)
In-Reply-To: <20171029181217.9927-1-clg@kaod.org>

On PowerNV, there is no need for a bitmap for the moment. The only
interrupts handled are the ones from the PSI controller.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/pnv.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c35c439d816b..8288940ef9d7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1018,6 +1018,23 @@ static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
     return cpu ? ICP(cpu->intc) : NULL;
 }
 
+static bool pnv_irq_test(XICSFabric *xi, int irq)
+{
+    PnvMachineState *pnv = POWERNV_MACHINE(xi);
+    int i;
+
+    /* We don't have a IRQ allocator for the PowerNV machine yet, so
+     * just check that the IRQ number is valid for the PSI source
+     */
+    for (i = 0; i < pnv->num_chips; i++) {
+        ICSState *ics = &pnv->chips[i]->psi.ics;
+        if (ics_valid_irq(ics, irq)) {
+            return true;
+        }
+    }
+    return false;
+}
+
 static void pnv_pic_print_info(InterruptStatsProvider *obj,
                                Monitor *mon)
 {
@@ -1102,6 +1119,7 @@ static void powernv_machine_class_init(ObjectClass *oc, void *data)
     xic->icp_get = pnv_icp_get;
     xic->ics_get = pnv_ics_get;
     xic->ics_resend = pnv_ics_resend;
+    xic->irq_test = pnv_irq_test;
     ispc->print_info = pnv_pic_print_info;
 
     powernv_machine_class_props_init(oc);
-- 
2.13.6

  parent reply	other threads:[~2017-10-29 18:12 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-29 18:12 [Qemu-devel] [PATCH 0/8] introduce an IRQ allocator at the machine level Cédric Le Goater
2017-10-29 18:12 ` [Qemu-devel] [PATCH 1/8] spapr: " Cédric Le Goater
2017-11-08  9:54   ` Greg Kurz
2017-11-08 16:56     ` Cédric Le Goater
2017-10-29 18:12 ` [Qemu-devel] [PATCH 2/8] spapr: introduce a machine class flag to handle migration compatibility Cédric Le Goater
2017-11-08 13:21   ` Greg Kurz
2017-11-08 16:53     ` Cédric Le Goater
2017-10-29 18:12 ` Cédric Le Goater [this message]
2017-10-29 18:12 ` [Qemu-devel] [PATCH 4/8] spapr: split the IRQ number space for LSI interrupts Cédric Le Goater
2017-10-29 18:12 ` [Qemu-devel] [PATCH 5/8] spapr: introduce an is_lsi() operation Cédric Le Goater
2017-10-29 18:12 ` [Qemu-devel] [PATCH 6/8] sparp: merge ics_set_irq_type() in irq_alloc_block() operation Cédric Le Goater
2017-10-29 18:12 ` [Qemu-devel] [PATCH 7/8] spapr: move spapr_ics_free() under irq_free_block() operation Cédric Le Goater
2017-10-29 18:12 ` [Qemu-devel] [PATCH 8/8] spapr: use sPAPRMachineState in spapr_ics_* prototypes Cédric Le Goater

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