From: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
To: qemu-devel@nongnu.org, qemu-block@nongnu.org,
qemu-arm@nongnu.org, qemu-ppc@nongnu.org
Cc: kwolf@redhat.com, mreitz@redhat.com, jan.kiszka@web.de,
edgar.iglesias@gmail.com, alistair.francis@xilinx.com,
michael@walle.cc, david@gibson.dropbear.id.au,
magnus.damm@gmail.com,
Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
Subject: [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving
Date: Tue, 31 Oct 2017 11:44:05 -0400 [thread overview]
Message-ID: <20171031154407.4184-1-michael.nawrocki@gtri.gatech.edu> (raw)
This patch set does a few things. First, it switches the AMD CFI flash MMIO
operations from the old MMIO API to the new one. Second, it enables 8-byte
wide flash arrays. Finally, it supports rudimentary interleaving of notional
flash "chips". It is expected that commands will be sent to all "chips"
simultaneously. See the example in the second patch for more details. This
behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
Mike Nawrocki (2):
Add 8-byte access to AMD CFI devices
Add support for flash interleaving of AMD chips
hw/arm/digic_boards.c | 2 +-
hw/arm/musicpal.c | 4 +-
hw/arm/xilinx_zynq.c | 2 +-
hw/block/pflash_cfi02.c | 210 ++++++++++++++++++++++++++---------------------
hw/lm32/lm32_boards.c | 4 +-
hw/ppc/ppc405_boards.c | 15 ++--
hw/sh4/r2d.c | 2 +-
include/hw/block/flash.h | 1 +
8 files changed, 132 insertions(+), 108 deletions(-)
--
2.14.2
next reply other threads:[~2017-10-31 15:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-31 15:44 Mike Nawrocki [this message]
2017-10-31 15:44 ` [Qemu-devel] [PATCH 1/2] Add 8-byte access to AMD CFI devices Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 2/2] Add support for flash interleaving of AMD chips Mike Nawrocki
2017-10-31 17:00 ` [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Peter Maydell
2017-11-01 15:01 ` Nawrocki, Michael
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