* [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving
@ 2017-10-31 15:44 Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 1/2] Add 8-byte access to AMD CFI devices Mike Nawrocki
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Mike Nawrocki @ 2017-10-31 15:44 UTC (permalink / raw)
To: qemu-devel, qemu-block, qemu-arm, qemu-ppc
Cc: kwolf, mreitz, jan.kiszka, edgar.iglesias, alistair.francis,
michael, david, magnus.damm, Mike Nawrocki
This patch set does a few things. First, it switches the AMD CFI flash MMIO
operations from the old MMIO API to the new one. Second, it enables 8-byte
wide flash arrays. Finally, it supports rudimentary interleaving of notional
flash "chips". It is expected that commands will be sent to all "chips"
simultaneously. See the example in the second patch for more details. This
behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
Mike Nawrocki (2):
Add 8-byte access to AMD CFI devices
Add support for flash interleaving of AMD chips
hw/arm/digic_boards.c | 2 +-
hw/arm/musicpal.c | 4 +-
hw/arm/xilinx_zynq.c | 2 +-
hw/block/pflash_cfi02.c | 210 ++++++++++++++++++++++++++---------------------
hw/lm32/lm32_boards.c | 4 +-
hw/ppc/ppc405_boards.c | 15 ++--
hw/sh4/r2d.c | 2 +-
include/hw/block/flash.h | 1 +
8 files changed, 132 insertions(+), 108 deletions(-)
--
2.14.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH 1/2] Add 8-byte access to AMD CFI devices
2017-10-31 15:44 [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Mike Nawrocki
@ 2017-10-31 15:44 ` Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 2/2] Add support for flash interleaving of AMD chips Mike Nawrocki
2017-10-31 17:00 ` [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Peter Maydell
2 siblings, 0 replies; 5+ messages in thread
From: Mike Nawrocki @ 2017-10-31 15:44 UTC (permalink / raw)
To: qemu-devel, qemu-block, qemu-arm, qemu-ppc
Cc: kwolf, mreitz, jan.kiszka, edgar.iglesias, alistair.francis,
michael, david, magnus.damm, Mike Nawrocki
This adds 8-byte wide access support to AMD CFI flash devices.
Additionally, it migrates the MMIO operations from old_mmio to the new
API.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
---
hw/block/pflash_cfi02.c | 172 +++++++++++++++++++++++-------------------------
1 file changed, 81 insertions(+), 91 deletions(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index c81ddd3a99..0aed0ab218 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -18,7 +18,7 @@
*/
/*
- * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
+ * For now, this code can emulate flashes of 1, 2, 4, or 8 bytes width.
* Supported commands/modes are:
* - flash read
* - flash write
@@ -138,11 +138,11 @@ static void pflash_timer (void *opaque)
pfl->cmd = 0;
}
-static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
- int width, int be)
+static uint64_t pflash_read(pflash_t *pfl, hwaddr offset,
+ int width, int be)
{
hwaddr boff;
- uint32_t ret;
+ uint64_t ret;
uint8_t *p;
DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
@@ -158,6 +158,8 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
boff = boff >> 1;
else if (pfl->width == 4)
boff = boff >> 2;
+ else if (pfl->width == 8)
+ boff = boff >> 3;
switch (pfl->cmd) {
default:
/* This should never happen : reset state & treat it as a read*/
@@ -200,6 +202,27 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
}
// DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
break;
+ case 8:
+ if (be) {
+ ret = (uint64_t)p[offset] << 56;
+ ret |= (uint64_t)p[offset + 1] << 48;
+ ret |= (uint64_t)p[offset + 2] << 40;
+ ret |= (uint64_t)p[offset + 3] << 32;
+ ret |= (uint64_t)p[offset + 4] << 24;
+ ret |= (uint64_t)p[offset + 5] << 16;
+ ret |= (uint64_t)p[offset + 6] << 8;
+ ret |= (uint64_t)p[offset + 7];
+ } else {
+ ret = (uint64_t)p[offset];
+ ret |= (uint64_t)p[offset + 1] << 8;
+ ret |= (uint64_t)p[offset + 2] << 16;
+ ret |= (uint64_t)p[offset + 3] << 24;
+ ret |= (uint64_t)p[offset + 4] << 32;
+ ret |= (uint64_t)p[offset + 5] << 40;
+ ret |= (uint64_t)p[offset + 6] << 48;
+ ret |= (uint64_t)p[offset + 7] << 56;
+ }
+ break;
}
break;
case 0x90:
@@ -222,14 +245,15 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
default:
goto flash_read;
}
- DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
+ DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__,
+ boff, ret);
break;
case 0xA0:
case 0x10:
case 0x30:
/* Status register read */
ret = pfl->status;
- DPRINTF("%s: status %x\n", __func__, ret);
+ DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
/* Toggle bit 6 */
pfl->status ^= 0x40;
break;
@@ -246,8 +270,7 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
}
/* update flash content on disk */
-static void pflash_update(pflash_t *pfl, int offset,
- int size)
+static void pflash_update(pflash_t *pfl, int offset, int size)
{
int offset_end;
if (pfl->blk) {
@@ -260,8 +283,8 @@ static void pflash_update(pflash_t *pfl, int offset,
}
}
-static void pflash_write (pflash_t *pfl, hwaddr offset,
- uint32_t value, int width, int be)
+static void pflash_write(pflash_t *pfl, hwaddr offset,
+ uint64_t value, int width, int be)
{
hwaddr boff;
uint8_t *p;
@@ -275,17 +298,19 @@ static void pflash_write (pflash_t *pfl, hwaddr offset,
#endif
goto reset_flash;
}
- DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,
- offset, value, width, pfl->wcycle);
+ DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d %d\n",
+ __func__, offset, value, width, pfl->wcycle);
offset &= pfl->chip_len - 1;
- DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
- offset, value, width);
+ DPRINTF("%s: offset " TARGET_FMT_plx " %08" PRIx64 " %d\n",
+ __func__, offset, value, width);
boff = offset & (pfl->sector_len - 1);
if (pfl->width == 2)
boff = boff >> 1;
else if (pfl->width == 4)
boff = boff >> 2;
+ else if (pfl->width == 8)
+ boff = boff >> 3;
switch (pfl->wcycle) {
case 0:
/* Set the device in I/O access mode if required */
@@ -346,8 +371,8 @@ static void pflash_write (pflash_t *pfl, hwaddr offset,
/* We need another unlock sequence */
goto check_unlock0;
case 0xA0:
- DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",
- __func__, offset, value, width);
+ DPRINTF("%s: write data offset " TARGET_FMT_plx
+ " %08" PRIx64 " %d\n", __func__, offset, value, width);
p = pfl->storage;
if (!pfl->ro) {
switch (width) {
@@ -379,6 +404,28 @@ static void pflash_write (pflash_t *pfl, hwaddr offset,
}
pflash_update(pfl, offset, 4);
break;
+ case 8:
+ if (be) {
+ p[offset] &= value >> 56;
+ p[offset + 1] &= value >> 48;
+ p[offset + 2] &= value >> 40;
+ p[offset + 3] &= value >> 32;
+ p[offset + 4] &= value >> 24;
+ p[offset + 5] &= value >> 16;
+ p[offset + 6] &= value >> 8;
+ p[offset + 7] &= value;
+ } else {
+ p[offset] &= value;
+ p[offset + 1] &= value >> 8;
+ p[offset + 2] &= value >> 16;
+ p[offset + 3] &= value >> 24;
+ p[offset + 4] &= value >> 32;
+ p[offset + 5] &= value >> 40;
+ p[offset + 6] &= value >> 48;
+ p[offset + 7] &= value >> 56;
+ }
+ pflash_update(pfl, offset, 8);
+ break;
}
}
pfl->status = 0x00 | ~(value & 0x80);
@@ -494,103 +541,46 @@ static void pflash_write (pflash_t *pfl, hwaddr offset,
pfl->cmd = 0;
}
-
-static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
-{
- return pflash_read(opaque, addr, 1, 1);
-}
-
-static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
-{
- return pflash_read(opaque, addr, 1, 0);
-}
-
-static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
+static uint64_t pflash_read_le(void *opaque, hwaddr addr, unsigned size)
{
pflash_t *pfl = opaque;
-
- return pflash_read(pfl, addr, 2, 1);
+ return pflash_read(pfl, addr, size, 0);
}
-static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
+static uint64_t pflash_read_be(void *opaque, hwaddr addr, unsigned size)
{
pflash_t *pfl = opaque;
-
- return pflash_read(pfl, addr, 2, 0);
+ return pflash_read(pfl, addr, size, 1);
}
-static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
+static void pflash_write_le(void *opaque, hwaddr addr, uint64_t data,
+ unsigned size)
{
pflash_t *pfl = opaque;
-
- return pflash_read(pfl, addr, 4, 1);
+ pflash_write(pfl, addr, data, size, 0);
}
-static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
+static void pflash_write_be(void *opaque, hwaddr addr, uint64_t data,
+ unsigned size)
{
pflash_t *pfl = opaque;
-
- return pflash_read(pfl, addr, 4, 0);
-}
-
-static void pflash_writeb_be(void *opaque, hwaddr addr,
- uint32_t value)
-{
- pflash_write(opaque, addr, value, 1, 1);
-}
-
-static void pflash_writeb_le(void *opaque, hwaddr addr,
- uint32_t value)
-{
- pflash_write(opaque, addr, value, 1, 0);
-}
-
-static void pflash_writew_be(void *opaque, hwaddr addr,
- uint32_t value)
-{
- pflash_t *pfl = opaque;
-
- pflash_write(pfl, addr, value, 2, 1);
-}
-
-static void pflash_writew_le(void *opaque, hwaddr addr,
- uint32_t value)
-{
- pflash_t *pfl = opaque;
-
- pflash_write(pfl, addr, value, 2, 0);
-}
-
-static void pflash_writel_be(void *opaque, hwaddr addr,
- uint32_t value)
-{
- pflash_t *pfl = opaque;
-
- pflash_write(pfl, addr, value, 4, 1);
-}
-
-static void pflash_writel_le(void *opaque, hwaddr addr,
- uint32_t value)
-{
- pflash_t *pfl = opaque;
-
- pflash_write(pfl, addr, value, 4, 0);
+ pflash_write(pfl, addr, data, size, 1);
}
static const MemoryRegionOps pflash_cfi02_ops_be = {
- .old_mmio = {
- .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
- .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
- },
+ .read = pflash_read_be,
+ .write = pflash_write_be,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.max_access_size = 8,
+ .impl.max_access_size = 8,
};
static const MemoryRegionOps pflash_cfi02_ops_le = {
- .old_mmio = {
- .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
- .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
- },
+ .read = pflash_read_le,
+ .write = pflash_write_le,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.max_access_size = 8,
+ .impl.max_access_size = 8,
};
static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
--
2.14.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [Qemu-devel] [PATCH 2/2] Add support for flash interleaving of AMD chips
2017-10-31 15:44 [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 1/2] Add 8-byte access to AMD CFI devices Mike Nawrocki
@ 2017-10-31 15:44 ` Mike Nawrocki
2017-10-31 17:00 ` [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Peter Maydell
2 siblings, 0 replies; 5+ messages in thread
From: Mike Nawrocki @ 2017-10-31 15:44 UTC (permalink / raw)
To: qemu-devel, qemu-block, qemu-arm, qemu-ppc
Cc: kwolf, mreitz, jan.kiszka, edgar.iglesias, alistair.francis,
michael, david, magnus.damm, Mike Nawrocki
Flash interleaving is partially supported using the new interleave_num
parameter, which indicates how many "devices" comprise the flash array.
The supported flash access pattern is one where commands are sent to all
devices simultaneously and the read result is duplicated according to
the interleave number. For example, given a flash array of width 8,
interleave 4, the command sequence
0x00AA00AA00AA00AA
0x0055005500550055
0x0090009000900090
sends the auto-select command sequence. If a read to address 0 is
issued, the user would expect the following: 0x0001000100010001 to
identify the AMD device array.
Issuing commands to individual members of the flash array is not
supported.
Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
---
hw/arm/digic_boards.c | 2 +-
hw/arm/musicpal.c | 4 ++--
hw/arm/xilinx_zynq.c | 2 +-
hw/block/pflash_cfi02.c | 38 +++++++++++++++++++++++++++++++++++++-
hw/lm32/lm32_boards.c | 4 ++--
hw/ppc/ppc405_boards.c | 15 ++++++---------
hw/sh4/r2d.c | 2 +-
include/hw/block/flash.h | 1 +
8 files changed, 51 insertions(+), 17 deletions(-)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 9f11dcd11f..7f039a989a 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -133,7 +133,7 @@ static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr,
NULL, FLASH_K8P3215UQB_SECTOR_SIZE,
FLASH_K8P3215UQB_SIZE / FLASH_K8P3215UQB_SECTOR_SIZE,
DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE,
- 4,
+ 4, 1,
0x00EC, 0x007E, 0x0003, 0x0001,
0x0555, 0x2aa, 0);
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index b648770882..5d98cd1eac 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -1640,14 +1640,14 @@ static void musicpal_init(MachineState *machine)
"musicpal.flash", flash_size,
blk, 0x10000, (flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size,
- 2, 0x00BF, 0x236D, 0x0000, 0x0000,
+ 2, 1, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 1);
#else
pflash_cfi02_register(0x100000000ULL-MP_FLASH_SIZE_MAX, NULL,
"musicpal.flash", flash_size,
blk, 0x10000, (flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size,
- 2, 0x00BF, 0x236D, 0x0000, 0x0000,
+ 2, 1, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 0);
#endif
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 1836a4ed45..ea85333104 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -210,7 +210,7 @@ static void zynq_init(MachineState *machine)
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
FLASH_SECTOR_SIZE,
FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
- 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
+ 1, 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
0);
dev = qdev_create(NULL, "xilinx,zynq_slcr");
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index 0aed0ab218..b0f86584c5 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -28,11 +28,28 @@
* - unlock bypass command
* - CFI queries
*
- * It does not support flash interleaving.
* It does not implement boot blocs with reduced size
* It does not implement software data protection as found in many real chips
* It does not implement erase suspend/resume commands
* It does not implement multiple sectors erase
+ *
+ * Flash interleaving is partially supported using the interleave_num
+ * parameter, which indicates how many "devices" comprise the flash array.
+ * The supported flash access pattern is one where commands are sent to all
+ * devices simultaneously and the read result is duplicated according to the
+ * interleave number. For example, given a flash array of width 8,
+ * interleave 4, the command sequence
+ *
+ * 0x00AA00AA00AA00AA
+ * 0x0055005500550055
+ * 0x0090009000900090
+ *
+ * sends the auto-select command sequence. If a read to address 0 is
+ * issued, the user would expect the following:
+ * 0x0001000100010001
+ * to identify the AMD device array.
+ *
+ * Issuing commands to individual members of the flash array is not supported.
*/
#include "qemu/osdep.h"
@@ -97,6 +114,7 @@ struct pflash_t {
int read_counter; /* used for lazy switch-back to rom mode */
char *name;
void *storage;
+ uint8_t interleave_num; /* number of devices that comprise the array */
};
/*
@@ -144,6 +162,8 @@ static uint64_t pflash_read(pflash_t *pfl, hwaddr offset,
hwaddr boff;
uint64_t ret;
uint8_t *p;
+ int i;
+ uint8_t intlv_shift = (pfl->width / pfl->interleave_num) << 3;
DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
ret = -1;
@@ -231,6 +251,10 @@ static uint64_t pflash_read(pflash_t *pfl, hwaddr offset,
case 0x00:
case 0x01:
ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
+ for (i = 1; i < pfl->interleave_num; ++i) {
+ ret = (ret << intlv_shift) | ret;
+ }
+
break;
case 0x02:
ret = 0x00; /* Pretend all sectors are unprotected */
@@ -241,6 +265,9 @@ static uint64_t pflash_read(pflash_t *pfl, hwaddr offset,
if (ret == (uint8_t)-1) {
goto flash_read;
}
+ for (i = 1; i < pfl->interleave_num; ++i) {
+ ret <<= intlv_shift;
+ }
break;
default:
goto flash_read;
@@ -253,6 +280,9 @@ static uint64_t pflash_read(pflash_t *pfl, hwaddr offset,
case 0x30:
/* Status register read */
ret = pfl->status;
+ for (i = 1; i < pfl->interleave_num; ++i) {
+ ret <<= intlv_shift;
+ }
DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
/* Toggle bit 6 */
pfl->status ^= 0x40;
@@ -263,6 +293,9 @@ static uint64_t pflash_read(pflash_t *pfl, hwaddr offset,
ret = 0;
else
ret = pfl->cfi_table[boff];
+ for (i = 1; i < pfl->interleave_num; ++i) {
+ ret <<= intlv_shift;
+ }
break;
}
@@ -745,6 +778,7 @@ static Property pflash_cfi02_properties[] = {
DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0),
DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0),
DEFINE_PROP_STRING("name", struct pflash_t, name),
+ DEFINE_PROP_UINT8("interleave_num", struct pflash_t, interleave_num, 1),
DEFINE_PROP_END_OF_LIST(),
};
@@ -776,6 +810,7 @@ pflash_t *pflash_cfi02_register(hwaddr base,
hwaddr size,
BlockBackend *blk, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
+ int interleave_num,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1,
@@ -798,6 +833,7 @@ pflash_t *pflash_cfi02_register(hwaddr base,
qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
qdev_prop_set_string(dev, "name", name);
+ qdev_prop_set_uint32(dev, "interleave_num", MAX(interleave_num, 1));
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c
index 002d638edd..523121142f 100644
--- a/hw/lm32/lm32_boards.c
+++ b/hw/lm32/lm32_boards.c
@@ -116,7 +116,7 @@ static void lm32_evr_init(MachineState *machine)
pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
flash_sector_size, flash_size / flash_sector_size,
- 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
+ 1, 2, 1, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
/* create irq lines */
env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
@@ -209,7 +209,7 @@ static void lm32_uclinux_init(MachineState *machine)
pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
flash_sector_size, flash_size / flash_sector_size,
- 1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
+ 1, 2, 1, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
/* create irq lines */
env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index e92db2c66a..04d318ca65 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -241,9 +241,8 @@ static void ref405ep_init(MachineState *machine)
#endif
pflash_cfi02_register((uint32_t)(-bios_size),
NULL, "ef405ep.bios", bios_size,
- blk, 65536, fl_sectors, 1,
- 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ blk, 65536, fl_sectors, 1, 2, 1,
+ 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1);
fl_idx++;
} else
#endif
@@ -539,9 +538,8 @@ static void taihu_405ep_init(MachineState *machine)
#endif
pflash_cfi02_register((uint32_t)(-bios_size),
NULL, "taihu_405ep.bios", bios_size,
- blk, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ blk, 65536, fl_sectors, 1, 4, 1,
+ 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1);
fl_idx++;
} else
#endif
@@ -586,9 +584,8 @@ static void taihu_405ep_init(MachineState *machine)
blk_name(blk));
#endif
pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
- blk, 65536, fl_sectors, 1,
- 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
- 1);
+ blk, 65536, fl_sectors, 1, 4, 1,
+ 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 1);
fl_idx++;
}
/* Register CLPD & LCD display */
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c
index 458ed83297..696175dad6 100644
--- a/hw/sh4/r2d.c
+++ b/hw/sh4/r2d.c
@@ -293,7 +293,7 @@ static void r2d_init(MachineState *machine)
pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(16 * 1024), FLASH_SIZE >> 16,
- 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
+ 1, 4, 1, 0x0000, 0x0000, 0x0000, 0x0000,
0x555, 0x2aa, 0);
/* NIC: rtl8139 on-board, and 2 slots. */
diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
index 67c3aa329e..b23e3e3030 100644
--- a/include/hw/block/flash.h
+++ b/include/hw/block/flash.h
@@ -25,6 +25,7 @@ pflash_t *pflash_cfi02_register(hwaddr base,
hwaddr size,
BlockBackend *blk, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
+ int interleave_num,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1,
--
2.14.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving
2017-10-31 15:44 [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 1/2] Add 8-byte access to AMD CFI devices Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 2/2] Add support for flash interleaving of AMD chips Mike Nawrocki
@ 2017-10-31 17:00 ` Peter Maydell
2017-11-01 15:01 ` Nawrocki, Michael
2 siblings, 1 reply; 5+ messages in thread
From: Peter Maydell @ 2017-10-31 17:00 UTC (permalink / raw)
To: Mike Nawrocki
Cc: QEMU Developers, Qemu-block, qemu-arm, qemu-ppc@nongnu.org,
Kevin Wolf, Magnus Damm, Alistair Francis, Michael Walle,
Jan Kiszka, Edgar E. Iglesias, Max Reitz, David Gibson
On 31 October 2017 at 15:44, Mike Nawrocki
<michael.nawrocki@gtri.gatech.edu> wrote:
> This patch set does a few things. First, it switches the AMD CFI flash MMIO
> operations from the old MMIO API to the new one. Second, it enables 8-byte
> wide flash arrays. Finally, it supports rudimentary interleaving of notional
> flash "chips". It is expected that commands will be sent to all "chips"
> simultaneously. See the example in the second patch for more details. This
> behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
I'm confused by the interleaving part. Can you explain how this
differs from the interleaving we already support in pflash_cfi01.c
via setting width, device-width and max-device-width ? (see the comment
in the pflash_cfi01_properties[] array about how those settings
interact). If it is the same thing, we should really implement it
in the same way for both kinds of flash device.
thanks
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving
2017-10-31 17:00 ` [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Peter Maydell
@ 2017-11-01 15:01 ` Nawrocki, Michael
0 siblings, 0 replies; 5+ messages in thread
From: Nawrocki, Michael @ 2017-11-01 15:01 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, Qemu-block, qemu-arm, qemu-ppc@nongnu.org,
Kevin Wolf, Magnus Damm, Alistair Francis, Michael Walle,
Jan Kiszka, Edgar E. Iglesias, Max Reitz, David Gibson
On 10/31/17, 13:00, "Peter Maydell" <peter.maydell@linaro.org> wrote:
On 31 October 2017 at 15:44, Mike Nawrocki
<michael.nawrocki@gtri.gatech.edu> wrote:
> This patch set does a few things. First, it switches the AMD CFI flash MMIO
> operations from the old MMIO API to the new one. Second, it enables 8-byte
> wide flash arrays. Finally, it supports rudimentary interleaving of notional
> flash "chips". It is expected that commands will be sent to all "chips"
> simultaneously. See the example in the second patch for more details. This
> behavior is used by drivers for the PPMC7400 PowerPC evaluation board.
I'm confused by the interleaving part. Can you explain how this
differs from the interleaving we already support in pflash_cfi01.c
via setting width, device-width and max-device-width ? (see the comment
in the pflash_cfi01_properties[] array about how those settings
interact). If it is the same thing, we should really implement it
in the same way for both kinds of flash device.
thanks
-- PMM
Looking through pflash_cfi01.c, it looks essentially the same, though my code doesn’t represent max_device_width. The interleaving in pflash_cfi01.c is more robust than what I implemented. Should I revert the changes to the pflash_cfi02_register prototype and mirror the qdev property implementation pflash_cfi01 uses? This would drastically reduce the number of files affected.
Thanks,
Mike
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-11-01 15:01 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-31 15:44 [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 1/2] Add 8-byte access to AMD CFI devices Mike Nawrocki
2017-10-31 15:44 ` [Qemu-devel] [PATCH 2/2] Add support for flash interleaving of AMD chips Mike Nawrocki
2017-10-31 17:00 ` [Qemu-devel] [PATCH 0/2] Add 8-byte wide AMD flash support, partial interleaving Peter Maydell
2017-11-01 15:01 ` Nawrocki, Michael
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).