From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48481) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eAPQQ-0008Qn-GM for qemu-devel@nongnu.org; Thu, 02 Nov 2017 20:01:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eAPQP-0000u1-LA for qemu-devel@nongnu.org; Thu, 02 Nov 2017 20:01:30 -0400 Received: from mail-lf0-x241.google.com ([2a00:1450:4010:c07::241]:47375) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eAPQP-0000tf-Dx for qemu-devel@nongnu.org; Thu, 02 Nov 2017 20:01:29 -0400 Received: by mail-lf0-x241.google.com with SMTP id k40so1309101lfi.4 for ; Thu, 02 Nov 2017 17:01:29 -0700 (PDT) From: Francisco Iglesias Date: Fri, 3 Nov 2017 01:01:07 +0100 Message-Id: <20171103000109.28244-12-frasse.iglesias@gmail.com> In-Reply-To: <20171103000109.28244-1-frasse.iglesias@gmail.com> References: <20171103000109.28244-1-frasse.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v7 11/13] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgari@xilinx.com, alistai@xilinx.com, francisco.iglesias@feimtech.se, mar.krzeminski@gmail.com, peter.maydell@linaro.org Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias --- hw/ssi/xilinx_spips.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7f0f317..159a89d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state == SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask = IXR_ALL; -- 2.9.3