* [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions
@ 2017-11-03 20:26 Laurent Vivier
2017-11-03 20:26 ` [Qemu-devel] [PATCH 1/4] arm: fix float64 " Laurent Vivier
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Laurent Vivier @ 2017-11-03 20:26 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Aurelien Jarno, Bastian Koppelmann, Stafford Horne,
qemu-arm, Laurent Vivier
This series fixes some errors found by
enabling USE_SOFTFLOAT_STRUCT_TYPES.
Most of them are helpers using int types
instead of float types.
This also requires the use of floatXX_val()
and make_floatXX().
Laurent Vivier (4):
arm: fix float64 helper definitions
openrisc: fix float32 and float64 helper definitions
tricore: use make_float32() and float32_val()
softfloat: use floatXX_val() in XX_minmax()
fpu/softfloat.c | 8 +++----
target/arm/helper-a64.h | 6 ++---
target/openrisc/fpu_helper.c | 52 ++++++++++++++++++++++----------------------
target/openrisc/helper.h | 20 ++++++++---------
target/tricore/fpu_helper.c | 34 ++++++++++++++---------------
5 files changed, 60 insertions(+), 60 deletions(-)
--
2.13.6
^ permalink raw reply [flat|nested] 16+ messages in thread* [Qemu-devel] [PATCH 1/4] arm: fix float64 helper definitions 2017-11-03 20:26 [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions Laurent Vivier @ 2017-11-03 20:26 ` Laurent Vivier 2017-11-07 14:54 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 2017-11-03 20:26 ` [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and " Laurent Vivier ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Laurent Vivier @ 2017-11-03 20:26 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Aurelien Jarno, Bastian Koppelmann, Stafford Horne, qemu-arm, Laurent Vivier neon_ceq_f64(), neon_cge_f64() and neon_cgt_f64() take float64 as parameter, fix the definition in helper-a64.h Signed-off-by: Laurent Vivier <laurent@vivier.eu> --- target/arm/helper-a64.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 85d86741db..b5e9ba03c0 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -26,9 +26,9 @@ DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32) DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) -DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) -DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) -DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) +DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, f64, f64, ptr) +DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, f64, f64, ptr) +DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, f64, f64, ptr) DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) -- 2.13.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 1/4] arm: fix float64 helper definitions 2017-11-03 20:26 ` [Qemu-devel] [PATCH 1/4] arm: fix float64 " Laurent Vivier @ 2017-11-07 14:54 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-07 14:54 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno Hi Laurent, On 11/03/2017 05:26 PM, Laurent Vivier wrote: > neon_ceq_f64(), neon_cge_f64() and neon_cgt_f64() > take float64 as parameter, fix the definition in > helper-a64.h > > Signed-off-by: Laurent Vivier <laurent@vivier.eu> > --- > target/arm/helper-a64.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h > index 85d86741db..b5e9ba03c0 100644 > --- a/target/arm/helper-a64.h > +++ b/target/arm/helper-a64.h > @@ -26,9 +26,9 @@ DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr) > DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32) > DEF_HELPER_FLAGS_3(vfp_mulxs, TCG_CALL_NO_RWG, f32, f32, f32, ptr) > DEF_HELPER_FLAGS_3(vfp_mulxd, TCG_CALL_NO_RWG, f64, f64, f64, ptr) > -DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) > -DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) > -DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, i64, i64, ptr) > +DEF_HELPER_FLAGS_3(neon_ceq_f64, TCG_CALL_NO_RWG, i64, f64, f64, ptr) > +DEF_HELPER_FLAGS_3(neon_cge_f64, TCG_CALL_NO_RWG, i64, f64, f64, ptr) > +DEF_HELPER_FLAGS_3(neon_cgt_f64, TCG_CALL_NO_RWG, i64, f64, f64, ptr) > DEF_HELPER_FLAGS_3(recpsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) > DEF_HELPER_FLAGS_3(recpsf_f64, TCG_CALL_NO_RWG, f64, f64, f64, ptr) > DEF_HELPER_FLAGS_3(rsqrtsf_f32, TCG_CALL_NO_RWG, f32, f32, f32, ptr) As commented replying to your series cover, this patch seems missing: diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c @@ -159,8 +159,8 @@ uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices, */ int elt = (rn * 2 + (index >> 3)) % 64; int bitidx = (index & 7) * 8; - uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8); - + uint64_t val = extract64(float64_val(env->vfp.regs[elt]), + bitidx, 8); result = deposit64(result, shift, 8, val); } } Regards, Phil. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and float64 helper definitions 2017-11-03 20:26 [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions Laurent Vivier 2017-11-03 20:26 ` [Qemu-devel] [PATCH 1/4] arm: fix float64 " Laurent Vivier @ 2017-11-03 20:26 ` Laurent Vivier 2017-11-04 21:20 ` Stafford Horne 2017-11-07 14:38 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 2017-11-03 20:26 ` [Qemu-devel] [PATCH 3/4] tricore: use make_float32() and float32_val() Laurent Vivier ` (2 subsequent siblings) 4 siblings, 2 replies; 16+ messages in thread From: Laurent Vivier @ 2017-11-03 20:26 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Aurelien Jarno, Bastian Koppelmann, Stafford Horne, qemu-arm, Laurent Vivier Signed-off-by: Laurent Vivier <laurent@vivier.eu> --- target/openrisc/fpu_helper.c | 52 ++++++++++++++++++++++---------------------- target/openrisc/helper.h | 20 ++++++++--------- 2 files changed, 36 insertions(+), 36 deletions(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index 1375cea948..f84f8bf26a 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -66,9 +66,9 @@ static inline void update_fpcsr(OpenRISCCPU *cpu) } } -uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) +float64 HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) { - uint64_t itofd; + float64 itofd; OpenRISCCPU *cpu = openrisc_env_get_cpu(env); set_float_exception_flags(0, &cpu->env.fp_status); @@ -78,9 +78,9 @@ uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) return itofd; } -uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) +float32 HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) { - uint32_t itofs; + float32 itofs; OpenRISCCPU *cpu = openrisc_env_get_cpu(env); set_float_exception_flags(0, &cpu->env.fp_status); @@ -90,7 +90,7 @@ uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) return itofs; } -uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) +uint64_t HELPER(ftoid)(CPUOpenRISCState *env, float32 val) { uint64_t ftoid; OpenRISCCPU *cpu = openrisc_env_get_cpu(env); @@ -102,7 +102,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) return ftoid; } -uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) +uint32_t HELPER(ftois)(CPUOpenRISCState *env, float32 val) { uint32_t ftois; OpenRISCCPU *cpu = openrisc_env_get_cpu(env); @@ -117,10 +117,10 @@ uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) #define FLOAT_OP(name, p) void helper_float_##_##p(void) #define FLOAT_CALC(name) \ -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ +float64 helper_float_ ## name ## _d(CPUOpenRISCState *env, \ + float64 fdt0, float64 fdt1) \ { \ - uint64_t result; \ + float64 result; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ set_float_exception_flags(0, &cpu->env.fp_status); \ result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ @@ -128,10 +128,10 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ return result; \ } \ \ -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ +float32 helper_float_ ## name ## _s(CPUOpenRISCState *env, \ + float32 fdt0, float32 fdt1) \ { \ - uint32_t result; \ + float32 result; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ set_float_exception_flags(0, &cpu->env.fp_status); \ result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ @@ -147,11 +147,11 @@ FLOAT_CALC(rem) #undef FLOAT_CALC -uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, - uint64_t b, uint64_t c) +float64 helper_float_madd_d(CPUOpenRISCState *env, float64 a, + float64 b, float64 c) { OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - uint64_t result; + float64 result; set_float_exception_flags(0, &cpu->env.fp_status); /* Note that or1ksim doesn't use merged operation. */ result = float64_mul(b, c, &cpu->env.fp_status); @@ -160,11 +160,11 @@ uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, return result; } -uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, - uint32_t b, uint32_t c) +float32 helper_float_madd_s(CPUOpenRISCState *env, float32 a, + float32 b, float32 c) { OpenRISCCPU *cpu = openrisc_env_get_cpu(env); - uint32_t result; + float32 result; set_float_exception_flags(0, &cpu->env.fp_status); /* Note that or1ksim doesn't use merged operation. */ result = float32_mul(b, c, &cpu->env.fp_status); @@ -176,7 +176,7 @@ uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, #define FLOAT_CMP(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ + float64 fdt0, float64 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -187,7 +187,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ } \ \ uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1)\ + float32 fdt0, float32 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -205,7 +205,7 @@ FLOAT_CMP(lt) #define FLOAT_CMPNE(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ + float64 fdt0, float64 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -216,7 +216,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ } \ \ uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ + float32 fdt0, float32 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -231,7 +231,7 @@ FLOAT_CMPNE(ne) #define FLOAT_CMPGT(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ + float64 fdt0, float64 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -242,7 +242,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ } \ \ uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ + float32 fdt0, float32 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -256,7 +256,7 @@ FLOAT_CMPGT(gt) #define FLOAT_CMPGE(name) \ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ - uint64_t fdt0, uint64_t fdt1) \ + float64 fdt0, float64 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ @@ -267,7 +267,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ } \ \ uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ - uint32_t fdt0, uint32_t fdt1) \ + float32 fdt0, float32 fdt1) \ { \ int res; \ OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index 4fd1a6bb8e..081606527b 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -24,17 +24,17 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env) DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env) /* float */ -DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) -DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, f64, env, i64) +DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, f32, env, i32) +DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, f32) +DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, f32) -DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) -DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, f32, env, f32, f32, f32) +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, f64, env, f64, f64, f64) #define FOP_CALC(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, f32, env, f32, f32) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, f64, env, f64, f64) FOP_CALC(add) FOP_CALC(sub) FOP_CALC(mul) @@ -43,8 +43,8 @@ FOP_CALC(rem) #undef FOP_CALC #define FOP_CMP(op) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, f32, f32) \ +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, f64, f64) FOP_CMP(eq) FOP_CMP(lt) FOP_CMP(le) -- 2.13.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and float64 helper definitions 2017-11-03 20:26 ` [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and " Laurent Vivier @ 2017-11-04 21:20 ` Stafford Horne 2017-11-05 14:39 ` Laurent Vivier 2017-11-07 14:38 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 1 sibling, 1 reply; 16+ messages in thread From: Stafford Horne @ 2017-11-04 21:20 UTC (permalink / raw) To: Laurent Vivier Cc: qemu-devel, Peter Maydell, Aurelien Jarno, Bastian Koppelmann, qemu-arm Hello, On Fri, Nov 03, 2017 at 09:26:22PM +0100, Laurent Vivier wrote: > Signed-off-by: Laurent Vivier <laurent@vivier.eu> There is no commit body here, do we need one? I can see in your cover letter its mentioned this was revealed after enabling "USE_SOFTFLOAT_STRUCT_TYPES". However, I'm just being curious why is this an issue? In softfloat I assume we pack our own floats so having the type that goes into a uint32 register wouldnt make much difference right? -Stafford > --- > target/openrisc/fpu_helper.c | 52 ++++++++++++++++++++++---------------------- > target/openrisc/helper.h | 20 ++++++++--------- > 2 files changed, 36 insertions(+), 36 deletions(-) > > diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c > index 1375cea948..f84f8bf26a 100644 > --- a/target/openrisc/fpu_helper.c > +++ b/target/openrisc/fpu_helper.c > @@ -66,9 +66,9 @@ static inline void update_fpcsr(OpenRISCCPU *cpu) > } > } > > -uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) > +float64 HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) > { > - uint64_t itofd; > + float64 itofd; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > > set_float_exception_flags(0, &cpu->env.fp_status); > @@ -78,9 +78,9 @@ uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) > return itofd; > } > > -uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) > +float32 HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) > { > - uint32_t itofs; > + float32 itofs; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > > set_float_exception_flags(0, &cpu->env.fp_status); > @@ -90,7 +90,7 @@ uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) > return itofs; > } > > -uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) > +uint64_t HELPER(ftoid)(CPUOpenRISCState *env, float32 val) > { > uint64_t ftoid; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > @@ -102,7 +102,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) > return ftoid; > } > > -uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) > +uint32_t HELPER(ftois)(CPUOpenRISCState *env, float32 val) > { > uint32_t ftois; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > @@ -117,10 +117,10 @@ uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) > #define FLOAT_OP(name, p) void helper_float_##_##p(void) > > #define FLOAT_CALC(name) \ > -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > +float64 helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > + float64 fdt0, float64 fdt1) \ > { \ > - uint64_t result; \ > + float64 result; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > set_float_exception_flags(0, &cpu->env.fp_status); \ > result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ > @@ -128,10 +128,10 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > return result; \ > } \ > \ > -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > +float32 helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > + float32 fdt0, float32 fdt1) \ > { \ > - uint32_t result; \ > + float32 result; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > set_float_exception_flags(0, &cpu->env.fp_status); \ > result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ > @@ -147,11 +147,11 @@ FLOAT_CALC(rem) > #undef FLOAT_CALC > > > -uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, > - uint64_t b, uint64_t c) > +float64 helper_float_madd_d(CPUOpenRISCState *env, float64 a, > + float64 b, float64 c) > { > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > - uint64_t result; > + float64 result; > set_float_exception_flags(0, &cpu->env.fp_status); > /* Note that or1ksim doesn't use merged operation. */ > result = float64_mul(b, c, &cpu->env.fp_status); > @@ -160,11 +160,11 @@ uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, > return result; > } > > -uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, > - uint32_t b, uint32_t c) > +float32 helper_float_madd_s(CPUOpenRISCState *env, float32 a, > + float32 b, float32 c) > { > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > - uint32_t result; > + float32 result; > set_float_exception_flags(0, &cpu->env.fp_status); > /* Note that or1ksim doesn't use merged operation. */ > result = float32_mul(b, c, &cpu->env.fp_status); > @@ -176,7 +176,7 @@ uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, > > #define FLOAT_CMP(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -187,7 +187,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1)\ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -205,7 +205,7 @@ FLOAT_CMP(lt) > > #define FLOAT_CMPNE(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -216,7 +216,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -231,7 +231,7 @@ FLOAT_CMPNE(ne) > > #define FLOAT_CMPGT(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -242,7 +242,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -256,7 +256,7 @@ FLOAT_CMPGT(gt) > > #define FLOAT_CMPGE(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -267,7 +267,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h > index 4fd1a6bb8e..081606527b 100644 > --- a/target/openrisc/helper.h > +++ b/target/openrisc/helper.h > @@ -24,17 +24,17 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env) > DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env) > > /* float */ > -DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64) > -DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) > -DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) > -DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) > +DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, f64, env, i64) > +DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, f32, env, i32) > +DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, f32) > +DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, f32) > > -DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) > -DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) > +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, f32, env, f32, f32, f32) > +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, f64, env, f64, f64, f64) > > #define FOP_CALC(op) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, f32, env, f32, f32) \ > +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, f64, env, f64, f64) > FOP_CALC(add) > FOP_CALC(sub) > FOP_CALC(mul) > @@ -43,8 +43,8 @@ FOP_CALC(rem) > #undef FOP_CALC > > #define FOP_CMP(op) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, f32, f32) \ > +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, f64, f64) > FOP_CMP(eq) > FOP_CMP(lt) > FOP_CMP(le) > -- > 2.13.6 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and float64 helper definitions 2017-11-04 21:20 ` Stafford Horne @ 2017-11-05 14:39 ` Laurent Vivier 2017-11-07 10:59 ` Stafford Horne 0 siblings, 1 reply; 16+ messages in thread From: Laurent Vivier @ 2017-11-05 14:39 UTC (permalink / raw) To: Stafford Horne Cc: qemu-devel, Peter Maydell, Aurelien Jarno, Bastian Koppelmann, qemu-arm Le 04/11/2017 à 22:20, Stafford Horne a écrit : > Hello, > > On Fri, Nov 03, 2017 at 09:26:22PM +0100, Laurent Vivier wrote: >> Signed-off-by: Laurent Vivier <laurent@vivier.eu> > > There is no commit body here, do we need one? I can see in your cover letter > its mentioned this was revealed after enabling "USE_SOFTFLOAT_STRUCT_TYPES". > > However, I'm just being curious why is this an issue? In softfloat I assume we > pack our own floats so having the type that goes into a uint32 register wouldnt > make much difference right? It's not an issue. It's for consistency. We can store a float32 in an uint32_t, but it's better to store float32 in float32 type. And as said in include/fpu/softfloat.h: "Use structures for soft-float types. This prevents accidentally mixing them with native int/float types." Thanks, Laurent ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and float64 helper definitions 2017-11-05 14:39 ` Laurent Vivier @ 2017-11-07 10:59 ` Stafford Horne 0 siblings, 0 replies; 16+ messages in thread From: Stafford Horne @ 2017-11-07 10:59 UTC (permalink / raw) To: Laurent Vivier Cc: qemu-devel, Peter Maydell, Aurelien Jarno, Bastian Koppelmann, qemu-arm On Sun, Nov 05, 2017 at 03:39:48PM +0100, Laurent Vivier wrote: > Le 04/11/2017 à 22:20, Stafford Horne a écrit : > > Hello, > > > > On Fri, Nov 03, 2017 at 09:26:22PM +0100, Laurent Vivier wrote: > >> Signed-off-by: Laurent Vivier <laurent@vivier.eu> > > > > There is no commit body here, do we need one? I can see in your cover letter > > its mentioned this was revealed after enabling "USE_SOFTFLOAT_STRUCT_TYPES". > > > > However, I'm just being curious why is this an issue? In softfloat I assume we > > pack our own floats so having the type that goes into a uint32 register wouldnt > > make much difference right? > > It's not an issue. It's for consistency. We can store a float32 in an > uint32_t, but it's better to store float32 in float32 type. OK, thank you. > And as said in include/fpu/softfloat.h: > > "Use structures for soft-float types. This prevents accidentally mixing > them with native int/float types." Thanks, I have not tested this but I trust it should not be an issue. Acked-by: Stafford Horne <shorne@gmail.com> -Stafford ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 2/4] openrisc: fix float32 and float64 helper definitions 2017-11-03 20:26 ` [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and " Laurent Vivier 2017-11-04 21:20 ` Stafford Horne @ 2017-11-07 14:38 ` Philippe Mathieu-Daudé 1 sibling, 0 replies; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-07 14:38 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno On 11/03/2017 05:26 PM, Laurent Vivier wrote: > Signed-off-by: Laurent Vivier <laurent@vivier.eu> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/openrisc/fpu_helper.c | 52 ++++++++++++++++++++++---------------------- > target/openrisc/helper.h | 20 ++++++++--------- > 2 files changed, 36 insertions(+), 36 deletions(-) > > diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c > index 1375cea948..f84f8bf26a 100644 > --- a/target/openrisc/fpu_helper.c > +++ b/target/openrisc/fpu_helper.c > @@ -66,9 +66,9 @@ static inline void update_fpcsr(OpenRISCCPU *cpu) > } > } > > -uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) > +float64 HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) > { > - uint64_t itofd; > + float64 itofd; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > > set_float_exception_flags(0, &cpu->env.fp_status); > @@ -78,9 +78,9 @@ uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val) > return itofd; > } > > -uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) > +float32 HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) > { > - uint32_t itofs; > + float32 itofs; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > > set_float_exception_flags(0, &cpu->env.fp_status); > @@ -90,7 +90,7 @@ uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val) > return itofs; > } > > -uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) > +uint64_t HELPER(ftoid)(CPUOpenRISCState *env, float32 val) > { > uint64_t ftoid; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > @@ -102,7 +102,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val) > return ftoid; > } > > -uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) > +uint32_t HELPER(ftois)(CPUOpenRISCState *env, float32 val) > { > uint32_t ftois; > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > @@ -117,10 +117,10 @@ uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val) > #define FLOAT_OP(name, p) void helper_float_##_##p(void) > > #define FLOAT_CALC(name) \ > -uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > +float64 helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > + float64 fdt0, float64 fdt1) \ > { \ > - uint64_t result; \ > + float64 result; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > set_float_exception_flags(0, &cpu->env.fp_status); \ > result = float64_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ > @@ -128,10 +128,10 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > return result; \ > } \ > \ > -uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > +float32 helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > + float32 fdt0, float32 fdt1) \ > { \ > - uint32_t result; \ > + float32 result; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > set_float_exception_flags(0, &cpu->env.fp_status); \ > result = float32_ ## name(fdt0, fdt1, &cpu->env.fp_status); \ > @@ -147,11 +147,11 @@ FLOAT_CALC(rem) > #undef FLOAT_CALC > > > -uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, > - uint64_t b, uint64_t c) > +float64 helper_float_madd_d(CPUOpenRISCState *env, float64 a, > + float64 b, float64 c) > { > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > - uint64_t result; > + float64 result; > set_float_exception_flags(0, &cpu->env.fp_status); > /* Note that or1ksim doesn't use merged operation. */ > result = float64_mul(b, c, &cpu->env.fp_status); > @@ -160,11 +160,11 @@ uint64_t helper_float_madd_d(CPUOpenRISCState *env, uint64_t a, > return result; > } > > -uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, > - uint32_t b, uint32_t c) > +float32 helper_float_madd_s(CPUOpenRISCState *env, float32 a, > + float32 b, float32 c) > { > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); > - uint32_t result; > + float32 result; > set_float_exception_flags(0, &cpu->env.fp_status); > /* Note that or1ksim doesn't use merged operation. */ > result = float32_mul(b, c, &cpu->env.fp_status); > @@ -176,7 +176,7 @@ uint32_t helper_float_madd_s(CPUOpenRISCState *env, uint32_t a, > > #define FLOAT_CMP(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -187,7 +187,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1)\ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -205,7 +205,7 @@ FLOAT_CMP(lt) > > #define FLOAT_CMPNE(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -216,7 +216,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -231,7 +231,7 @@ FLOAT_CMPNE(ne) > > #define FLOAT_CMPGT(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -242,7 +242,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -256,7 +256,7 @@ FLOAT_CMPGT(gt) > > #define FLOAT_CMPGE(name) \ > uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > - uint64_t fdt0, uint64_t fdt1) \ > + float64 fdt0, float64 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > @@ -267,7 +267,7 @@ uint64_t helper_float_ ## name ## _d(CPUOpenRISCState *env, \ > } \ > \ > uint32_t helper_float_ ## name ## _s(CPUOpenRISCState *env, \ > - uint32_t fdt0, uint32_t fdt1) \ > + float32 fdt0, float32 fdt1) \ > { \ > int res; \ > OpenRISCCPU *cpu = openrisc_env_get_cpu(env); \ > diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h > index 4fd1a6bb8e..081606527b 100644 > --- a/target/openrisc/helper.h > +++ b/target/openrisc/helper.h > @@ -24,17 +24,17 @@ DEF_HELPER_FLAGS_1(ove_ov, TCG_CALL_NO_WG, void, env) > DEF_HELPER_FLAGS_1(ove_cyov, TCG_CALL_NO_WG, void, env) > > /* float */ > -DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, i64, env, i64) > -DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, i32, env, i32) > -DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, i64) > -DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, i32) > +DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_WG, f64, env, i64) > +DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_WG, f32, env, i32) > +DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_WG, i64, env, f32) > +DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_WG, i32, env, f32) > > -DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, i32, env, i32, i32, i32) > -DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, i64, env, i64, i64, i64) > +DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_WG, f32, env, f32, f32, f32) > +DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_WG, f64, env, f64, f64, f64) > > #define FOP_CALC(op) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, f32, env, f32, f32) \ > +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, f64, env, f64, f64) > FOP_CALC(add) > FOP_CALC(sub) > FOP_CALC(mul) > @@ -43,8 +43,8 @@ FOP_CALC(rem) > #undef FOP_CALC > > #define FOP_CMP(op) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, i32, i32) \ > -DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, i64, i64) > +DEF_HELPER_FLAGS_3(float_ ## op ## _s, TCG_CALL_NO_WG, i32, env, f32, f32) \ > +DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_WG, i64, env, f64, f64) > FOP_CMP(eq) > FOP_CMP(lt) > FOP_CMP(le) > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 3/4] tricore: use make_float32() and float32_val() 2017-11-03 20:26 [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions Laurent Vivier 2017-11-03 20:26 ` [Qemu-devel] [PATCH 1/4] arm: fix float64 " Laurent Vivier 2017-11-03 20:26 ` [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and " Laurent Vivier @ 2017-11-03 20:26 ` Laurent Vivier 2017-11-07 14:40 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 2017-11-03 20:26 ` [Qemu-devel] [PATCH 4/4] softfloat: use floatXX_val() in XX_minmax() Laurent Vivier 2017-11-03 21:27 ` [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions Philippe Mathieu-Daudé 4 siblings, 1 reply; 16+ messages in thread From: Laurent Vivier @ 2017-11-03 20:26 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Aurelien Jarno, Bastian Koppelmann, Stafford Horne, qemu-arm, Laurent Vivier Signed-off-by: Laurent Vivier <laurent@vivier.eu> --- target/tricore/fpu_helper.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index 7979bb6692..d233d010c5 100644 --- a/target/tricore/fpu_helper.c +++ b/target/tricore/fpu_helper.c @@ -21,10 +21,10 @@ #include "cpu.h" #include "exec/helper-proto.h" -#define QUIET_NAN 0x7fc00000 -#define ADD_NAN 0x7fc00001 -#define DIV_NAN 0x7fc00008 -#define MUL_NAN 0x7fc00002 +#define QUIET_NAN make_float32(0x7fc00000) +#define ADD_NAN make_float32(0x7fc00001) +#define DIV_NAN make_float32(0x7fc00008) +#define MUL_NAN make_float32(0x7fc00002) #define FPU_FS PSW_USB_C #define FPU_FI PSW_USB_V #define FPU_FV PSW_USB_SV @@ -63,13 +63,13 @@ static inline float32 f_maddsub_nan_result(float32 arg1, float32 arg2, } else if (float32_is_zero(arg1) && float32_is_infinity(arg2)) { return MUL_NAN; } else { - aSign = arg1 >> 31; - bSign = arg2 >> 31; - cSign = arg3 >> 31; + aSign = float32_val(arg1) >> 31; + bSign = float32_val(arg2) >> 31; + cSign = float32_val(arg3) >> 31; - aExp = (arg1 >> 23) & 0xff; - bExp = (arg2 >> 23) & 0xff; - cExp = (arg3 >> 23) & 0xff; + aExp = (float32_val(arg1) >> 23) & 0xff; + bExp = (float32_val(arg2) >> 23) & 0xff; + cExp = (float32_val(arg3) >> 23) & 0xff; if (muladd_negate_c) { cSign ^= 1; @@ -139,7 +139,7 @@ uint32_t helper_f##op(CPUTriCoreState *env, uint32_t r1, uint32_t r2) \ } else { \ env->FPU_FS = 0; \ } \ - return (uint32_t)f_result; \ + return float32_val(f_result); \ } FADD_SUB(add) FADD_SUB(sub) @@ -166,7 +166,7 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2) } else { env->FPU_FS = 0; } - return (uint32_t)f_result; + return float32_val(f_result); } @@ -193,7 +193,7 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) env->FPU_FS = 0; } - return (uint32_t)f_result; + return float32_val(f_result); } uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1, @@ -219,7 +219,7 @@ uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1, } else { env->FPU_FS = 0; } - return (uint32_t)f_result; + return float32_val(f_result); } uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1, @@ -247,7 +247,7 @@ uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1, } else { env->FPU_FS = 0; } - return (uint32_t)f_result; + return float32_val(f_result); } uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2) @@ -304,7 +304,7 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg) } else { env->FPU_FS = 0; } - return (uint32_t)f_result; + return float32_val(f_result); } uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) @@ -321,7 +321,7 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) if (float32_is_any_nan(f_arg)) { result = 0; } - } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) { + } else if (float32_lt_quiet(f_arg, float32_zero, &env->fp_status)) { flags = float_flag_invalid; result = 0; } -- 2.13.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 3/4] tricore: use make_float32() and float32_val() 2017-11-03 20:26 ` [Qemu-devel] [PATCH 3/4] tricore: use make_float32() and float32_val() Laurent Vivier @ 2017-11-07 14:40 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-07 14:40 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno On 11/03/2017 05:26 PM, Laurent Vivier wrote: > Signed-off-by: Laurent Vivier <laurent@vivier.eu> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/tricore/fpu_helper.c | 34 +++++++++++++++++----------------- > 1 file changed, 17 insertions(+), 17 deletions(-) > > diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c > index 7979bb6692..d233d010c5 100644 > --- a/target/tricore/fpu_helper.c > +++ b/target/tricore/fpu_helper.c > @@ -21,10 +21,10 @@ > #include "cpu.h" > #include "exec/helper-proto.h" > > -#define QUIET_NAN 0x7fc00000 > -#define ADD_NAN 0x7fc00001 > -#define DIV_NAN 0x7fc00008 > -#define MUL_NAN 0x7fc00002 > +#define QUIET_NAN make_float32(0x7fc00000) > +#define ADD_NAN make_float32(0x7fc00001) > +#define DIV_NAN make_float32(0x7fc00008) > +#define MUL_NAN make_float32(0x7fc00002) > #define FPU_FS PSW_USB_C > #define FPU_FI PSW_USB_V > #define FPU_FV PSW_USB_SV > @@ -63,13 +63,13 @@ static inline float32 f_maddsub_nan_result(float32 arg1, float32 arg2, > } else if (float32_is_zero(arg1) && float32_is_infinity(arg2)) { > return MUL_NAN; > } else { > - aSign = arg1 >> 31; > - bSign = arg2 >> 31; > - cSign = arg3 >> 31; > + aSign = float32_val(arg1) >> 31; > + bSign = float32_val(arg2) >> 31; > + cSign = float32_val(arg3) >> 31; > > - aExp = (arg1 >> 23) & 0xff; > - bExp = (arg2 >> 23) & 0xff; > - cExp = (arg3 >> 23) & 0xff; > + aExp = (float32_val(arg1) >> 23) & 0xff; > + bExp = (float32_val(arg2) >> 23) & 0xff; > + cExp = (float32_val(arg3) >> 23) & 0xff; > > if (muladd_negate_c) { > cSign ^= 1; > @@ -139,7 +139,7 @@ uint32_t helper_f##op(CPUTriCoreState *env, uint32_t r1, uint32_t r2) \ > } else { \ > env->FPU_FS = 0; \ > } \ > - return (uint32_t)f_result; \ > + return float32_val(f_result); \ > } > FADD_SUB(add) > FADD_SUB(sub) > @@ -166,7 +166,7 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2) > } else { > env->FPU_FS = 0; > } > - return (uint32_t)f_result; > + return float32_val(f_result); > > } > > @@ -193,7 +193,7 @@ uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) > env->FPU_FS = 0; > } > > - return (uint32_t)f_result; > + return float32_val(f_result); > } > > uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1, > @@ -219,7 +219,7 @@ uint32_t helper_fmadd(CPUTriCoreState *env, uint32_t r1, > } else { > env->FPU_FS = 0; > } > - return (uint32_t)f_result; > + return float32_val(f_result); > } > > uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1, > @@ -247,7 +247,7 @@ uint32_t helper_fmsub(CPUTriCoreState *env, uint32_t r1, > } else { > env->FPU_FS = 0; > } > - return (uint32_t)f_result; > + return float32_val(f_result); > } > > uint32_t helper_fcmp(CPUTriCoreState *env, uint32_t r1, uint32_t r2) > @@ -304,7 +304,7 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg) > } else { > env->FPU_FS = 0; > } > - return (uint32_t)f_result; > + return float32_val(f_result); > } > > uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) > @@ -321,7 +321,7 @@ uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) > if (float32_is_any_nan(f_arg)) { > result = 0; > } > - } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) { > + } else if (float32_lt_quiet(f_arg, float32_zero, &env->fp_status)) { > flags = float_flag_invalid; > result = 0; > } > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH 4/4] softfloat: use floatXX_val() in XX_minmax() 2017-11-03 20:26 [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions Laurent Vivier ` (2 preceding siblings ...) 2017-11-03 20:26 ` [Qemu-devel] [PATCH 3/4] tricore: use make_float32() and float32_val() Laurent Vivier @ 2017-11-03 20:26 ` Laurent Vivier 2017-11-03 21:27 ` [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions Philippe Mathieu-Daudé 4 siblings, 0 replies; 16+ messages in thread From: Laurent Vivier @ 2017-11-03 20:26 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Aurelien Jarno, Bastian Koppelmann, Stafford Horne, qemu-arm, Laurent Vivier Signed-off-by: Laurent Vivier <laurent@vivier.eu> --- fpu/softfloat.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 433c5dad2d..331d78e848 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -7700,11 +7700,9 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \ } \ aSign = extractFloat ## s ## Sign(a); \ bSign = extractFloat ## s ## Sign(b); \ - av = float ## s ## _val(a); \ - bv = float ## s ## _val(b); \ if (ismag) { \ - aav = float ## s ## _abs(av); \ - abv = float ## s ## _abs(bv); \ + aav = float ## s ## _val(float ## s ## _abs(a)); \ + abv = float ## s ## _val(float ## s ## _abs(b)); \ if (aav != abv) { \ if (ismin) { \ return (aav < abv) ? a : b; \ @@ -7713,6 +7711,8 @@ static inline float ## s float ## s ## _minmax(float ## s a, float ## s b, \ } \ } \ } \ + av = float ## s ## _val(a); \ + bv = float ## s ## _val(b); \ if (aSign != bSign) { \ if (ismin) { \ return aSign ? a : b; \ -- 2.13.6 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions 2017-11-03 20:26 [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions Laurent Vivier ` (3 preceding siblings ...) 2017-11-03 20:26 ` [Qemu-devel] [PATCH 4/4] softfloat: use floatXX_val() in XX_minmax() Laurent Vivier @ 2017-11-03 21:27 ` Philippe Mathieu-Daudé 2017-11-03 21:51 ` Philippe Mathieu-Daudé 4 siblings, 1 reply; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-03 21:27 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno Hi Laurent, On 11/03/2017 05:26 PM, Laurent Vivier wrote: > This series fixes some errors found by > enabling USE_SOFTFLOAT_STRUCT_TYPES. > > Most of them are helpers using int types > instead of float types. > This also requires the use of floatXX_val() > and make_floatXX(). > > Laurent Vivier (4): > arm: fix float64 helper definitions > openrisc: fix float32 and float64 helper definitions > tricore: use make_float32() and float32_val() > softfloat: use floatXX_val() in XX_minmax() > > fpu/softfloat.c | 8 +++---- > target/arm/helper-a64.h | 6 ++--- > target/openrisc/fpu_helper.c | 52 ++++++++++++++++++++++---------------------- > target/openrisc/helper.h | 20 ++++++++--------- > target/tricore/fpu_helper.c | 34 ++++++++++++++--------------- > 5 files changed, 60 insertions(+), 60 deletions(-) > I'm getting those errors: $ make subdir-arm-softmmu -j2 /source/qemu/migration/vmstate-types.c:430:5: error: conversion to non-scalar type requested qemu_put_be64(f, float64_val(*v)); ^~~~~~~~~~~~~ make: *** [migration/vmstate-types.o] Error 1 In file included from /source/qemu/fpu/softfloat.c:87:0: /source/qemu/fpu/softfloat-specialize.h: In function ‘float16_default_nan’: /source/qemu/include/fpu/softfloat.h:117:26: error: expected expression before ‘{’ token #define const_float16(x) { x } ^ /source/qemu/fpu/softfloat-specialize.h:95:12: note: in expansion of macro ‘const_float16’ return const_float16(0x7E00); ^~~~~~~~~~~~~ make: *** [fpu/softfloat.o] Error 1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions 2017-11-03 21:27 ` [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions Philippe Mathieu-Daudé @ 2017-11-03 21:51 ` Philippe Mathieu-Daudé 2017-11-04 8:55 ` Laurent Vivier 0 siblings, 1 reply; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-03 21:51 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno > On 11/03/2017 05:26 PM, Laurent Vivier wrote: >> This series fixes some errors found by >> enabling USE_SOFTFLOAT_STRUCT_TYPES. [...] > > I'm getting those errors: > > $ make subdir-arm-softmmu -j2 > > /source/qemu/migration/vmstate-types.c:430:5: error: conversion to > non-scalar type requested > qemu_put_be64(f, float64_val(*v)); > ^~~~~~~~~~~~~ > make: *** [migration/vmstate-types.o] Error 1 > > In file included from /source/qemu/fpu/softfloat.c:87:0: > /source/qemu/fpu/softfloat-specialize.h: In function ‘float16_default_nan’: > /source/qemu/include/fpu/softfloat.h:117:26: error: expected expression > before ‘{’ token > #define const_float16(x) { x } > ^ > /source/qemu/fpu/softfloat-specialize.h:95:12: note: in expansion of > macro ‘const_float16’ > return const_float16(0x7E00); > ^~~~~~~~~~~~~ > make: *** [fpu/softfloat.o] Error 1 > Also: $ make subdir-armeb-linux-user -j2 CC linux-user/signal.o In file included from /source/qemu/linux-user/signal.c:24:0: /source/qemu/linux-user/signal.c: In function ‘restore_sigframe_v2_vfp’: /source/qemu/linux-user/qemu.h:472:8: error: lvalue required as left operand of assignment ((x) = (typeof(*hptr))( \ ^ /source/qemu/linux-user/qemu.h:481:31: note: in expansion of macro ‘__get_user_e’ # define __get_user(x, hptr) __get_user_e(x, hptr, be) ^~~~~~~~~~~~ /source/qemu/linux-user/signal.c:2209:9: note: in expansion of macro ‘__get_user’ __get_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]); ^~~~~~~~~~ /source/qemu/linux-user/qemu.h:477:13: error: left-hand operand of comma expression has no effect [-Werror=unused-value] (hptr)), (void)0) ^ /source/qemu/linux-user/qemu.h:481:31: note: in expansion of macro ‘__get_user_e’ # define __get_user(x, hptr) __get_user_e(x, hptr, be) ^~~~~~~~~~~~ /source/qemu/linux-user/signal.c:2209:9: note: in expansion of macro ‘__get_user’ __get_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]); ^~~~~~~~~~ cc1: all warnings being treated as errors /source/qemu/rules.mak:66: recipe for target 'linux-user/signal.o' failed CC linux-user/arm/nwfpe/fpa11_cpdt.o ... /source/qemu/linux-user/arm/nwfpe/fpa11_cpdt.c:37:4: note: in expansion of macro ‘get_user_u32’ get_user_u32(float32_val(fpa11->fpreg[Fn].fSingle), addr); ^~~~~~~~~~~~ /source/qemu/linux-user/qemu.h:515:13: error: lvalue required as left operand of assignment (x) = 0; \ ^ /source/qemu/linux-user/qemu.h:536:32: note: in expansion of macro ‘get_user’ #define get_user_u32(x, gaddr) get_user((x), (gaddr), uint32_t) ^~~~~~~~ /source/qemu/linux-user/arm/nwfpe/fpa11_cpdt.c:37:4: note: in expansion of macro ‘get_user_u32’ get_user_u32(float32_val(fpa11->fpreg[Fn].fSingle), addr); ^~~~~~~~~~~~ ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions 2017-11-03 21:51 ` Philippe Mathieu-Daudé @ 2017-11-04 8:55 ` Laurent Vivier 2017-11-04 16:18 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 16+ messages in thread From: Laurent Vivier @ 2017-11-04 8:55 UTC (permalink / raw) To: Philippe Mathieu-Daudé, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno Le 03/11/2017 à 22:51, Philippe Mathieu-Daudé a écrit : >> On 11/03/2017 05:26 PM, Laurent Vivier wrote: >>> This series fixes some errors found by >>> enabling USE_SOFTFLOAT_STRUCT_TYPES. > [...] >> >> I'm getting those errors: >> >> $ make subdir-arm-softmmu -j2 >> >> /source/qemu/migration/vmstate-types.c:430:5: error: conversion to >> non-scalar type requested >> qemu_put_be64(f, float64_val(*v)); >> ^~~~~~~~~~~~~ >> make: *** [migration/vmstate-types.o] Error 1 >> >> In file included from /source/qemu/fpu/softfloat.c:87:0: >> /source/qemu/fpu/softfloat-specialize.h: In function ‘float16_default_nan’: >> /source/qemu/include/fpu/softfloat.h:117:26: error: expected expression >> before ‘{’ token >> #define const_float16(x) { x } >> ^ >> /source/qemu/fpu/softfloat-specialize.h:95:12: note: in expansion of >> macro ‘const_float16’ >> return const_float16(0x7E00); >> ^~~~~~~~~~~~~ >> make: *** [fpu/softfloat.o] Error 1 >> > > Also: > > $ make subdir-armeb-linux-user -j2 > > CC linux-user/signal.o > In file included from /source/qemu/linux-user/signal.c:24:0: > /source/qemu/linux-user/signal.c: In function ‘restore_sigframe_v2_vfp’: > /source/qemu/linux-user/qemu.h:472:8: error: lvalue required as left > operand of assignment > ((x) = (typeof(*hptr))( \ > ^ > /source/qemu/linux-user/qemu.h:481:31: note: in expansion of macro > ‘__get_user_e’ > # define __get_user(x, hptr) __get_user_e(x, hptr, be) > ^~~~~~~~~~~~ > /source/qemu/linux-user/signal.c:2209:9: note: in expansion of macro > ‘__get_user’ > __get_user(float64_val(env->vfp.regs[i]), > &vfpframe->ufp.fpregs[i]); > ^~~~~~~~~~ > /source/qemu/linux-user/qemu.h:477:13: error: left-hand operand of comma > expression has no effect [-Werror=unused-value] > (hptr)), (void)0) > ^ > /source/qemu/linux-user/qemu.h:481:31: note: in expansion of macro > ‘__get_user_e’ > # define __get_user(x, hptr) __get_user_e(x, hptr, be) > ^~~~~~~~~~~~ > /source/qemu/linux-user/signal.c:2209:9: note: in expansion of macro > ‘__get_user’ > __get_user(float64_val(env->vfp.regs[i]), > &vfpframe->ufp.fpregs[i]); > ^~~~~~~~~~ > cc1: all warnings being treated as errors > /source/qemu/rules.mak:66: recipe for target 'linux-user/signal.o' failed > > CC linux-user/arm/nwfpe/fpa11_cpdt.o > ... > /source/qemu/linux-user/arm/nwfpe/fpa11_cpdt.c:37:4: note: in expansion > of macro ‘get_user_u32’ > get_user_u32(float32_val(fpa11->fpreg[Fn].fSingle), addr); > ^~~~~~~~~~~~ > /source/qemu/linux-user/qemu.h:515:13: error: lvalue required as left > operand of assignment > (x) = 0; \ > ^ > /source/qemu/linux-user/qemu.h:536:32: note: in expansion of macro > ‘get_user’ > #define get_user_u32(x, gaddr) get_user((x), (gaddr), uint32_t) > ^~~~~~~~ > /source/qemu/linux-user/arm/nwfpe/fpa11_cpdt.c:37:4: note: in expansion > of macro ‘get_user_u32’ > get_user_u32(float32_val(fpa11->fpreg[Fn].fSingle), addr); > ^~~~~~~~~~~~ > These series doesn't fix all the problems, only the easiest to fix... for this one, you need: diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c index 48184c380d..0c273d616a 100644 --- a/migration/vmstate-types.c +++ b/migration/vmstate-types.c @@ -425,7 +425,7 @@ static int get_float64(QEMUFile *f, void *pv, size_t size, static int put_float64(QEMUFile *f, void *pv, size_t size, VMStateField *field, QJSON *vmdesc) { - uint64_t *v = pv; + float64 *v = pv; qemu_put_be64(f, float64_val(*v)); return 0; Thanks, Laurent ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions 2017-11-04 8:55 ` Laurent Vivier @ 2017-11-04 16:18 ` Philippe Mathieu-Daudé 2017-11-07 14:52 ` Philippe Mathieu-Daudé 0 siblings, 1 reply; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-04 16:18 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno On 11/04/2017 05:55 AM, Laurent Vivier wrote: > Le 03/11/2017 à 22:51, Philippe Mathieu-Daudé a écrit : >>> On 11/03/2017 05:26 PM, Laurent Vivier wrote: >>>> This series fixes some errors found by >>>> enabling USE_SOFTFLOAT_STRUCT_TYPES. >> [...] >>> >>> I'm getting those errors: >>> >>> $ make subdir-arm-softmmu -j2 >>> >>> /source/qemu/migration/vmstate-types.c:430:5: error: conversion to >>> non-scalar type requested >>> qemu_put_be64(f, float64_val(*v)); >>> ^~~~~~~~~~~~~ >>> make: *** [migration/vmstate-types.o] Error 1 [...] > > These series doesn't fix all the problems, only the easiest to fix... > > for this one, you need: > > diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c > index 48184c380d..0c273d616a 100644 > --- a/migration/vmstate-types.c > +++ b/migration/vmstate-types.c > @@ -425,7 +425,7 @@ static int get_float64(QEMUFile *f, void *pv, size_t > size, > static int put_float64(QEMUFile *f, void *pv, size_t size, VMStateField > *field, > QJSON *vmdesc) > { > - uint64_t *v = pv; > + float64 *v = pv; > > qemu_put_be64(f, float64_val(*v)); > return 0; If you respin with this one you can add my Reviewed-by + Tested-by. Another error: $ make subdir-aarch64-softmmu [...] CC target/arm/helper-a64.o /source/qemu/target/arm/helper-a64.c: In function ‘helper_simd_tbl’: /source/qemu/target/arm/helper-a64.c:162:38: error: incompatible type for argument 1 of ‘extract64’ uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8); ^~~ In file included from /source/qemu/include/qemu/bitmap.h:16:0, from /source/qemu/include/hw/qdev-core.h:6, from /source/qemu/include/qom/cpu.h:23, from /source/qemu/target/arm/cpu-qom.h:23, from /source/qemu/target/arm/cpu.h:39, from /source/qemu/target/arm/helper-a64.c:21: /source/qemu/include/qemu/bitops.h:316:24: note: expected ‘uint64_t {aka long unsigned int}’ but argument is of type ‘float64 {aka struct <anonymous>}’ static inline uint64_t extract64(uint64_t value, int start, int length) ^~~~~~~~~ make: *** [target/arm/helper-a64.o] Error 1 ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions 2017-11-04 16:18 ` Philippe Mathieu-Daudé @ 2017-11-07 14:52 ` Philippe Mathieu-Daudé 0 siblings, 0 replies; 16+ messages in thread From: Philippe Mathieu-Daudé @ 2017-11-07 14:52 UTC (permalink / raw) To: Laurent Vivier, qemu-devel Cc: Peter Maydell, Bastian Koppelmann, qemu-arm, Stafford Horne, Aurelien Jarno On 11/04/2017 01:18 PM, Philippe Mathieu-Daudé wrote: > On 11/04/2017 05:55 AM, Laurent Vivier wrote: >> Le 03/11/2017 à 22:51, Philippe Mathieu-Daudé a écrit : >>>> On 11/03/2017 05:26 PM, Laurent Vivier wrote: >>>>> This series fixes some errors found by >>>>> enabling USE_SOFTFLOAT_STRUCT_TYPES. >>> [...] >>>> >>>> I'm getting those errors: >>>> >>>> $ make subdir-arm-softmmu -j2 >>>> >>>> /source/qemu/migration/vmstate-types.c:430:5: error: conversion to >>>> non-scalar type requested >>>> qemu_put_be64(f, float64_val(*v)); >>>> ^~~~~~~~~~~~~ >>>> make: *** [migration/vmstate-types.o] Error 1 > [...] >> >> These series doesn't fix all the problems, only the easiest to fix... >> >> for this one, you need: >> >> diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c >> index 48184c380d..0c273d616a 100644 >> --- a/migration/vmstate-types.c >> +++ b/migration/vmstate-types.c >> @@ -425,7 +425,7 @@ static int get_float64(QEMUFile *f, void *pv, size_t >> size, >> static int put_float64(QEMUFile *f, void *pv, size_t size, VMStateField >> *field, >> QJSON *vmdesc) >> { >> - uint64_t *v = pv; >> + float64 *v = pv; >> >> qemu_put_be64(f, float64_val(*v)); >> return 0; > > If you respin with this one you can add my Reviewed-by + Tested-by. > > Another error: > > $ make subdir-aarch64-softmmu > [...] > CC target/arm/helper-a64.o > /source/qemu/target/arm/helper-a64.c: In function ‘helper_simd_tbl’: > /source/qemu/target/arm/helper-a64.c:162:38: error: incompatible type > for argument 1 of ‘extract64’ > uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8); > ^~~ > In file included from /source/qemu/include/qemu/bitmap.h:16:0, > from /source/qemu/include/hw/qdev-core.h:6, > from /source/qemu/include/qom/cpu.h:23, > from /source/qemu/target/arm/cpu-qom.h:23, > from /source/qemu/target/arm/cpu.h:39, > from /source/qemu/target/arm/helper-a64.c:21: > /source/qemu/include/qemu/bitops.h:316:24: note: expected ‘uint64_t {aka > long unsigned int}’ but argument is of type ‘float64 {aka struct > <anonymous>}’ > static inline uint64_t extract64(uint64_t value, int start, int length) > ^~~~~~~~~ > make: *** [target/arm/helper-a64.o] Error 1 OK with: - uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8); + uint64_t val = extract64(float64_val(env->vfp.regs[elt]), bitidx, 8); ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-11-07 14:55 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2017-11-03 20:26 [Qemu-devel] [PATCH 0/4] softfloat: fix some helper definitions Laurent Vivier 2017-11-03 20:26 ` [Qemu-devel] [PATCH 1/4] arm: fix float64 " Laurent Vivier 2017-11-07 14:54 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 2017-11-03 20:26 ` [Qemu-devel] [PATCH 2/4] openrisc: fix float32 and " Laurent Vivier 2017-11-04 21:20 ` Stafford Horne 2017-11-05 14:39 ` Laurent Vivier 2017-11-07 10:59 ` Stafford Horne 2017-11-07 14:38 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 2017-11-03 20:26 ` [Qemu-devel] [PATCH 3/4] tricore: use make_float32() and float32_val() Laurent Vivier 2017-11-07 14:40 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé 2017-11-03 20:26 ` [Qemu-devel] [PATCH 4/4] softfloat: use floatXX_val() in XX_minmax() Laurent Vivier 2017-11-03 21:27 ` [Qemu-devel] [Qemu-arm] [PATCH 0/4] softfloat: fix some helper definitions Philippe Mathieu-Daudé 2017-11-03 21:51 ` Philippe Mathieu-Daudé 2017-11-04 8:55 ` Laurent Vivier 2017-11-04 16:18 ` Philippe Mathieu-Daudé 2017-11-07 14:52 ` Philippe Mathieu-Daudé
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